2 * Frame buffer driver for Trident Blade and Image series
4 * Copyright 2001, 2002 - Jani Monoses <jani@iv.ro>
7 * CREDITS:(in order of appearance)
8 * skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video
9 * Special thanks ;) to Mattia Crivellini <tia@mclink.it>
10 * much inspired by the XFree86 4.x Trident driver sources
11 * by Alan Hourihane the FreeVGA project
12 * Francesco Salvestrini <salvestrini@users.sf.net> XP support,
15 * timing value tweaking so it looks good on every monitor in every mode
19 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/pci.h>
24 #include <linux/delay.h>
25 #include <video/vga.h>
26 #include <video/trident.h>
28 #define VERSION "0.7.9-NEWAPI"
30 struct tridentfb_par {
31 void __iomem *io_virt; /* iospace virtual memory address */
35 void (*init_accel) (struct tridentfb_par *, int, int);
36 void (*wait_engine) (struct tridentfb_par *);
38 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
40 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
43 static unsigned char eng_oper; /* engine operation... */
44 static struct fb_ops tridentfb_ops;
46 static struct fb_fix_screeninfo tridentfb_fix = {
48 .type = FB_TYPE_PACKED_PIXELS,
50 .visual = FB_VISUAL_PSEUDOCOLOR,
51 .accel = FB_ACCEL_NONE,
54 /* defaults which are normally overriden by user values */
57 static char *mode_option __devinitdata = "640x480";
58 static int bpp __devinitdata = 8;
60 static int noaccel __devinitdata;
65 static int fp __devinitdata;
66 static int crt __devinitdata;
68 static int memsize __devinitdata;
69 static int memdiff __devinitdata;
72 module_param(mode_option, charp, 0);
73 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
74 module_param_named(mode, mode_option, charp, 0);
75 MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)");
76 module_param(bpp, int, 0);
77 module_param(center, int, 0);
78 module_param(stretch, int, 0);
79 module_param(noaccel, int, 0);
80 module_param(memsize, int, 0);
81 module_param(memdiff, int, 0);
82 module_param(nativex, int, 0);
83 module_param(fp, int, 0);
84 MODULE_PARM_DESC(fp, "Define if flatpanel is connected");
85 module_param(crt, int, 0);
86 MODULE_PARM_DESC(crt, "Define if CRT is connected");
88 static int is_blade(int id)
90 return (id == BLADE3D) ||
91 (id == CYBERBLADEE4) ||
92 (id == CYBERBLADEi7) ||
93 (id == CYBERBLADEi7D) ||
94 (id == CYBERBLADEi1) ||
95 (id == CYBERBLADEi1D) ||
96 (id == CYBERBLADEAi1) ||
97 (id == CYBERBLADEAi1D);
100 static int is_xp(int id)
102 return (id == CYBERBLADEXPAi1) ||
103 (id == CYBERBLADEXPm8) ||
104 (id == CYBERBLADEXPm16);
107 static int is3Dchip(int id)
109 return ((id == BLADE3D) || (id == CYBERBLADEE4) ||
110 (id == CYBERBLADEi7) || (id == CYBERBLADEi7D) ||
111 (id == CYBER9397) || (id == CYBER9397DVD) ||
112 (id == CYBER9520) || (id == CYBER9525DVD) ||
113 (id == IMAGE975) || (id == IMAGE985) ||
114 (id == CYBERBLADEi1) || (id == CYBERBLADEi1D) ||
115 (id == CYBERBLADEAi1) || (id == CYBERBLADEAi1D) ||
116 (id == CYBERBLADEXPm8) || (id == CYBERBLADEXPm16) ||
117 (id == CYBERBLADEXPAi1));
120 static int iscyber(int id)
136 case CYBERBLADEXPAi1:
144 case CYBERBLADEi7: /* VIA MPV4 integrated version */
147 /* case CYBERBLDAEXPm8: Strange */
148 /* case CYBERBLDAEXPm16: Strange */
153 static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg)
155 fb_writeb(val, p->io_virt + reg);
158 static inline u8 t_inb(struct tridentfb_par *p, u16 reg)
160 return fb_readb(p->io_virt + reg);
163 static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v)
165 fb_writel(v, par->io_virt + r);
168 static inline u32 readmmr(struct tridentfb_par *par, u16 r)
170 return fb_readl(par->io_virt + r);
174 * Blade specific acceleration.
177 #define point(x, y) ((y) << 16 | (x))
189 static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp)
191 int v1 = (pitch >> 3) << 20;
208 v2 = v1 | (tmp << 29);
209 writemmr(par, 0x21C0, v2);
210 writemmr(par, 0x21C4, v2);
211 writemmr(par, 0x21B8, v2);
212 writemmr(par, 0x21BC, v2);
213 writemmr(par, 0x21D0, v1);
214 writemmr(par, 0x21D4, v1);
215 writemmr(par, 0x21C8, v1);
216 writemmr(par, 0x21CC, v1);
217 writemmr(par, 0x216C, 0);
220 static void blade_wait_engine(struct tridentfb_par *par)
222 while (readmmr(par, STA) & 0xFA800000) ;
225 static void blade_fill_rect(struct tridentfb_par *par,
226 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
228 writemmr(par, CLR, c);
229 writemmr(par, ROP, rop ? 0x66 : ROP_S);
230 writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2);
232 writemmr(par, DR1, point(x, y));
233 writemmr(par, DR2, point(x + w - 1, y + h - 1));
236 static void blade_copy_rect(struct tridentfb_par *par,
237 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
242 s2 = point(x1 + w - 1, y1 + h - 1);
244 d2 = point(x2 + w - 1, y2 + h - 1);
246 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
249 writemmr(par, ROP, ROP_S);
250 writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction);
252 writemmr(par, SR1, direction ? s2 : s1);
253 writemmr(par, SR2, direction ? s1 : s2);
254 writemmr(par, DR1, direction ? d2 : d1);
255 writemmr(par, DR2, direction ? d1 : d2);
259 * BladeXP specific acceleration functions
263 #define masked_point(x, y) ((y & 0xffff)<<16|(x & 0xffff))
265 static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp)
285 switch (pitch << (bpp >> 3)) {
301 t_outb(par, x, 0x2125);
321 writemmr(par, 0x2154, v1);
322 writemmr(par, 0x2150, v1);
323 t_outb(par, 3, 0x2126);
326 static void xp_wait_engine(struct tridentfb_par *par)
334 busy = t_inb(par, STA) & 0x80;
338 if (count == 10000000) {
344 t_outb(par, 0x00, 0x2120);
351 static void xp_fill_rect(struct tridentfb_par *par,
352 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
354 writemmr(par, 0x2127, ROP_P);
355 writemmr(par, 0x2158, c);
356 writemmr(par, 0x2128, 0x4000);
357 writemmr(par, 0x2140, masked_point(h, w));
358 writemmr(par, 0x2138, masked_point(y, x));
359 t_outb(par, 0x01, 0x2124);
360 t_outb(par, eng_oper, 0x2125);
363 static void xp_copy_rect(struct tridentfb_par *par,
364 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
367 u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
371 if ((x1 < x2) && (y1 == y2)) {
389 writemmr(par, 0x2128, direction);
390 t_outb(par, ROP_S, 0x2127);
391 writemmr(par, 0x213C, masked_point(y1_tmp, x1_tmp));
392 writemmr(par, 0x2138, masked_point(y2_tmp, x2_tmp));
393 writemmr(par, 0x2140, masked_point(h, w));
394 t_outb(par, 0x01, 0x2124);
398 * Image specific acceleration functions
400 static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp)
418 writemmr(par, 0x2120, 0xF0000000);
419 writemmr(par, 0x2120, 0x40000000 | tmp);
420 writemmr(par, 0x2120, 0x80000000);
421 writemmr(par, 0x2144, 0x00000000);
422 writemmr(par, 0x2148, 0x00000000);
423 writemmr(par, 0x2150, 0x00000000);
424 writemmr(par, 0x2154, 0x00000000);
425 writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch);
426 writemmr(par, 0x216C, 0x00000000);
427 writemmr(par, 0x2170, 0x00000000);
428 writemmr(par, 0x217C, 0x00000000);
429 writemmr(par, 0x2120, 0x10000000);
430 writemmr(par, 0x2130, (2047 << 16) | 2047);
433 static void image_wait_engine(struct tridentfb_par *par)
435 while (readmmr(par, 0x2164) & 0xF0000000) ;
438 static void image_fill_rect(struct tridentfb_par *par,
439 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
441 writemmr(par, 0x2120, 0x80000000);
442 writemmr(par, 0x2120, 0x90000000 | ROP_S);
444 writemmr(par, 0x2144, c);
446 writemmr(par, DR1, point(x, y));
447 writemmr(par, DR2, point(x + w - 1, y + h - 1));
449 writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9);
452 static void image_copy_rect(struct tridentfb_par *par,
453 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
458 s2 = point(x1 + w - 1, y1 + h - 1);
460 d2 = point(x2 + w - 1, y2 + h - 1);
462 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
465 writemmr(par, 0x2120, 0x80000000);
466 writemmr(par, 0x2120, 0x90000000 | ROP_S);
468 writemmr(par, SR1, direction ? s2 : s1);
469 writemmr(par, SR2, direction ? s1 : s2);
470 writemmr(par, DR1, direction ? d2 : d1);
471 writemmr(par, DR2, direction ? d1 : d2);
472 writemmr(par, 0x2124,
473 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction);
477 * Accel functions called by the upper layers
479 #ifdef CONFIG_FB_TRIDENT_ACCEL
480 static void tridentfb_fillrect(struct fb_info *info,
481 const struct fb_fillrect *fr)
483 struct tridentfb_par *par = info->par;
484 int bpp = info->var.bits_per_pixel;
495 col = ((u32 *)(info->pseudo_palette))[fr->color];
498 col = ((u32 *)(info->pseudo_palette))[fr->color];
502 par->fill_rect(par, fr->dx, fr->dy, fr->width,
503 fr->height, col, fr->rop);
504 par->wait_engine(par);
506 static void tridentfb_copyarea(struct fb_info *info,
507 const struct fb_copyarea *ca)
509 struct tridentfb_par *par = info->par;
511 par->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy,
512 ca->width, ca->height);
513 par->wait_engine(par);
515 #else /* !CONFIG_FB_TRIDENT_ACCEL */
516 #define tridentfb_fillrect cfb_fillrect
517 #define tridentfb_copyarea cfb_copyarea
518 #endif /* CONFIG_FB_TRIDENT_ACCEL */
522 * Hardware access functions
525 static inline unsigned char read3X4(struct tridentfb_par *par, int reg)
527 return vga_mm_rcrt(par->io_virt, reg);
530 static inline void write3X4(struct tridentfb_par *par, int reg,
533 vga_mm_wcrt(par->io_virt, reg, val);
536 static inline unsigned char read3CE(struct tridentfb_par *par,
539 return vga_mm_rgfx(par->io_virt, reg);
542 static inline void writeAttr(struct tridentfb_par *par, int reg,
545 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
546 vga_mm_wattr(par->io_virt, reg, val);
549 static inline void write3CE(struct tridentfb_par *par, int reg,
552 vga_mm_wgfx(par->io_virt, reg, val);
555 static void enable_mmio(void)
560 /* Unprotect registers */
561 vga_io_wseq(NewMode1, 0x80);
565 outb(inb(0x3D5) | 0x01, 0x3D5);
568 static void disable_mmio(struct tridentfb_par *par)
571 vga_mm_rseq(par->io_virt, 0x0B);
573 /* Unprotect registers */
574 vga_mm_wseq(par->io_virt, NewMode1, 0x80);
577 t_outb(par, PCIReg, 0x3D4);
578 t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5);
581 static void crtc_unlock(struct tridentfb_par *par)
583 write3X4(par, VGA_CRTC_V_SYNC_END,
584 read3X4(par, VGA_CRTC_V_SYNC_END) & 0x7F);
587 /* Return flat panel's maximum x resolution */
588 static int __devinit get_nativex(struct tridentfb_par *par)
595 tmp = (read3CE(par, VertStretch) >> 4) & 3;
616 output("%dx%d flat panel found\n", x, y);
621 static void set_lwidth(struct tridentfb_par *par, int width)
623 write3X4(par, VGA_CRTC_OFFSET, width & 0xFF);
624 write3X4(par, AddColReg,
625 (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4));
628 /* For resolutions smaller than FP resolution stretch */
629 static void screen_stretch(struct tridentfb_par *par)
631 if (par->chip_id != CYBERBLADEXPAi1)
632 write3CE(par, BiosReg, 0);
634 write3CE(par, BiosReg, 8);
635 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1);
636 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1);
639 /* For resolutions smaller than FP resolution center */
640 static void screen_center(struct tridentfb_par *par)
642 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80);
643 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80);
646 /* Address of first shown pixel in display memory */
647 static void set_screen_start(struct tridentfb_par *par, int base)
650 write3X4(par, VGA_CRTC_START_LO, base & 0xFF);
651 write3X4(par, VGA_CRTC_START_HI, (base & 0xFF00) >> 8);
652 tmp = read3X4(par, CRTCModuleTest) & 0xDF;
653 write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11));
654 tmp = read3X4(par, CRTHiOrd) & 0xF8;
655 write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17));
658 /* Set dotclock frequency */
659 static void set_vclk(struct tridentfb_par *par, unsigned long freq)
662 unsigned long f, fi, d, di;
663 unsigned char lo = 0, hi = 0;
666 for (k = 2; k >= 0; k--)
667 for (m = 0; m < 63; m++)
668 for (n = 0; n < 128; n++) {
669 fi = ((14318l * (n + 8)) / (m + 2)) >> k;
670 if ((di = abs(fi - freq)) < d) {
679 if (is3Dchip(par->chip_id)) {
680 vga_mm_wseq(par->io_virt, ClockHigh, hi);
681 vga_mm_wseq(par->io_virt, ClockLow, lo);
686 debug("VCLK = %X %X\n", hi, lo);
689 /* Set number of lines for flat panels*/
690 static void set_number_of_lines(struct tridentfb_par *par, int lines)
692 int tmp = read3CE(par, CyberEnhance) & 0x8F;
695 else if (lines > 768)
697 else if (lines > 600)
699 else if (lines > 480)
701 write3CE(par, CyberEnhance, tmp);
705 * If we see that FP is active we assume we have one.
706 * Otherwise we have a CRT display. User can override.
708 static int __devinit is_flatpanel(struct tridentfb_par *par)
712 if (crt || !iscyber(par->chip_id))
714 return (read3CE(par, FPConfig) & 0x10) ? 1 : 0;
717 /* Try detecting the video memory size */
718 static unsigned int __devinit get_memsize(struct tridentfb_par *par)
720 unsigned char tmp, tmp2;
723 /* If memory size provided by user */
727 switch (par->chip_id) {
732 tmp = read3X4(par, SPR) & 0x0F;
748 k = 10 * Mb; /* XP */
754 k = 12 * Mb; /* XP */
757 k = 14 * Mb; /* XP */
760 k = 16 * Mb; /* XP */
764 tmp2 = vga_mm_rseq(par->io_virt, 0xC1);
794 output("framebuffer size = %d Kb\n", k / Kb);
798 /* See if we can handle the video mode described in var */
799 static int tridentfb_check_var(struct fb_var_screeninfo *var,
800 struct fb_info *info)
802 struct tridentfb_par *par = info->par;
803 int bpp = var->bits_per_pixel;
806 /* check color depth */
808 bpp = var->bits_per_pixel = 32;
809 /* check whether resolution fits on panel and in memory */
810 if (par->flatpanel && nativex && var->xres > nativex)
812 if (var->xres * var->yres_virtual * bpp / 8 > info->fix.smem_len)
818 var->green.offset = 0;
819 var->blue.offset = 0;
821 var->green.length = 6;
822 var->blue.length = 6;
825 var->red.offset = 11;
826 var->green.offset = 5;
827 var->blue.offset = 0;
829 var->green.length = 6;
830 var->blue.length = 5;
833 var->red.offset = 16;
834 var->green.offset = 8;
835 var->blue.offset = 0;
837 var->green.length = 8;
838 var->blue.length = 8;
849 /* Pan the display */
850 static int tridentfb_pan_display(struct fb_var_screeninfo *var,
851 struct fb_info *info)
853 struct tridentfb_par *par = info->par;
857 offset = (var->xoffset + (var->yoffset * var->xres))
858 * var->bits_per_pixel / 32;
859 info->var.xoffset = var->xoffset;
860 info->var.yoffset = var->yoffset;
861 set_screen_start(par, offset);
866 static void shadowmode_on(struct tridentfb_par *par)
868 write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81);
871 static void shadowmode_off(struct tridentfb_par *par)
873 write3CE(par, CyberControl, read3CE(par, CyberControl) & 0x7E);
876 /* Set the hardware to the requested video mode */
877 static int tridentfb_set_par(struct fb_info *info)
879 struct tridentfb_par *par = (struct tridentfb_par *)(info->par);
880 u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend;
881 u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend;
882 struct fb_var_screeninfo *var = &info->var;
883 int bpp = var->bits_per_pixel;
888 hdispend = var->xres / 8 - 1;
889 hsyncstart = (var->xres + var->right_margin) / 8;
890 hsyncend = var->hsync_len / 8;
892 (var->xres + var->left_margin + var->right_margin +
893 var->hsync_len) / 8 - 10;
894 hblankstart = hdispend + 1;
895 hblankend = htotal + 5;
897 vdispend = var->yres - 1;
898 vsyncstart = var->yres + var->lower_margin;
899 vsyncend = var->vsync_len;
900 vtotal = var->upper_margin + vsyncstart + vsyncend - 2;
901 vblankstart = var->yres;
902 vblankend = vtotal + 2;
905 write3CE(par, CyberControl, 8);
907 if (par->flatpanel && var->xres < nativex) {
909 * on flat panels with native size larger
910 * than requested resolution decide whether
911 * we stretch or center
913 t_outb(par, 0xEB, VGA_MIS_W);
923 t_outb(par, 0x2B, VGA_MIS_W);
924 write3CE(par, CyberControl, 8);
927 /* vertical timing values */
928 write3X4(par, VGA_CRTC_V_TOTAL, vtotal & 0xFF);
929 write3X4(par, VGA_CRTC_V_DISP_END, vdispend & 0xFF);
930 write3X4(par, VGA_CRTC_V_SYNC_START, vsyncstart & 0xFF);
931 write3X4(par, VGA_CRTC_V_SYNC_END, (vsyncend & 0x0F));
932 write3X4(par, VGA_CRTC_V_BLANK_START, vblankstart & 0xFF);
933 write3X4(par, VGA_CRTC_V_BLANK_END, 0 /* p->vblankend & 0xFF */);
935 /* horizontal timing values */
936 write3X4(par, VGA_CRTC_H_TOTAL, htotal & 0xFF);
937 write3X4(par, VGA_CRTC_H_DISP, hdispend & 0xFF);
938 write3X4(par, VGA_CRTC_H_SYNC_START, hsyncstart & 0xFF);
939 write3X4(par, VGA_CRTC_H_SYNC_END,
940 (hsyncend & 0x1F) | ((hblankend & 0x20) << 2));
941 write3X4(par, VGA_CRTC_H_BLANK_START, hblankstart & 0xFF);
942 write3X4(par, VGA_CRTC_H_BLANK_END, 0 /* (p->hblankend & 0x1F) */);
944 /* higher bits of vertical timing values */
946 if (vtotal & 0x100) tmp |= 0x01;
947 if (vdispend & 0x100) tmp |= 0x02;
948 if (vsyncstart & 0x100) tmp |= 0x04;
949 if (vblankstart & 0x100) tmp |= 0x08;
951 if (vtotal & 0x200) tmp |= 0x20;
952 if (vdispend & 0x200) tmp |= 0x40;
953 if (vsyncstart & 0x200) tmp |= 0x80;
954 write3X4(par, VGA_CRTC_OVERFLOW, tmp);
956 tmp = read3X4(par, CRTHiOrd) | 0x08; /* line compare bit 10 */
957 if (vtotal & 0x400) tmp |= 0x80;
958 if (vblankstart & 0x400) tmp |= 0x40;
959 if (vsyncstart & 0x400) tmp |= 0x20;
960 if (vdispend & 0x400) tmp |= 0x10;
961 write3X4(par, CRTHiOrd, tmp);
964 if (htotal & 0x800) tmp |= 0x800 >> 11;
965 if (hblankstart & 0x800) tmp |= 0x800 >> 7;
966 write3X4(par, HorizOverflow, tmp);
969 if (vblankstart & 0x200) tmp |= 0x20;
970 //FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */
971 write3X4(par, VGA_CRTC_MAX_SCAN, tmp);
973 write3X4(par, VGA_CRTC_LINE_COMPARE, 0xFF);
974 write3X4(par, VGA_CRTC_PRESET_ROW, 0);
975 write3X4(par, VGA_CRTC_MODE, 0xC3);
977 write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */
979 tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80;
980 /* enable access extended memory */
981 write3X4(par, CRTCModuleTest, tmp);
983 /* enable GE for text acceleration */
984 write3X4(par, GraphEngReg, 0x80);
986 #ifdef CONFIG_FB_TRIDENT_ACCEL
987 par->init_accel(par, info->var.xres, bpp);
1005 write3X4(par, PixelBusReg, tmp);
1008 if (iscyber(par->chip_id))
1010 write3X4(par, DRAMControl, tmp); /* both IO, linear enable */
1012 write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40);
1013 write3X4(par, Performance, 0x92);
1014 /* MMIO & PCI read and write burst enable */
1015 write3X4(par, PCIReg, 0x07);
1017 /* convert from picoseconds to kHz */
1018 vclk = PICOS2KHZ(info->var.pixclock);
1021 set_vclk(par, vclk);
1023 vga_mm_wseq(par->io_virt, 0, 3);
1024 vga_mm_wseq(par->io_virt, 1, 1); /* set char clock 8 dots wide */
1025 /* enable 4 maps because needed in chain4 mode */
1026 vga_mm_wseq(par->io_virt, 2, 0x0F);
1027 vga_mm_wseq(par->io_virt, 3, 0);
1028 vga_mm_wseq(par->io_virt, 4, 0x0E); /* memory mode enable bitmaps ?? */
1030 /* divide clock by 2 if 32bpp chain4 mode display and CPU path */
1031 write3CE(par, MiscExtFunc, (bpp == 32) ? 0x1A : 0x12);
1032 write3CE(par, 0x5, 0x40); /* no CGA compat, allow 256 col */
1033 write3CE(par, 0x6, 0x05); /* graphics mode */
1034 write3CE(par, 0x7, 0x0F); /* planes? */
1036 if (par->chip_id == CYBERBLADEXPAi1) {
1037 /* This fixes snow-effect in 32 bpp */
1038 write3X4(par, VGA_CRTC_H_SYNC_START, 0x84);
1041 /* graphics mode and support 256 color modes */
1042 writeAttr(par, 0x10, 0x41);
1043 writeAttr(par, 0x12, 0x0F); /* planes */
1044 writeAttr(par, 0x13, 0); /* horizontal pel panning */
1047 for (tmp = 0; tmp < 0x10; tmp++)
1048 writeAttr(par, tmp, tmp);
1049 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
1050 t_outb(par, 0x20, VGA_ATT_W); /* enable attr */
1068 t_inb(par, VGA_PEL_IW);
1069 t_inb(par, VGA_PEL_MSK);
1070 t_inb(par, VGA_PEL_MSK);
1071 t_inb(par, VGA_PEL_MSK);
1072 t_inb(par, VGA_PEL_MSK);
1073 t_outb(par, tmp, VGA_PEL_MSK);
1074 t_inb(par, VGA_PEL_IW);
1077 set_number_of_lines(par, info->var.yres);
1078 set_lwidth(par, info->var.xres * bpp / (4 * 16));
1079 info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1080 info->fix.line_length = info->var.xres * (bpp >> 3);
1081 info->cmap.len = (bpp == 8) ? 256 : 16;
1086 /* Set one color register */
1087 static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1088 unsigned blue, unsigned transp,
1089 struct fb_info *info)
1091 int bpp = info->var.bits_per_pixel;
1092 struct tridentfb_par *par = info->par;
1094 if (regno >= info->cmap.len)
1098 t_outb(par, 0xFF, VGA_PEL_MSK);
1099 t_outb(par, regno, VGA_PEL_IW);
1101 t_outb(par, red >> 10, VGA_PEL_D);
1102 t_outb(par, green >> 10, VGA_PEL_D);
1103 t_outb(par, blue >> 10, VGA_PEL_D);
1105 } else if (regno < 16) {
1106 if (bpp == 16) { /* RGB 565 */
1109 col = (red & 0xF800) | ((green & 0xFC00) >> 5) |
1110 ((blue & 0xF800) >> 11);
1112 ((u32 *)(info->pseudo_palette))[regno] = col;
1113 } else if (bpp == 32) /* ARGB 8888 */
1114 ((u32*)info->pseudo_palette)[regno] =
1115 ((transp & 0xFF00) << 16) |
1116 ((red & 0xFF00) << 8) |
1117 ((green & 0xFF00)) |
1118 ((blue & 0xFF00) >> 8);
1121 /* debug("exit\n"); */
1125 /* Try blanking the screen.For flat panels it does nothing */
1126 static int tridentfb_blank(int blank_mode, struct fb_info *info)
1128 unsigned char PMCont, DPMSCont;
1129 struct tridentfb_par *par = info->par;
1134 t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */
1135 PMCont = t_inb(par, 0x83C6) & 0xFC;
1136 DPMSCont = read3CE(par, PowerStatus) & 0xFC;
1137 switch (blank_mode) {
1138 case FB_BLANK_UNBLANK:
1139 /* Screen: On, HSync: On, VSync: On */
1140 case FB_BLANK_NORMAL:
1141 /* Screen: Off, HSync: On, VSync: On */
1145 case FB_BLANK_HSYNC_SUSPEND:
1146 /* Screen: Off, HSync: Off, VSync: On */
1150 case FB_BLANK_VSYNC_SUSPEND:
1151 /* Screen: Off, HSync: On, VSync: Off */
1155 case FB_BLANK_POWERDOWN:
1156 /* Screen: Off, HSync: Off, VSync: Off */
1162 write3CE(par, PowerStatus, DPMSCont);
1163 t_outb(par, 4, 0x83C8);
1164 t_outb(par, PMCont, 0x83C6);
1168 /* let fbcon do a softblank for us */
1169 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1172 static struct fb_ops tridentfb_ops = {
1173 .owner = THIS_MODULE,
1174 .fb_setcolreg = tridentfb_setcolreg,
1175 .fb_pan_display = tridentfb_pan_display,
1176 .fb_blank = tridentfb_blank,
1177 .fb_check_var = tridentfb_check_var,
1178 .fb_set_par = tridentfb_set_par,
1179 .fb_fillrect = tridentfb_fillrect,
1180 .fb_copyarea = tridentfb_copyarea,
1181 .fb_imageblit = cfb_imageblit,
1184 static int __devinit trident_pci_probe(struct pci_dev *dev,
1185 const struct pci_device_id *id)
1188 unsigned char revision;
1189 struct fb_info *info;
1190 struct tridentfb_par *default_par;
1195 err = pci_enable_device(dev);
1199 info = framebuffer_alloc(sizeof(struct tridentfb_par), &dev->dev);
1202 default_par = info->par;
1204 chip_id = id->device;
1206 if (chip_id == CYBERBLADEi1)
1207 output("*** Please do use cyblafb, Cyberblade/i1 support "
1208 "will soon be removed from tridentfb!\n");
1211 /* If PCI id is 0x9660 then further detect chip type */
1213 if (chip_id == TGUI9660) {
1214 revision = vga_io_rseq(RevisionID);
1219 chip_id = CYBER9397;
1222 chip_id = CYBER9397DVD;
1231 chip_id = CYBER9385;
1234 chip_id = CYBER9382;
1237 chip_id = CYBER9388;
1244 chip3D = is3Dchip(chip_id);
1246 if (is_xp(chip_id)) {
1247 default_par->init_accel = xp_init_accel;
1248 default_par->wait_engine = xp_wait_engine;
1249 default_par->fill_rect = xp_fill_rect;
1250 default_par->copy_rect = xp_copy_rect;
1251 } else if (is_blade(chip_id)) {
1252 default_par->init_accel = blade_init_accel;
1253 default_par->wait_engine = blade_wait_engine;
1254 default_par->fill_rect = blade_fill_rect;
1255 default_par->copy_rect = blade_copy_rect;
1257 default_par->init_accel = image_init_accel;
1258 default_par->wait_engine = image_wait_engine;
1259 default_par->fill_rect = image_fill_rect;
1260 default_par->copy_rect = image_copy_rect;
1263 default_par->chip_id = chip_id;
1265 /* acceleration is on by default for 3D chips */
1266 defaultaccel = chip3D && !noaccel;
1268 /* setup MMIO region */
1269 tridentfb_fix.mmio_start = pci_resource_start(dev, 1);
1270 tridentfb_fix.mmio_len = chip3D ? 0x20000 : 0x10000;
1272 if (!request_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len, "tridentfb")) {
1273 debug("request_region failed!\n");
1277 default_par->io_virt = ioremap_nocache(tridentfb_fix.mmio_start,
1278 tridentfb_fix.mmio_len);
1280 if (!default_par->io_virt) {
1281 debug("ioremap failed\n");
1288 /* setup framebuffer memory */
1289 tridentfb_fix.smem_start = pci_resource_start(dev, 0);
1290 tridentfb_fix.smem_len = get_memsize(default_par);
1292 if (!request_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len, "tridentfb")) {
1293 debug("request_mem_region failed!\n");
1294 disable_mmio(info->par);
1299 info->screen_base = ioremap_nocache(tridentfb_fix.smem_start,
1300 tridentfb_fix.smem_len);
1302 if (!info->screen_base) {
1303 debug("ioremap failed\n");
1308 output("%s board found\n", pci_name(dev));
1309 default_par->flatpanel = is_flatpanel(default_par);
1311 if (default_par->flatpanel)
1312 nativex = get_nativex(default_par);
1314 info->fix = tridentfb_fix;
1315 info->fbops = &tridentfb_ops;
1318 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1319 #ifdef CONFIG_FB_TRIDENT_ACCEL
1320 info->flags |= FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT;
1322 if (!fb_find_mode(&info->var, info,
1323 mode_option, NULL, 0, NULL, bpp)) {
1327 err = fb_alloc_cmap(&info->cmap, 256, 0);
1331 if (defaultaccel && default_par->init_accel)
1332 info->var.accel_flags |= FB_ACCELF_TEXT;
1334 info->var.accel_flags &= ~FB_ACCELF_TEXT;
1335 info->var.activate |= FB_ACTIVATE_NOW;
1336 info->device = &dev->dev;
1337 if (register_framebuffer(info) < 0) {
1338 printk(KERN_ERR "tridentfb: could not register Trident framebuffer\n");
1339 fb_dealloc_cmap(&info->cmap);
1343 output("fb%d: %s frame buffer device %dx%d-%dbpp\n",
1344 info->node, info->fix.id, info->var.xres,
1345 info->var.yres, info->var.bits_per_pixel);
1347 pci_set_drvdata(dev, info);
1351 if (info->screen_base)
1352 iounmap(info->screen_base);
1353 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1354 disable_mmio(info->par);
1356 if (default_par->io_virt)
1357 iounmap(default_par->io_virt);
1358 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1359 framebuffer_release(info);
1363 static void __devexit trident_pci_remove(struct pci_dev *dev)
1365 struct fb_info *info = pci_get_drvdata(dev);
1366 struct tridentfb_par *par = info->par;
1368 unregister_framebuffer(info);
1369 iounmap(par->io_virt);
1370 iounmap(info->screen_base);
1371 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1372 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1373 pci_set_drvdata(dev, NULL);
1374 framebuffer_release(info);
1377 /* List of boards that we are trying to support */
1378 static struct pci_device_id trident_devices[] = {
1379 {PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1380 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1381 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1382 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1383 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1384 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1385 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1386 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1387 {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1388 {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1389 {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1390 {PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1391 {PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1392 {PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1393 {PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1394 {PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1395 {PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1396 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1397 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1398 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1402 MODULE_DEVICE_TABLE(pci, trident_devices);
1404 static struct pci_driver tridentfb_pci_driver = {
1405 .name = "tridentfb",
1406 .id_table = trident_devices,
1407 .probe = trident_pci_probe,
1408 .remove = __devexit_p(trident_pci_remove)
1412 * Parse user specified options (`video=trident:')
1414 * video=trident:800x600,bpp=16,noaccel
1417 static int __init tridentfb_setup(char *options)
1420 if (!options || !*options)
1422 while ((opt = strsep(&options, ",")) != NULL) {
1425 if (!strncmp(opt, "noaccel", 7))
1427 else if (!strncmp(opt, "fp", 2))
1429 else if (!strncmp(opt, "crt", 3))
1431 else if (!strncmp(opt, "bpp=", 4))
1432 bpp = simple_strtoul(opt + 4, NULL, 0);
1433 else if (!strncmp(opt, "center", 6))
1435 else if (!strncmp(opt, "stretch", 7))
1437 else if (!strncmp(opt, "memsize=", 8))
1438 memsize = simple_strtoul(opt + 8, NULL, 0);
1439 else if (!strncmp(opt, "memdiff=", 8))
1440 memdiff = simple_strtoul(opt + 8, NULL, 0);
1441 else if (!strncmp(opt, "nativex=", 8))
1442 nativex = simple_strtoul(opt + 8, NULL, 0);
1450 static int __init tridentfb_init(void)
1453 char *option = NULL;
1455 if (fb_get_options("tridentfb", &option))
1457 tridentfb_setup(option);
1459 output("Trident framebuffer %s initializing\n", VERSION);
1460 return pci_register_driver(&tridentfb_pci_driver);
1463 static void __exit tridentfb_exit(void)
1465 pci_unregister_driver(&tridentfb_pci_driver);
1468 module_init(tridentfb_init);
1469 module_exit(tridentfb_exit);
1471 MODULE_AUTHOR("Jani Monoses <jani@iv.ro>");
1472 MODULE_DESCRIPTION("Framebuffer driver for Trident cards");
1473 MODULE_LICENSE("GPL");