2 * linux/drivers/video/vga16.c -- VGA 16-color framebuffer driver
4 * Copyright 1999 Ben Pfaff <pfaffben@debian.org> and Petr Vandrovec <VANDROVE@vc.cvut.cz>
5 * Based on VGA info at http://www.goodnet.com/~tinara/FreeVGA/home.htm
6 * Based on VESA framebuffer (c) 1998 Gerd Knorr <kraxel@goldbach.in-berlin.de>
8 * This file is subject to the terms and conditions of the GNU General
9 * Public License. See the file COPYING in the main directory of this
10 * archive for more details.
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/errno.h>
16 #include <linux/string.h>
18 #include <linux/tty.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
22 #include <linux/ioport.h>
23 #include <linux/init.h>
24 #include <linux/platform_device.h>
27 #include <video/vga.h>
29 #define GRAPHICS_ADDR_REG VGA_GFX_I /* Graphics address register. */
30 #define GRAPHICS_DATA_REG VGA_GFX_D /* Graphics data register. */
32 #define SET_RESET_INDEX VGA_GFX_SR_VALUE /* Set/Reset Register index. */
33 #define ENABLE_SET_RESET_INDEX VGA_GFX_SR_ENABLE /* Enable Set/Reset Register index. */
34 #define DATA_ROTATE_INDEX VGA_GFX_DATA_ROTATE /* Data Rotate Register index. */
35 #define GRAPHICS_MODE_INDEX VGA_GFX_MODE /* Graphics Mode Register index. */
36 #define BIT_MASK_INDEX VGA_GFX_BIT_MASK /* Bit Mask Register index. */
38 #define dac_reg (VGA_PEL_IW)
39 #define dac_val (VGA_PEL_D)
41 #define VGA_FB_PHYS 0xA0000
42 #define VGA_FB_PHYS_LEN 65536
49 /* --------------------------------------------------------------------- */
56 /* structure holding original VGA register settings when the
59 unsigned char SeqCtrlIndex; /* Sequencer Index reg. */
60 unsigned char CrtCtrlIndex; /* CRT-Contr. Index reg. */
61 unsigned char CrtMiscIO; /* Miscellaneous register */
62 unsigned char HorizontalTotal; /* CRT-Controller:00h */
63 unsigned char HorizDisplayEnd; /* CRT-Controller:01h */
64 unsigned char StartHorizRetrace;/* CRT-Controller:04h */
65 unsigned char EndHorizRetrace; /* CRT-Controller:05h */
66 unsigned char Overflow; /* CRT-Controller:07h */
67 unsigned char StartVertRetrace; /* CRT-Controller:10h */
68 unsigned char EndVertRetrace; /* CRT-Controller:11h */
69 unsigned char ModeControl; /* CRT-Controller:17h */
70 unsigned char ClockingMode; /* Seq-Controller:01h */
72 struct vgastate state;
74 int palette_blanked, vesa_blanked, mode, isVGA;
75 u8 misc, pel_msk, vss, clkdiv;
79 /* --------------------------------------------------------------------- */
81 static struct fb_var_screeninfo vga16fb_defined __initdata = {
87 .activate = FB_ACTIVATE_TEST,
97 .vmode = FB_VMODE_NONINTERLACED,
100 /* name should not depend on EGA/VGA */
101 static struct fb_fix_screeninfo vga16fb_fix __initdata = {
103 .smem_start = VGA_FB_PHYS,
104 .smem_len = VGA_FB_PHYS_LEN,
105 .type = FB_TYPE_VGA_PLANES,
106 .type_aux = FB_AUX_VGA_PLANES_VGA4,
107 .visual = FB_VISUAL_PSEUDOCOLOR,
110 .line_length = 640/8,
111 .accel = FB_ACCEL_NONE
114 /* The VGA's weird architecture often requires that we read a byte and
115 write a byte to the same location. It doesn't matter *what* byte
116 we write, however. This is because all the action goes on behind
117 the scenes in the VGA's 32-bit latch register, and reading and writing
118 video memory just invokes latch behavior.
120 To avoid race conditions (is this necessary?), reading and writing
121 the memory byte should be done with a single instruction. One
122 suitable instruction is the x86 bitwise OR. The following
123 read-modify-write routine should optimize to one such bitwise
125 static inline void rmw(volatile char __iomem *p)
131 /* Set the Graphics Mode Register, and return its previous value.
132 Bits 0-1 are write mode, bit 3 is read mode. */
133 static inline int setmode(int mode)
137 vga_io_w(GRAPHICS_ADDR_REG, GRAPHICS_MODE_INDEX);
138 oldmode = vga_io_r(GRAPHICS_DATA_REG);
139 vga_io_w(GRAPHICS_DATA_REG, mode);
143 /* Select the Bit Mask Register and return its value. */
144 static inline int selectmask(void)
146 return vga_io_rgfx(BIT_MASK_INDEX);
149 /* Set the value of the Bit Mask Register. It must already have been
150 selected with selectmask(). */
151 static inline void setmask(int mask)
153 vga_io_w(GRAPHICS_DATA_REG, mask);
156 /* Set the Data Rotate Register and return its old value.
157 Bits 0-2 are rotate count, bits 3-4 are logical operation
158 (0=NOP, 1=AND, 2=OR, 3=XOR). */
159 static inline int setop(int op)
163 vga_io_w(GRAPHICS_ADDR_REG, DATA_ROTATE_INDEX);
164 oldop = vga_io_r(GRAPHICS_DATA_REG);
165 vga_io_w(GRAPHICS_DATA_REG, op);
169 /* Set the Enable Set/Reset Register and return its old value.
170 The code here always uses value 0xf for thsi register. */
171 static inline int setsr(int sr)
175 vga_io_w(GRAPHICS_ADDR_REG, ENABLE_SET_RESET_INDEX);
176 oldsr = vga_io_r(GRAPHICS_DATA_REG);
177 vga_io_w(GRAPHICS_DATA_REG, sr);
181 /* Set the Set/Reset Register and return its old value. */
182 static inline int setcolor(int color)
186 vga_io_w(GRAPHICS_ADDR_REG, SET_RESET_INDEX);
187 oldcolor = vga_io_r(GRAPHICS_DATA_REG);
188 vga_io_w(GRAPHICS_DATA_REG, color);
192 /* Return the value in the Graphics Address Register. */
193 static inline int getindex(void)
195 return vga_io_r(GRAPHICS_ADDR_REG);
198 /* Set the value in the Graphics Address Register. */
199 static inline void setindex(int index)
201 vga_io_w(GRAPHICS_ADDR_REG, index);
204 static void vga16fb_pan_var(struct fb_info *info,
205 struct fb_var_screeninfo *var)
207 struct vga16fb_par *par = info->par;
210 xoffset = var->xoffset;
211 if (info->var.bits_per_pixel == 8) {
212 pos = (info->var.xres_virtual * var->yoffset + xoffset) >> 2;
213 } else if (par->mode & MODE_TEXT) {
214 int fh = 16; // FIXME !!! font height. Fugde for now.
215 pos = (info->var.xres_virtual * (var->yoffset / fh) + xoffset) >> 3;
217 if (info->var.nonstd)
219 pos = (info->var.xres_virtual * var->yoffset + xoffset) >> 3;
221 vga_io_wcrt(VGA_CRTC_START_HI, pos >> 8);
222 vga_io_wcrt(VGA_CRTC_START_LO, pos & 0xFF);
223 /* if we support CFB4, then we must! support xoffset with pixel
224 * granularity if someone supports xoffset in bit resolution */
225 vga_io_r(VGA_IS1_RC); /* reset flip-flop */
226 vga_io_w(VGA_ATT_IW, VGA_ATC_PEL);
227 if (var->bits_per_pixel == 8)
228 vga_io_w(VGA_ATT_IW, (xoffset & 3) << 1);
230 vga_io_w(VGA_ATT_IW, xoffset & 7);
231 vga_io_r(VGA_IS1_RC);
232 vga_io_w(VGA_ATT_IW, 0x20);
235 static void vga16fb_update_fix(struct fb_info *info)
237 if (info->var.bits_per_pixel == 4) {
238 if (info->var.nonstd) {
239 info->fix.type = FB_TYPE_PACKED_PIXELS;
240 info->fix.line_length = info->var.xres_virtual / 2;
242 info->fix.type = FB_TYPE_VGA_PLANES;
243 info->fix.type_aux = FB_AUX_VGA_PLANES_VGA4;
244 info->fix.line_length = info->var.xres_virtual / 8;
246 } else if (info->var.bits_per_pixel == 0) {
247 info->fix.type = FB_TYPE_TEXT;
248 info->fix.type_aux = FB_AUX_TEXT_CGA;
249 info->fix.line_length = info->var.xres_virtual / 4;
251 if (info->var.nonstd) {
252 info->fix.type = FB_TYPE_VGA_PLANES;
253 info->fix.type_aux = FB_AUX_VGA_PLANES_CFB8;
254 info->fix.line_length = info->var.xres_virtual / 4;
256 info->fix.type = FB_TYPE_PACKED_PIXELS;
257 info->fix.line_length = info->var.xres_virtual;
262 static void vga16fb_clock_chip(struct vga16fb_par *par,
263 unsigned int pixclock,
264 const struct fb_info *info,
271 } *ptr, *best, vgaclocks[] = {
272 { 79442 /* 12.587 */, 0x00, 0x08},
273 { 70616 /* 14.161 */, 0x04, 0x08},
274 { 39721 /* 25.175 */, 0x00, 0x00},
275 { 35308 /* 28.322 */, 0x04, 0x00},
276 { 0 /* bad */, 0x00, 0x00}};
279 pixclock = (pixclock * mul) / div;
281 err = pixclock - best->pixclock;
282 if (err < 0) err = -err;
283 for (ptr = vgaclocks + 1; ptr->pixclock; ptr++) {
286 tmp = pixclock - ptr->pixclock;
287 if (tmp < 0) tmp = -tmp;
293 par->misc |= best->misc;
294 par->clkdiv = best->seq_clock_mode;
295 pixclock = (best->pixclock * div) / mul;
298 #define FAIL(X) return -EINVAL
300 static int vga16fb_open(struct fb_info *info, int user)
302 struct vga16fb_par *par = info->par;
303 int cnt = atomic_read(&par->ref_count);
306 memset(&par->state, 0, sizeof(struct vgastate));
307 par->state.flags = VGA_SAVE_FONTS | VGA_SAVE_MODE |
309 save_vga(&par->state);
311 atomic_inc(&par->ref_count);
315 static int vga16fb_release(struct fb_info *info, int user)
317 struct vga16fb_par *par = info->par;
318 int cnt = atomic_read(&par->ref_count);
323 restore_vga(&par->state);
324 atomic_dec(&par->ref_count);
329 static int vga16fb_check_var(struct fb_var_screeninfo *var,
330 struct fb_info *info)
332 struct vga16fb_par *par = info->par;
333 u32 xres, right, hslen, left, xtotal;
334 u32 yres, lower, vslen, upper, ytotal;
335 u32 vxres, xoffset, vyres, yoffset;
344 if (var->bits_per_pixel == 4) {
349 mode = MODE_SKIP4 | MODE_CFB;
357 } else if (var->bits_per_pixel == 8) {
359 return -EINVAL; /* no support on EGA */
362 mode = MODE_8BPP | MODE_CFB;
365 mode = MODE_SKIP4 | MODE_8BPP | MODE_CFB;
371 xres = (var->xres + 7) & ~7;
372 vxres = (var->xres_virtual + 0xF) & ~0xF;
373 xoffset = (var->xoffset + 7) & ~7;
374 left = (var->left_margin + 7) & ~7;
375 right = (var->right_margin + 7) & ~7;
376 hslen = (var->hsync_len + 7) & ~7;
380 if (xres + xoffset > vxres)
381 xoffset = vxres - xres;
384 var->right_margin = right;
385 var->hsync_len = hslen;
386 var->left_margin = left;
387 var->xres_virtual = vxres;
388 var->xoffset = xoffset;
395 xtotal = xres + right + hslen + left;
397 FAIL("xtotal too big");
399 FAIL("hslen too big");
400 if (right + hslen + left > 64)
401 FAIL("hblank too big");
402 par->crtc[VGA_CRTC_H_TOTAL] = xtotal - 5;
403 par->crtc[VGA_CRTC_H_BLANK_START] = xres - 1;
404 par->crtc[VGA_CRTC_H_DISP] = xres - 1;
406 par->crtc[VGA_CRTC_H_SYNC_START] = pos;
408 par->crtc[VGA_CRTC_H_SYNC_END] = pos & 0x1F;
409 pos += left - 2; /* blank_end + 2 <= total + 5 */
410 par->crtc[VGA_CRTC_H_BLANK_END] = (pos & 0x1F) | 0x80;
412 par->crtc[VGA_CRTC_H_SYNC_END] |= 0x80;
415 lower = var->lower_margin;
416 vslen = var->vsync_len;
417 upper = var->upper_margin;
418 vyres = var->yres_virtual;
419 yoffset = var->yoffset;
423 if (vxres * vyres > maxmem) {
424 vyres = maxmem / vxres;
428 if (yoffset + yres > vyres)
429 yoffset = vyres - yres;
431 var->lower_margin = lower;
432 var->vsync_len = vslen;
433 var->upper_margin = upper;
434 var->yres_virtual = vyres;
435 var->yoffset = yoffset;
437 if (var->vmode & FB_VMODE_DOUBLE) {
443 ytotal = yres + lower + vslen + upper;
454 FAIL("ytotal too big");
456 FAIL("vslen too big");
457 par->crtc[VGA_CRTC_V_TOTAL] = ytotal - 2;
458 r7 = 0x10; /* disable linecompare */
459 if (ytotal & 0x100) r7 |= 0x01;
460 if (ytotal & 0x200) r7 |= 0x20;
461 par->crtc[VGA_CRTC_PRESET_ROW] = 0;
462 par->crtc[VGA_CRTC_MAX_SCAN] = 0x40; /* 1 scanline, no linecmp */
463 if (var->vmode & FB_VMODE_DOUBLE)
464 par->crtc[VGA_CRTC_MAX_SCAN] |= 0x80;
465 par->crtc[VGA_CRTC_CURSOR_START] = 0x20;
466 par->crtc[VGA_CRTC_CURSOR_END] = 0x00;
467 if ((mode & (MODE_CFB | MODE_8BPP)) == MODE_CFB)
469 pos = yoffset * vxres + (xoffset >> shift);
470 par->crtc[VGA_CRTC_START_HI] = pos >> 8;
471 par->crtc[VGA_CRTC_START_LO] = pos & 0xFF;
472 par->crtc[VGA_CRTC_CURSOR_HI] = 0x00;
473 par->crtc[VGA_CRTC_CURSOR_LO] = 0x00;
475 par->crtc[VGA_CRTC_V_DISP_END] = pos & 0xFF;
476 par->crtc[VGA_CRTC_V_BLANK_START] = pos & 0xFF;
478 r7 |= 0x0A; /* 0x02 -> DISP_END, 0x08 -> BLANK_START */
480 r7 |= 0x40; /* 0x40 -> DISP_END */
481 par->crtc[VGA_CRTC_MAX_SCAN] |= 0x20; /* BLANK_START */
484 par->crtc[VGA_CRTC_V_SYNC_START] = pos & 0xFF;
490 par->crtc[VGA_CRTC_V_SYNC_END] = (pos & 0x0F) & ~0x10; /* disabled IRQ */
491 pos += upper - 1; /* blank_end + 1 <= ytotal + 2 */
492 par->crtc[VGA_CRTC_V_BLANK_END] = pos & 0xFF; /* 0x7F for original VGA,
493 but some SVGA chips requires all 8 bits to set */
495 FAIL("vxres too long");
496 par->crtc[VGA_CRTC_OFFSET] = vxres >> 1;
497 if (mode & MODE_SKIP4)
498 par->crtc[VGA_CRTC_UNDERLINE] = 0x5F; /* 256, cfb8 */
500 par->crtc[VGA_CRTC_UNDERLINE] = 0x1F; /* 16, vgap */
501 par->crtc[VGA_CRTC_MODE] = rMode | ((mode & MODE_TEXT) ? 0xA3 : 0xE3);
502 par->crtc[VGA_CRTC_LINE_COMPARE] = 0xFF;
503 par->crtc[VGA_CRTC_OVERFLOW] = r7;
505 par->vss = 0x00; /* 3DA */
507 par->misc = 0xE3; /* enable CPU, ports 0x3Dx, positive sync */
508 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
510 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
515 if (mode & MODE_8BPP)
516 /* pixel clock == vga clock / 2 */
517 vga16fb_clock_chip(par, var->pixclock, info, 1, 2);
519 /* pixel clock == vga clock */
520 vga16fb_clock_chip(par, var->pixclock, info, 1, 1);
522 var->red.offset = var->green.offset = var->blue.offset =
523 var->transp.offset = 0;
524 var->red.length = var->green.length = var->blue.length =
525 (par->isVGA) ? 6 : 2;
526 var->transp.length = 0;
527 var->activate = FB_ACTIVATE_NOW;
530 var->accel_flags = 0;
535 static int vga16fb_set_par(struct fb_info *info)
537 struct vga16fb_par *par = info->par;
543 seq[VGA_SEQ_CLOCK_MODE] = 0x01 | par->clkdiv;
544 if (par->mode & MODE_TEXT)
545 seq[VGA_SEQ_PLANE_WRITE] = 0x03;
547 seq[VGA_SEQ_PLANE_WRITE] = 0x0F;
548 seq[VGA_SEQ_CHARACTER_MAP] = 0x00;
549 if (par->mode & MODE_TEXT)
550 seq[VGA_SEQ_MEMORY_MODE] = 0x03;
551 else if (par->mode & MODE_SKIP4)
552 seq[VGA_SEQ_MEMORY_MODE] = 0x0E;
554 seq[VGA_SEQ_MEMORY_MODE] = 0x06;
556 gdc[VGA_GFX_SR_VALUE] = 0x00;
557 gdc[VGA_GFX_SR_ENABLE] = 0x00;
558 gdc[VGA_GFX_COMPARE_VALUE] = 0x00;
559 gdc[VGA_GFX_DATA_ROTATE] = 0x00;
560 gdc[VGA_GFX_PLANE_READ] = 0;
561 if (par->mode & MODE_TEXT) {
562 gdc[VGA_GFX_MODE] = 0x10;
563 gdc[VGA_GFX_MISC] = 0x06;
565 if (par->mode & MODE_CFB)
566 gdc[VGA_GFX_MODE] = 0x40;
568 gdc[VGA_GFX_MODE] = 0x00;
569 gdc[VGA_GFX_MISC] = 0x05;
571 gdc[VGA_GFX_COMPARE_MASK] = 0x0F;
572 gdc[VGA_GFX_BIT_MASK] = 0xFF;
574 for (i = 0x00; i < 0x10; i++)
576 if (par->mode & MODE_TEXT)
577 atc[VGA_ATC_MODE] = 0x04;
578 else if (par->mode & MODE_8BPP)
579 atc[VGA_ATC_MODE] = 0x41;
581 atc[VGA_ATC_MODE] = 0x81;
582 atc[VGA_ATC_OVERSCAN] = 0x00; /* 0 for EGA, 0xFF for VGA */
583 atc[VGA_ATC_PLANE_ENABLE] = 0x0F;
584 if (par->mode & MODE_8BPP)
585 atc[VGA_ATC_PEL] = (info->var.xoffset & 3) << 1;
587 atc[VGA_ATC_PEL] = info->var.xoffset & 7;
588 atc[VGA_ATC_COLOR_PAGE] = 0x00;
590 if (par->mode & MODE_TEXT) {
591 fh = 16; // FIXME !!! Fudge font height.
592 par->crtc[VGA_CRTC_MAX_SCAN] = (par->crtc[VGA_CRTC_MAX_SCAN]
596 vga_io_w(VGA_MIS_W, vga_io_r(VGA_MIS_R) | 0x01);
598 /* Enable graphics register modification */
600 vga_io_w(EGA_GFX_E0, 0x00);
601 vga_io_w(EGA_GFX_E1, 0x01);
604 /* update misc output register */
605 vga_io_w(VGA_MIS_W, par->misc);
607 /* synchronous reset on */
608 vga_io_wseq(0x00, 0x01);
611 vga_io_w(VGA_PEL_MSK, par->pel_msk);
613 /* write sequencer registers */
614 vga_io_wseq(VGA_SEQ_CLOCK_MODE, seq[VGA_SEQ_CLOCK_MODE] | 0x20);
615 for (i = 2; i < VGA_SEQ_C; i++) {
616 vga_io_wseq(i, seq[i]);
619 /* synchronous reset off */
620 vga_io_wseq(0x00, 0x03);
622 /* deprotect CRT registers 0-7 */
623 vga_io_wcrt(VGA_CRTC_V_SYNC_END, par->crtc[VGA_CRTC_V_SYNC_END]);
625 /* write CRT registers */
626 for (i = 0; i < VGA_CRTC_REGS; i++) {
627 vga_io_wcrt(i, par->crtc[i]);
630 /* write graphics controller registers */
631 for (i = 0; i < VGA_GFX_C; i++) {
632 vga_io_wgfx(i, gdc[i]);
635 /* write attribute controller registers */
636 for (i = 0; i < VGA_ATT_C; i++) {
637 vga_io_r(VGA_IS1_RC); /* reset flip-flop */
638 vga_io_wattr(i, atc[i]);
641 /* Wait for screen to stabilize. */
644 vga_io_wseq(VGA_SEQ_CLOCK_MODE, seq[VGA_SEQ_CLOCK_MODE]);
646 vga_io_r(VGA_IS1_RC);
647 vga_io_w(VGA_ATT_IW, 0x20);
649 vga16fb_update_fix(info);
653 static void ega16_setpalette(int regno, unsigned red, unsigned green, unsigned blue)
655 static unsigned char map[] = { 000, 001, 010, 011 };
660 val = map[red>>14] | ((map[green>>14]) << 1) | ((map[blue>>14]) << 2);
661 vga_io_r(VGA_IS1_RC); /* ! 0x3BA */
662 vga_io_wattr(regno, val);
663 vga_io_r(VGA_IS1_RC); /* some clones need it */
664 vga_io_w(VGA_ATT_IW, 0x20); /* unblank screen */
667 static void vga16_setpalette(int regno, unsigned red, unsigned green, unsigned blue)
669 outb(regno, dac_reg);
670 outb(red >> 10, dac_val);
671 outb(green >> 10, dac_val);
672 outb(blue >> 10, dac_val);
675 static int vga16fb_setcolreg(unsigned regno, unsigned red, unsigned green,
676 unsigned blue, unsigned transp,
677 struct fb_info *info)
679 struct vga16fb_par *par = info->par;
683 * Set a single color register. The values supplied are
684 * already rounded down to the hardware's capabilities
685 * (according to the entries in the `var' structure). Return
686 * != 0 for invalid regno.
692 gray = info->var.grayscale;
695 /* gray = 0.30*R + 0.59*G + 0.11*B */
696 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
699 vga16_setpalette(regno,red,green,blue);
701 ega16_setpalette(regno,red,green,blue);
705 static int vga16fb_pan_display(struct fb_var_screeninfo *var,
706 struct fb_info *info)
708 if (var->xoffset + info->var.xres > info->var.xres_virtual ||
709 var->yoffset + info->var.yres > info->var.yres_virtual)
712 vga16fb_pan_var(info, var);
714 info->var.xoffset = var->xoffset;
715 info->var.yoffset = var->yoffset;
716 info->var.vmode &= ~FB_VMODE_YWRAP;
720 /* The following VESA blanking code is taken from vgacon.c. The VGA
721 blanking code was originally by Huang shi chao, and modified by
722 Christoph Rimek (chrimek@toppoint.de) and todd j. derr
723 (tjd@barefoot.org) for Linux. */
724 #define attrib_port VGA_ATC_IW
725 #define seq_port_reg VGA_SEQ_I
726 #define seq_port_val VGA_SEQ_D
727 #define gr_port_reg VGA_GFX_I
728 #define gr_port_val VGA_GFX_D
729 #define video_misc_rd VGA_MIS_R
730 #define video_misc_wr VGA_MIS_W
731 #define vga_video_port_reg VGA_CRT_IC
732 #define vga_video_port_val VGA_CRT_DC
734 static void vga_vesa_blank(struct vga16fb_par *par, int mode)
736 unsigned char SeqCtrlIndex;
737 unsigned char CrtCtrlIndex;
740 SeqCtrlIndex = vga_io_r(seq_port_reg);
741 CrtCtrlIndex = vga_io_r(vga_video_port_reg);
743 /* save original values of VGA controller registers */
744 if(!par->vesa_blanked) {
745 par->vga_state.CrtMiscIO = vga_io_r(video_misc_rd);
748 par->vga_state.HorizontalTotal = vga_io_rcrt(0x00); /* HorizontalTotal */
749 par->vga_state.HorizDisplayEnd = vga_io_rcrt(0x01); /* HorizDisplayEnd */
750 par->vga_state.StartHorizRetrace = vga_io_rcrt(0x04); /* StartHorizRetrace */
751 par->vga_state.EndHorizRetrace = vga_io_rcrt(0x05); /* EndHorizRetrace */
752 par->vga_state.Overflow = vga_io_rcrt(0x07); /* Overflow */
753 par->vga_state.StartVertRetrace = vga_io_rcrt(0x10); /* StartVertRetrace */
754 par->vga_state.EndVertRetrace = vga_io_rcrt(0x11); /* EndVertRetrace */
755 par->vga_state.ModeControl = vga_io_rcrt(0x17); /* ModeControl */
756 par->vga_state.ClockingMode = vga_io_rseq(0x01); /* ClockingMode */
759 /* assure that video is enabled */
760 /* "0x20" is VIDEO_ENABLE_bit in register 01 of sequencer */
762 vga_io_wseq(0x01, par->vga_state.ClockingMode | 0x20);
764 /* test for vertical retrace in process.... */
765 if ((par->vga_state.CrtMiscIO & 0x80) == 0x80)
766 vga_io_w(video_misc_wr, par->vga_state.CrtMiscIO & 0xef);
769 * Set <End of vertical retrace> to minimum (0) and
770 * <Start of vertical Retrace> to maximum (incl. overflow)
771 * Result: turn off vertical sync (VSync) pulse.
773 if (mode & FB_BLANK_VSYNC_SUSPEND) {
774 outb_p(0x10,vga_video_port_reg); /* StartVertRetrace */
775 outb_p(0xff,vga_video_port_val); /* maximum value */
776 outb_p(0x11,vga_video_port_reg); /* EndVertRetrace */
777 outb_p(0x40,vga_video_port_val); /* minimum (bits 0..3) */
778 outb_p(0x07,vga_video_port_reg); /* Overflow */
779 outb_p(par->vga_state.Overflow | 0x84,vga_video_port_val); /* bits 9,10 of vert. retrace */
782 if (mode & FB_BLANK_HSYNC_SUSPEND) {
784 * Set <End of horizontal retrace> to minimum (0) and
785 * <Start of horizontal Retrace> to maximum
786 * Result: turn off horizontal sync (HSync) pulse.
788 outb_p(0x04,vga_video_port_reg); /* StartHorizRetrace */
789 outb_p(0xff,vga_video_port_val); /* maximum */
790 outb_p(0x05,vga_video_port_reg); /* EndHorizRetrace */
791 outb_p(0x00,vga_video_port_val); /* minimum (0) */
794 /* restore both index registers */
795 outb_p(SeqCtrlIndex,seq_port_reg);
796 outb_p(CrtCtrlIndex,vga_video_port_reg);
800 static void vga_vesa_unblank(struct vga16fb_par *par)
802 unsigned char SeqCtrlIndex;
803 unsigned char CrtCtrlIndex;
806 SeqCtrlIndex = vga_io_r(seq_port_reg);
807 CrtCtrlIndex = vga_io_r(vga_video_port_reg);
809 /* restore original values of VGA controller registers */
810 vga_io_w(video_misc_wr, par->vga_state.CrtMiscIO);
812 /* HorizontalTotal */
813 vga_io_wcrt(0x00, par->vga_state.HorizontalTotal);
814 /* HorizDisplayEnd */
815 vga_io_wcrt(0x01, par->vga_state.HorizDisplayEnd);
816 /* StartHorizRetrace */
817 vga_io_wcrt(0x04, par->vga_state.StartHorizRetrace);
818 /* EndHorizRetrace */
819 vga_io_wcrt(0x05, par->vga_state.EndHorizRetrace);
821 vga_io_wcrt(0x07, par->vga_state.Overflow);
822 /* StartVertRetrace */
823 vga_io_wcrt(0x10, par->vga_state.StartVertRetrace);
825 vga_io_wcrt(0x11, par->vga_state.EndVertRetrace);
827 vga_io_wcrt(0x17, par->vga_state.ModeControl);
829 vga_io_wseq(0x01, par->vga_state.ClockingMode);
831 /* restore index/control registers */
832 vga_io_w(seq_port_reg, SeqCtrlIndex);
833 vga_io_w(vga_video_port_reg, CrtCtrlIndex);
837 static void vga_pal_blank(void)
841 for (i=0; i<16; i++) {
842 outb_p (i, dac_reg) ;
843 outb_p (0, dac_val) ;
844 outb_p (0, dac_val) ;
845 outb_p (0, dac_val) ;
849 /* 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off */
850 static int vga16fb_blank(int blank, struct fb_info *info)
852 struct vga16fb_par *par = info->par;
855 case FB_BLANK_UNBLANK: /* Unblank */
856 if (par->vesa_blanked) {
857 vga_vesa_unblank(par);
858 par->vesa_blanked = 0;
860 if (par->palette_blanked) {
861 par->palette_blanked = 0;
864 case FB_BLANK_NORMAL: /* blank */
866 par->palette_blanked = 1;
868 default: /* VESA blanking */
869 vga_vesa_blank(par, blank);
870 par->vesa_blanked = 1;
876 static void vga_8planes_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
878 u32 dx = rect->dx, width = rect->width;
879 char oldindex = getindex();
880 char oldmode = setmode(0x40);
881 char oldmask = selectmask();
882 int line_ofs, height;
887 where = info->screen_base + dx + rect->dy * info->fix.line_length;
889 if (rect->rop == ROP_COPY) {
894 line_ofs = info->fix.line_length - width;
897 height = rect->height;
902 /* we can do memset... */
903 for (x = width; x > 0; --x) {
904 writeb(rect->color, where);
910 char oldcolor = setcolor(0xf);
916 for (y = 0; y < rect->height; y++) {
919 where += info->fix.line_length;
930 static void vga16fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
932 int x, x2, y2, vxres, vyres, width, height, line_ofs;
935 vxres = info->var.xres_virtual;
936 vyres = info->var.yres_virtual;
938 if (!rect->width || !rect->height || rect->dx > vxres || rect->dy > vyres)
941 /* We could use hardware clipping but on many cards you get around
942 * hardware clipping by writing to framebuffer directly. */
944 x2 = rect->dx + rect->width;
945 y2 = rect->dy + rect->height;
946 x2 = x2 < vxres ? x2 : vxres;
947 y2 = y2 < vyres ? y2 : vyres;
948 width = x2 - rect->dx;
950 switch (info->fix.type) {
951 case FB_TYPE_VGA_PLANES:
952 if (info->fix.type_aux == FB_AUX_VGA_PLANES_VGA4) {
954 height = y2 - rect->dy;
955 width = rect->width/8;
957 line_ofs = info->fix.line_length - width;
958 dst = info->screen_base + (rect->dx/8) + rect->dy * info->fix.line_length;
965 setcolor(rect->color);
971 for (x = 0; x < width; x++) {
987 for (x = 0; x < width; x++) {
996 vga_8planes_fillrect(info, rect);
998 case FB_TYPE_PACKED_PIXELS:
1000 cfb_fillrect(info, rect);
1005 static void vga_8planes_copyarea(struct fb_info *info, const struct fb_copyarea *area)
1007 char oldindex = getindex();
1008 char oldmode = setmode(0x41);
1009 char oldop = setop(0);
1010 char oldsr = setsr(0xf);
1011 int height, line_ofs, x;
1016 height = area->height;
1020 width = area->width / 4;
1022 if (area->dy < area->sy || (area->dy == area->sy && dx < sx)) {
1023 line_ofs = info->fix.line_length - width;
1024 dest = info->screen_base + dx + area->dy * info->fix.line_length;
1025 src = info->screen_base + sx + area->sy * info->fix.line_length;
1027 for (x = 0; x < width; x++) {
1037 line_ofs = info->fix.line_length - width;
1038 dest = info->screen_base + dx + width +
1039 (area->dy + height - 1) * info->fix.line_length;
1040 src = info->screen_base + sx + width +
1041 (area->sy + height - 1) * info->fix.line_length;
1043 for (x = 0; x < width; x++) {
1060 static void vga16fb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
1062 u32 dx = area->dx, dy = area->dy, sx = area->sx, sy = area->sy;
1063 int x, x2, y2, old_dx, old_dy, vxres, vyres;
1064 int height, width, line_ofs;
1065 char __iomem *dst = NULL;
1066 char __iomem *src = NULL;
1068 vxres = info->var.xres_virtual;
1069 vyres = info->var.yres_virtual;
1071 if (area->dx > vxres || area->sx > vxres || area->dy > vyres ||
1075 /* clip the destination */
1080 * We could use hardware clipping but on many cards you get around
1081 * hardware clipping by writing to framebuffer directly.
1083 x2 = area->dx + area->width;
1084 y2 = area->dy + area->height;
1085 dx = area->dx > 0 ? area->dx : 0;
1086 dy = area->dy > 0 ? area->dy : 0;
1087 x2 = x2 < vxres ? x2 : vxres;
1088 y2 = y2 < vyres ? y2 : vyres;
1092 /* update sx1,sy1 */
1093 sx += (dx - old_dx);
1094 sy += (dy - old_dy);
1096 /* the source must be completely inside the virtual screen */
1097 if (sx < 0 || sy < 0 || (sx + width) > vxres || (sy + height) > vyres)
1100 switch (info->fix.type) {
1101 case FB_TYPE_VGA_PLANES:
1102 if (info->fix.type_aux == FB_AUX_VGA_PLANES_VGA4) {
1105 line_ofs = info->fix.line_length - width;
1111 if (dy < sy || (dy == sy && dx < sx)) {
1112 dst = info->screen_base + (dx/8) + dy * info->fix.line_length;
1113 src = info->screen_base + (sx/8) + sy * info->fix.line_length;
1115 for (x = 0; x < width; x++) {
1125 dst = info->screen_base + (dx/8) + width +
1126 (dy + height - 1) * info->fix.line_length;
1127 src = info->screen_base + (sx/8) + width +
1128 (sy + height - 1) * info->fix.line_length;
1130 for (x = 0; x < width; x++) {
1141 vga_8planes_copyarea(info, area);
1143 case FB_TYPE_PACKED_PIXELS:
1145 cfb_copyarea(info, area);
1150 #ifdef __LITTLE_ENDIAN
1151 static unsigned int transl_l[] =
1152 {0x0,0x8,0x4,0xC,0x2,0xA,0x6,0xE,0x1,0x9,0x5,0xD,0x3,0xB,0x7,0xF};
1153 static unsigned int transl_h[] =
1154 {0x000, 0x800, 0x400, 0xC00, 0x200, 0xA00, 0x600, 0xE00,
1155 0x100, 0x900, 0x500, 0xD00, 0x300, 0xB00, 0x700, 0xF00};
1158 static unsigned int transl_h[] =
1159 {0x0,0x8,0x4,0xC,0x2,0xA,0x6,0xE,0x1,0x9,0x5,0xD,0x3,0xB,0x7,0xF};
1160 static unsigned int transl_l[] =
1161 {0x000, 0x800, 0x400, 0xC00, 0x200, 0xA00, 0x600, 0xE00,
1162 0x100, 0x900, 0x500, 0xD00, 0x300, 0xB00, 0x700, 0xF00};
1164 #error "Only __BIG_ENDIAN and __LITTLE_ENDIAN are supported in vga-planes"
1168 static void vga_8planes_imageblit(struct fb_info *info, const struct fb_image *image)
1170 char oldindex = getindex();
1171 char oldmode = setmode(0x40);
1172 char oldop = setop(0);
1173 char oldsr = setsr(0);
1174 char oldmask = selectmask();
1175 const char *cdat = image->data;
1177 char __iomem *where;
1181 where = info->screen_base + dx + image->dy * info->fix.line_length;
1184 writeb(image->bg_color, where);
1187 setmask(image->fg_color ^ image->bg_color);
1190 for (y = 0; y < image->height; y++, where += info->fix.line_length)
1191 writew(transl_h[cdat[y]&0xF] | transl_l[cdat[y] >> 4], where);
1199 static void vga_imageblit_expand(struct fb_info *info, const struct fb_image *image)
1201 char __iomem *where = info->screen_base + (image->dx/8) +
1202 image->dy * info->fix.line_length;
1203 struct vga16fb_par *par = info->par;
1204 char *cdat = (char *) image->data;
1208 switch (info->fix.type) {
1209 case FB_TYPE_VGA_PLANES:
1210 if (info->fix.type_aux == FB_AUX_VGA_PLANES_VGA4) {
1215 setcolor(image->fg_color);
1219 writeb(image->bg_color, where);
1221 readb(where); /* fill latches */
1224 for (y = 0; y < image->height; y++) {
1226 for (x = image->width/8; x--;)
1227 writeb(*cdat++, dst++);
1228 where += info->fix.line_length;
1235 setcolor(image->bg_color);
1239 for (y = 0; y < image->height; y++) {
1241 for (x=image->width/8; x--;){
1243 setcolor(image->fg_color);
1250 where += info->fix.line_length;
1254 vga_8planes_imageblit(info, image);
1256 case FB_TYPE_PACKED_PIXELS:
1258 cfb_imageblit(info, image);
1263 static void vga_imageblit_color(struct fb_info *info, const struct fb_image *image)
1268 struct vga16fb_par *par = info->par;
1269 char __iomem *where =
1270 info->screen_base + image->dy * info->fix.line_length +
1272 const char *cdat = image->data;
1276 switch (info->fix.type) {
1277 case FB_TYPE_VGA_PLANES:
1278 if (info->fix.type_aux == FB_AUX_VGA_PLANES_VGA4 &&
1284 for (y = 0; y < image->height; y++) {
1285 for (x = 0; x < image->width; x++) {
1290 setmask(1 << (7 - (x % 8)));
1296 where += info->fix.line_length;
1300 case FB_TYPE_PACKED_PIXELS:
1301 cfb_imageblit(info, image);
1308 static void vga16fb_imageblit(struct fb_info *info, const struct fb_image *image)
1310 if (image->depth == 1)
1311 vga_imageblit_expand(info, image);
1313 vga_imageblit_color(info, image);
1316 static struct fb_ops vga16fb_ops = {
1317 .owner = THIS_MODULE,
1318 .fb_open = vga16fb_open,
1319 .fb_release = vga16fb_release,
1320 .fb_check_var = vga16fb_check_var,
1321 .fb_set_par = vga16fb_set_par,
1322 .fb_setcolreg = vga16fb_setcolreg,
1323 .fb_pan_display = vga16fb_pan_display,
1324 .fb_blank = vga16fb_blank,
1325 .fb_fillrect = vga16fb_fillrect,
1326 .fb_copyarea = vga16fb_copyarea,
1327 .fb_imageblit = vga16fb_imageblit,
1331 static int vga16fb_setup(char *options)
1335 if (!options || !*options)
1338 while ((this_opt = strsep(&options, ",")) != NULL) {
1339 if (!*this_opt) continue;
1345 static int __init vga16fb_probe(struct device *device)
1347 struct platform_device *dev = to_platform_device(device);
1348 struct fb_info *info;
1349 struct vga16fb_par *par;
1353 printk(KERN_DEBUG "vga16fb: initializing\n");
1354 info = framebuffer_alloc(sizeof(struct vga16fb_par), &dev->dev);
1361 /* XXX share VGA_FB_PHYS and I/O region with vgacon and others */
1362 info->screen_base = (void __iomem *)VGA_MAP_MEM(VGA_FB_PHYS);
1364 if (!info->screen_base) {
1365 printk(KERN_ERR "vga16fb: unable to map device\n");
1370 printk(KERN_INFO "vga16fb: mapped to 0x%p\n", info->screen_base);
1373 par->isVGA = ORIG_VIDEO_ISVGA;
1374 par->palette_blanked = 0;
1375 par->vesa_blanked = 0;
1377 i = par->isVGA? 6 : 2;
1379 vga16fb_defined.red.length = i;
1380 vga16fb_defined.green.length = i;
1381 vga16fb_defined.blue.length = i;
1383 /* name should not depend on EGA/VGA */
1384 info->fbops = &vga16fb_ops;
1385 info->var = vga16fb_defined;
1386 info->fix = vga16fb_fix;
1387 info->flags = FBINFO_FLAG_DEFAULT |
1388 FBINFO_HWACCEL_YPAN;
1390 i = (info->var.bits_per_pixel == 8) ? 256 : 16;
1391 ret = fb_alloc_cmap(&info->cmap, i, 0);
1393 printk(KERN_ERR "vga16fb: unable to allocate colormap\n");
1395 goto err_alloc_cmap;
1398 if (vga16fb_check_var(&info->var, info)) {
1399 printk(KERN_ERR "vga16fb: unable to validate variable\n");
1404 vga16fb_update_fix(info);
1406 if (register_framebuffer(info) < 0) {
1407 printk(KERN_ERR "vga16fb: unable to register framebuffer\n");
1412 printk(KERN_INFO "fb%d: %s frame buffer device\n",
1413 info->node, info->fix.id);
1414 dev_set_drvdata(device, info);
1419 fb_dealloc_cmap(&info->cmap);
1421 iounmap(info->screen_base);
1423 framebuffer_release(info);
1428 static int vga16fb_remove(struct device *device)
1430 struct fb_info *info = dev_get_drvdata(device);
1433 unregister_framebuffer(info);
1434 iounmap(info->screen_base);
1435 fb_dealloc_cmap(&info->cmap);
1436 /* XXX unshare VGA regions */
1437 framebuffer_release(info);
1443 static struct device_driver vga16fb_driver = {
1445 .bus = &platform_bus_type,
1446 .probe = vga16fb_probe,
1447 .remove = vga16fb_remove,
1450 static struct platform_device vga16fb_device = {
1454 static int __init vga16fb_init(void)
1458 char *option = NULL;
1460 if (fb_get_options("vga16fb", &option))
1463 vga16fb_setup(option);
1465 ret = driver_register(&vga16fb_driver);
1468 ret = platform_device_register(&vga16fb_device);
1470 driver_unregister(&vga16fb_driver);
1476 static void __exit vga16fb_exit(void)
1478 platform_device_unregister(&vga16fb_device);
1479 driver_unregister(&vga16fb_driver);
1482 MODULE_LICENSE("GPL");
1483 module_init(vga16fb_init);
1484 module_exit(vga16fb_exit);
1488 * Overrides for Emacs so that we follow Linus's tabbing style.
1489 * ---------------------------------------------------------------------------