2 * Support for the Tundra TSI148 VME-PCI Bridge Chip
4 * Author: Martyn Welch <martyn.welch@ge.com>
5 * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
7 * Based on work by Tom Armistead and Ajit Prem
8 * Copyright 2004 Motorola Inc.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
16 #include <linux/module.h>
17 #include <linux/moduleparam.h>
19 #include <linux/types.h>
20 #include <linux/errno.h>
21 #include <linux/proc_fs.h>
22 #include <linux/pci.h>
23 #include <linux/poll.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/interrupt.h>
26 #include <linux/spinlock.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
29 #include <linux/time.h>
31 #include <linux/uaccess.h>
32 #include <linux/byteorder/generic.h>
33 #include <linux/vme.h>
35 #include "../vme_bridge.h"
36 #include "vme_tsi148.h"
38 static int tsi148_probe(struct pci_dev *, const struct pci_device_id *);
39 static void tsi148_remove(struct pci_dev *);
42 /* Module parameter */
46 static const char driver_name[] = "vme_tsi148";
48 static const struct pci_device_id tsi148_ids[] = {
49 { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_TSI148) },
53 static struct pci_driver tsi148_driver = {
55 .id_table = tsi148_ids,
56 .probe = tsi148_probe,
57 .remove = tsi148_remove,
60 static void reg_join(unsigned int high, unsigned int low,
61 unsigned long long *variable)
63 *variable = (unsigned long long)high << 32;
64 *variable |= (unsigned long long)low;
67 static void reg_split(unsigned long long variable, unsigned int *high,
70 *low = (unsigned int)variable & 0xFFFFFFFF;
71 *high = (unsigned int)(variable >> 32);
77 static u32 tsi148_DMA_irqhandler(struct tsi148_driver *bridge,
82 if (channel_mask & TSI148_LCSR_INTS_DMA0S) {
83 wake_up(&bridge->dma_queue[0]);
84 serviced |= TSI148_LCSR_INTC_DMA0C;
86 if (channel_mask & TSI148_LCSR_INTS_DMA1S) {
87 wake_up(&bridge->dma_queue[1]);
88 serviced |= TSI148_LCSR_INTC_DMA1C;
95 * Wake up location monitor queue
97 static u32 tsi148_LM_irqhandler(struct tsi148_driver *bridge, u32 stat)
102 for (i = 0; i < 4; i++) {
103 if (stat & TSI148_LCSR_INTS_LMS[i]) {
104 /* We only enable interrupts if the callback is set */
105 bridge->lm_callback[i](i);
106 serviced |= TSI148_LCSR_INTC_LMC[i];
114 * Wake up mail box queue.
116 * XXX This functionality is not exposed up though API.
118 static u32 tsi148_MB_irqhandler(struct vme_bridge *tsi148_bridge, u32 stat)
123 struct tsi148_driver *bridge;
125 bridge = tsi148_bridge->driver_priv;
127 for (i = 0; i < 4; i++) {
128 if (stat & TSI148_LCSR_INTS_MBS[i]) {
129 val = ioread32be(bridge->base + TSI148_GCSR_MBOX[i]);
130 dev_err(tsi148_bridge->parent, "VME Mailbox %d received"
132 serviced |= TSI148_LCSR_INTC_MBC[i];
140 * Display error & status message when PERR (PCI) exception interrupt occurs.
142 static u32 tsi148_PERR_irqhandler(struct vme_bridge *tsi148_bridge)
144 struct tsi148_driver *bridge;
146 bridge = tsi148_bridge->driver_priv;
148 dev_err(tsi148_bridge->parent, "PCI Exception at address: 0x%08x:%08x, "
149 "attributes: %08x\n",
150 ioread32be(bridge->base + TSI148_LCSR_EDPAU),
151 ioread32be(bridge->base + TSI148_LCSR_EDPAL),
152 ioread32be(bridge->base + TSI148_LCSR_EDPAT));
154 dev_err(tsi148_bridge->parent, "PCI-X attribute reg: %08x, PCI-X split "
155 "completion reg: %08x\n",
156 ioread32be(bridge->base + TSI148_LCSR_EDPXA),
157 ioread32be(bridge->base + TSI148_LCSR_EDPXS));
159 iowrite32be(TSI148_LCSR_EDPAT_EDPCL, bridge->base + TSI148_LCSR_EDPAT);
161 return TSI148_LCSR_INTC_PERRC;
165 * Save address and status when VME error interrupt occurs.
167 static u32 tsi148_VERR_irqhandler(struct vme_bridge *tsi148_bridge)
169 unsigned int error_addr_high, error_addr_low;
170 unsigned long long error_addr;
172 struct vme_bus_error *error = NULL;
173 struct tsi148_driver *bridge;
175 bridge = tsi148_bridge->driver_priv;
177 error_addr_high = ioread32be(bridge->base + TSI148_LCSR_VEAU);
178 error_addr_low = ioread32be(bridge->base + TSI148_LCSR_VEAL);
179 error_attrib = ioread32be(bridge->base + TSI148_LCSR_VEAT);
181 reg_join(error_addr_high, error_addr_low, &error_addr);
183 /* Check for exception register overflow (we have lost error data) */
184 if (error_attrib & TSI148_LCSR_VEAT_VEOF) {
185 dev_err(tsi148_bridge->parent, "VME Bus Exception Overflow "
190 error = kmalloc(sizeof(struct vme_bus_error), GFP_ATOMIC);
192 error->address = error_addr;
193 error->attributes = error_attrib;
194 list_add_tail(&error->list, &tsi148_bridge->vme_errors);
196 dev_err(tsi148_bridge->parent,
197 "Unable to alloc memory for VMEbus Error reporting\n");
202 dev_err(tsi148_bridge->parent,
203 "VME Bus Error at address: 0x%llx, attributes: %08x\n",
204 error_addr, error_attrib);
208 iowrite32be(TSI148_LCSR_VEAT_VESCL, bridge->base + TSI148_LCSR_VEAT);
210 return TSI148_LCSR_INTC_VERRC;
214 * Wake up IACK queue.
216 static u32 tsi148_IACK_irqhandler(struct tsi148_driver *bridge)
218 wake_up(&bridge->iack_queue);
220 return TSI148_LCSR_INTC_IACKC;
224 * Calling VME bus interrupt callback if provided.
226 static u32 tsi148_VIRQ_irqhandler(struct vme_bridge *tsi148_bridge,
229 int vec, i, serviced = 0;
230 struct tsi148_driver *bridge;
232 bridge = tsi148_bridge->driver_priv;
234 for (i = 7; i > 0; i--) {
235 if (stat & (1 << i)) {
237 * Note: Even though the registers are defined as
238 * 32-bits in the spec, we only want to issue 8-bit
239 * IACK cycles on the bus, read from offset 3.
241 vec = ioread8(bridge->base + TSI148_LCSR_VIACK[i] + 3);
243 vme_irq_handler(tsi148_bridge, i, vec);
245 serviced |= (1 << i);
253 * Top level interrupt handler. Clears appropriate interrupt status bits and
254 * then calls appropriate sub handler(s).
256 static irqreturn_t tsi148_irqhandler(int irq, void *ptr)
258 u32 stat, enable, serviced = 0;
259 struct vme_bridge *tsi148_bridge;
260 struct tsi148_driver *bridge;
264 bridge = tsi148_bridge->driver_priv;
266 /* Determine which interrupts are unmasked and set */
267 enable = ioread32be(bridge->base + TSI148_LCSR_INTEO);
268 stat = ioread32be(bridge->base + TSI148_LCSR_INTS);
270 /* Only look at unmasked interrupts */
276 /* Call subhandlers as appropriate */
278 if (stat & (TSI148_LCSR_INTS_DMA1S | TSI148_LCSR_INTS_DMA0S))
279 serviced |= tsi148_DMA_irqhandler(bridge, stat);
281 /* Location monitor irqs */
282 if (stat & (TSI148_LCSR_INTS_LM3S | TSI148_LCSR_INTS_LM2S |
283 TSI148_LCSR_INTS_LM1S | TSI148_LCSR_INTS_LM0S))
284 serviced |= tsi148_LM_irqhandler(bridge, stat);
287 if (stat & (TSI148_LCSR_INTS_MB3S | TSI148_LCSR_INTS_MB2S |
288 TSI148_LCSR_INTS_MB1S | TSI148_LCSR_INTS_MB0S))
289 serviced |= tsi148_MB_irqhandler(tsi148_bridge, stat);
292 if (stat & TSI148_LCSR_INTS_PERRS)
293 serviced |= tsi148_PERR_irqhandler(tsi148_bridge);
296 if (stat & TSI148_LCSR_INTS_VERRS)
297 serviced |= tsi148_VERR_irqhandler(tsi148_bridge);
300 if (stat & TSI148_LCSR_INTS_IACKS)
301 serviced |= tsi148_IACK_irqhandler(bridge);
304 if (stat & (TSI148_LCSR_INTS_IRQ7S | TSI148_LCSR_INTS_IRQ6S |
305 TSI148_LCSR_INTS_IRQ5S | TSI148_LCSR_INTS_IRQ4S |
306 TSI148_LCSR_INTS_IRQ3S | TSI148_LCSR_INTS_IRQ2S |
307 TSI148_LCSR_INTS_IRQ1S))
308 serviced |= tsi148_VIRQ_irqhandler(tsi148_bridge, stat);
310 /* Clear serviced interrupts */
311 iowrite32be(serviced, bridge->base + TSI148_LCSR_INTC);
316 static int tsi148_irq_init(struct vme_bridge *tsi148_bridge)
320 struct pci_dev *pdev;
321 struct tsi148_driver *bridge;
323 pdev = to_pci_dev(tsi148_bridge->parent);
325 bridge = tsi148_bridge->driver_priv;
327 /* Initialise list for VME bus errors */
328 INIT_LIST_HEAD(&tsi148_bridge->vme_errors);
330 mutex_init(&tsi148_bridge->irq_mtx);
332 result = request_irq(pdev->irq,
335 driver_name, tsi148_bridge);
337 dev_err(tsi148_bridge->parent, "Can't get assigned pci irq "
338 "vector %02X\n", pdev->irq);
342 /* Enable and unmask interrupts */
343 tmp = TSI148_LCSR_INTEO_DMA1EO | TSI148_LCSR_INTEO_DMA0EO |
344 TSI148_LCSR_INTEO_MB3EO | TSI148_LCSR_INTEO_MB2EO |
345 TSI148_LCSR_INTEO_MB1EO | TSI148_LCSR_INTEO_MB0EO |
346 TSI148_LCSR_INTEO_PERREO | TSI148_LCSR_INTEO_VERREO |
347 TSI148_LCSR_INTEO_IACKEO;
349 /* This leaves the following interrupts masked.
350 * TSI148_LCSR_INTEO_VIEEO
351 * TSI148_LCSR_INTEO_SYSFLEO
352 * TSI148_LCSR_INTEO_ACFLEO
355 /* Don't enable Location Monitor interrupts here - they will be
356 * enabled when the location monitors are properly configured and
357 * a callback has been attached.
358 * TSI148_LCSR_INTEO_LM0EO
359 * TSI148_LCSR_INTEO_LM1EO
360 * TSI148_LCSR_INTEO_LM2EO
361 * TSI148_LCSR_INTEO_LM3EO
364 /* Don't enable VME interrupts until we add a handler, else the board
365 * will respond to it and we don't want that unless it knows how to
366 * properly deal with it.
367 * TSI148_LCSR_INTEO_IRQ7EO
368 * TSI148_LCSR_INTEO_IRQ6EO
369 * TSI148_LCSR_INTEO_IRQ5EO
370 * TSI148_LCSR_INTEO_IRQ4EO
371 * TSI148_LCSR_INTEO_IRQ3EO
372 * TSI148_LCSR_INTEO_IRQ2EO
373 * TSI148_LCSR_INTEO_IRQ1EO
376 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
377 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
382 static void tsi148_irq_exit(struct vme_bridge *tsi148_bridge,
383 struct pci_dev *pdev)
385 struct tsi148_driver *bridge = tsi148_bridge->driver_priv;
387 /* Turn off interrupts */
388 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEO);
389 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEN);
391 /* Clear all interrupts */
392 iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_INTC);
394 /* Detach interrupt handler */
395 free_irq(pdev->irq, tsi148_bridge);
399 * Check to see if an IACk has been received, return true (1) or false (0).
401 static int tsi148_iack_received(struct tsi148_driver *bridge)
405 tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);
407 if (tmp & TSI148_LCSR_VICR_IRQS)
414 * Configure VME interrupt
416 static void tsi148_irq_set(struct vme_bridge *tsi148_bridge, int level,
419 struct pci_dev *pdev;
421 struct tsi148_driver *bridge;
423 bridge = tsi148_bridge->driver_priv;
425 /* We need to do the ordering differently for enabling and disabling */
427 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
428 tmp &= ~TSI148_LCSR_INTEN_IRQEN[level - 1];
429 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
431 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
432 tmp &= ~TSI148_LCSR_INTEO_IRQEO[level - 1];
433 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
436 pdev = to_pci_dev(tsi148_bridge->parent);
437 synchronize_irq(pdev->irq);
440 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
441 tmp |= TSI148_LCSR_INTEO_IRQEO[level - 1];
442 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
444 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
445 tmp |= TSI148_LCSR_INTEN_IRQEN[level - 1];
446 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
451 * Generate a VME bus interrupt at the requested level & vector. Wait for
452 * interrupt to be acked.
454 static int tsi148_irq_generate(struct vme_bridge *tsi148_bridge, int level,
458 struct tsi148_driver *bridge;
460 bridge = tsi148_bridge->driver_priv;
462 mutex_lock(&bridge->vme_int);
464 /* Read VICR register */
465 tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);
468 tmp = (tmp & ~TSI148_LCSR_VICR_STID_M) |
469 (statid & TSI148_LCSR_VICR_STID_M);
470 iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);
472 /* Assert VMEbus IRQ */
473 tmp = tmp | TSI148_LCSR_VICR_IRQL[level];
474 iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);
476 /* XXX Consider implementing a timeout? */
477 wait_event_interruptible(bridge->iack_queue,
478 tsi148_iack_received(bridge));
480 mutex_unlock(&bridge->vme_int);
486 * Find the first error in this address range
488 static struct vme_bus_error *tsi148_find_error(struct vme_bridge *tsi148_bridge,
489 u32 aspace, unsigned long long address, size_t count)
491 struct list_head *err_pos;
492 struct vme_bus_error *vme_err, *valid = NULL;
493 unsigned long long bound;
495 bound = address + count;
498 * XXX We are currently not looking at the address space when parsing
499 * for errors. This is because parsing the Address Modifier Codes
500 * is going to be quite resource intensive to do properly. We
501 * should be OK just looking at the addresses and this is certainly
502 * much better than what we had before.
505 /* Iterate through errors */
506 list_for_each(err_pos, &tsi148_bridge->vme_errors) {
507 vme_err = list_entry(err_pos, struct vme_bus_error, list);
508 if ((vme_err->address >= address) &&
509 (vme_err->address < bound)) {
520 * Clear errors in the provided address range.
522 static void tsi148_clear_errors(struct vme_bridge *tsi148_bridge,
523 u32 aspace, unsigned long long address, size_t count)
525 struct list_head *err_pos, *temp;
526 struct vme_bus_error *vme_err;
527 unsigned long long bound;
529 bound = address + count;
532 * XXX We are currently not looking at the address space when parsing
533 * for errors. This is because parsing the Address Modifier Codes
534 * is going to be quite resource intensive to do properly. We
535 * should be OK just looking at the addresses and this is certainly
536 * much better than what we had before.
539 /* Iterate through errors */
540 list_for_each_safe(err_pos, temp, &tsi148_bridge->vme_errors) {
541 vme_err = list_entry(err_pos, struct vme_bus_error, list);
543 if ((vme_err->address >= address) &&
544 (vme_err->address < bound)) {
553 * Initialize a slave window with the requested attributes.
555 static int tsi148_slave_set(struct vme_slave_resource *image, int enabled,
556 unsigned long long vme_base, unsigned long long size,
557 dma_addr_t pci_base, u32 aspace, u32 cycle)
559 unsigned int i, addr = 0, granularity = 0;
560 unsigned int temp_ctl = 0;
561 unsigned int vme_base_low, vme_base_high;
562 unsigned int vme_bound_low, vme_bound_high;
563 unsigned int pci_offset_low, pci_offset_high;
564 unsigned long long vme_bound, pci_offset;
565 struct vme_bridge *tsi148_bridge;
566 struct tsi148_driver *bridge;
568 tsi148_bridge = image->parent;
569 bridge = tsi148_bridge->driver_priv;
576 addr |= TSI148_LCSR_ITAT_AS_A16;
579 granularity = 0x1000;
580 addr |= TSI148_LCSR_ITAT_AS_A24;
583 granularity = 0x10000;
584 addr |= TSI148_LCSR_ITAT_AS_A32;
587 granularity = 0x10000;
588 addr |= TSI148_LCSR_ITAT_AS_A64;
591 dev_err(tsi148_bridge->parent, "Invalid address space\n");
596 /* Convert 64-bit variables to 2x 32-bit variables */
597 reg_split(vme_base, &vme_base_high, &vme_base_low);
600 * Bound address is a valid address for the window, adjust
603 vme_bound = vme_base + size - granularity;
604 reg_split(vme_bound, &vme_bound_high, &vme_bound_low);
605 pci_offset = (unsigned long long)pci_base - vme_base;
606 reg_split(pci_offset, &pci_offset_high, &pci_offset_low);
608 if (vme_base_low & (granularity - 1)) {
609 dev_err(tsi148_bridge->parent, "Invalid VME base alignment\n");
612 if (vme_bound_low & (granularity - 1)) {
613 dev_err(tsi148_bridge->parent, "Invalid VME bound alignment\n");
616 if (pci_offset_low & (granularity - 1)) {
617 dev_err(tsi148_bridge->parent, "Invalid PCI Offset "
622 /* Disable while we are mucking around */
623 temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
624 TSI148_LCSR_OFFSET_ITAT);
625 temp_ctl &= ~TSI148_LCSR_ITAT_EN;
626 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
627 TSI148_LCSR_OFFSET_ITAT);
630 iowrite32be(vme_base_high, bridge->base + TSI148_LCSR_IT[i] +
631 TSI148_LCSR_OFFSET_ITSAU);
632 iowrite32be(vme_base_low, bridge->base + TSI148_LCSR_IT[i] +
633 TSI148_LCSR_OFFSET_ITSAL);
634 iowrite32be(vme_bound_high, bridge->base + TSI148_LCSR_IT[i] +
635 TSI148_LCSR_OFFSET_ITEAU);
636 iowrite32be(vme_bound_low, bridge->base + TSI148_LCSR_IT[i] +
637 TSI148_LCSR_OFFSET_ITEAL);
638 iowrite32be(pci_offset_high, bridge->base + TSI148_LCSR_IT[i] +
639 TSI148_LCSR_OFFSET_ITOFU);
640 iowrite32be(pci_offset_low, bridge->base + TSI148_LCSR_IT[i] +
641 TSI148_LCSR_OFFSET_ITOFL);
643 /* Setup 2eSST speeds */
644 temp_ctl &= ~TSI148_LCSR_ITAT_2eSSTM_M;
645 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
647 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_160;
650 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_267;
653 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_320;
657 /* Setup cycle types */
658 temp_ctl &= ~(0x1F << 7);
660 temp_ctl |= TSI148_LCSR_ITAT_BLT;
661 if (cycle & VME_MBLT)
662 temp_ctl |= TSI148_LCSR_ITAT_MBLT;
663 if (cycle & VME_2eVME)
664 temp_ctl |= TSI148_LCSR_ITAT_2eVME;
665 if (cycle & VME_2eSST)
666 temp_ctl |= TSI148_LCSR_ITAT_2eSST;
667 if (cycle & VME_2eSSTB)
668 temp_ctl |= TSI148_LCSR_ITAT_2eSSTB;
670 /* Setup address space */
671 temp_ctl &= ~TSI148_LCSR_ITAT_AS_M;
675 if (cycle & VME_SUPER)
676 temp_ctl |= TSI148_LCSR_ITAT_SUPR ;
677 if (cycle & VME_USER)
678 temp_ctl |= TSI148_LCSR_ITAT_NPRIV;
679 if (cycle & VME_PROG)
680 temp_ctl |= TSI148_LCSR_ITAT_PGM;
681 if (cycle & VME_DATA)
682 temp_ctl |= TSI148_LCSR_ITAT_DATA;
684 /* Write ctl reg without enable */
685 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
686 TSI148_LCSR_OFFSET_ITAT);
689 temp_ctl |= TSI148_LCSR_ITAT_EN;
691 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
692 TSI148_LCSR_OFFSET_ITAT);
698 * Get slave window configuration.
700 static int tsi148_slave_get(struct vme_slave_resource *image, int *enabled,
701 unsigned long long *vme_base, unsigned long long *size,
702 dma_addr_t *pci_base, u32 *aspace, u32 *cycle)
704 unsigned int i, granularity = 0, ctl = 0;
705 unsigned int vme_base_low, vme_base_high;
706 unsigned int vme_bound_low, vme_bound_high;
707 unsigned int pci_offset_low, pci_offset_high;
708 unsigned long long vme_bound, pci_offset;
709 struct tsi148_driver *bridge;
711 bridge = image->parent->driver_priv;
716 ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
717 TSI148_LCSR_OFFSET_ITAT);
719 vme_base_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
720 TSI148_LCSR_OFFSET_ITSAU);
721 vme_base_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
722 TSI148_LCSR_OFFSET_ITSAL);
723 vme_bound_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
724 TSI148_LCSR_OFFSET_ITEAU);
725 vme_bound_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
726 TSI148_LCSR_OFFSET_ITEAL);
727 pci_offset_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
728 TSI148_LCSR_OFFSET_ITOFU);
729 pci_offset_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
730 TSI148_LCSR_OFFSET_ITOFL);
732 /* Convert 64-bit variables to 2x 32-bit variables */
733 reg_join(vme_base_high, vme_base_low, vme_base);
734 reg_join(vme_bound_high, vme_bound_low, &vme_bound);
735 reg_join(pci_offset_high, pci_offset_low, &pci_offset);
737 *pci_base = (dma_addr_t)(*vme_base + pci_offset);
743 if (ctl & TSI148_LCSR_ITAT_EN)
746 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A16) {
750 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A24) {
751 granularity = 0x1000;
754 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A32) {
755 granularity = 0x10000;
758 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A64) {
759 granularity = 0x10000;
763 /* Need granularity before we set the size */
764 *size = (unsigned long long)((vme_bound - *vme_base) + granularity);
767 if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_160)
768 *cycle |= VME_2eSST160;
769 if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_267)
770 *cycle |= VME_2eSST267;
771 if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_320)
772 *cycle |= VME_2eSST320;
774 if (ctl & TSI148_LCSR_ITAT_BLT)
776 if (ctl & TSI148_LCSR_ITAT_MBLT)
778 if (ctl & TSI148_LCSR_ITAT_2eVME)
780 if (ctl & TSI148_LCSR_ITAT_2eSST)
782 if (ctl & TSI148_LCSR_ITAT_2eSSTB)
783 *cycle |= VME_2eSSTB;
785 if (ctl & TSI148_LCSR_ITAT_SUPR)
787 if (ctl & TSI148_LCSR_ITAT_NPRIV)
789 if (ctl & TSI148_LCSR_ITAT_PGM)
791 if (ctl & TSI148_LCSR_ITAT_DATA)
798 * Allocate and map PCI Resource
800 static int tsi148_alloc_resource(struct vme_master_resource *image,
801 unsigned long long size)
803 unsigned long long existing_size;
805 struct pci_dev *pdev;
806 struct vme_bridge *tsi148_bridge;
808 tsi148_bridge = image->parent;
810 pdev = to_pci_dev(tsi148_bridge->parent);
812 existing_size = (unsigned long long)(image->bus_resource.end -
813 image->bus_resource.start);
815 /* If the existing size is OK, return */
816 if ((size != 0) && (existing_size == (size - 1)))
819 if (existing_size != 0) {
820 iounmap(image->kern_base);
821 image->kern_base = NULL;
822 kfree(image->bus_resource.name);
823 release_resource(&image->bus_resource);
824 memset(&image->bus_resource, 0, sizeof(struct resource));
827 /* Exit here if size is zero */
831 if (image->bus_resource.name == NULL) {
832 image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_ATOMIC);
833 if (image->bus_resource.name == NULL) {
834 dev_err(tsi148_bridge->parent, "Unable to allocate "
835 "memory for resource name\n");
841 sprintf((char *)image->bus_resource.name, "%s.%d", tsi148_bridge->name,
844 image->bus_resource.start = 0;
845 image->bus_resource.end = (unsigned long)size;
846 image->bus_resource.flags = IORESOURCE_MEM;
848 retval = pci_bus_alloc_resource(pdev->bus,
849 &image->bus_resource, size, size, PCIBIOS_MIN_MEM,
852 dev_err(tsi148_bridge->parent, "Failed to allocate mem "
853 "resource for window %d size 0x%lx start 0x%lx\n",
854 image->number, (unsigned long)size,
855 (unsigned long)image->bus_resource.start);
859 image->kern_base = ioremap_nocache(
860 image->bus_resource.start, size);
861 if (image->kern_base == NULL) {
862 dev_err(tsi148_bridge->parent, "Failed to remap resource\n");
870 release_resource(&image->bus_resource);
872 kfree(image->bus_resource.name);
873 memset(&image->bus_resource, 0, sizeof(struct resource));
879 * Free and unmap PCI Resource
881 static void tsi148_free_resource(struct vme_master_resource *image)
883 iounmap(image->kern_base);
884 image->kern_base = NULL;
885 release_resource(&image->bus_resource);
886 kfree(image->bus_resource.name);
887 memset(&image->bus_resource, 0, sizeof(struct resource));
891 * Set the attributes of an outbound window.
893 static int tsi148_master_set(struct vme_master_resource *image, int enabled,
894 unsigned long long vme_base, unsigned long long size, u32 aspace,
895 u32 cycle, u32 dwidth)
899 unsigned int temp_ctl = 0;
900 unsigned int pci_base_low, pci_base_high;
901 unsigned int pci_bound_low, pci_bound_high;
902 unsigned int vme_offset_low, vme_offset_high;
903 unsigned long long pci_bound, vme_offset, pci_base;
904 struct vme_bridge *tsi148_bridge;
905 struct tsi148_driver *bridge;
906 struct pci_bus_region region;
907 struct pci_dev *pdev;
909 tsi148_bridge = image->parent;
911 bridge = tsi148_bridge->driver_priv;
913 pdev = to_pci_dev(tsi148_bridge->parent);
915 /* Verify input data */
916 if (vme_base & 0xFFFF) {
917 dev_err(tsi148_bridge->parent, "Invalid VME Window "
923 if ((size == 0) && (enabled != 0)) {
924 dev_err(tsi148_bridge->parent, "Size must be non-zero for "
925 "enabled windows\n");
930 spin_lock(&image->lock);
932 /* Let's allocate the resource here rather than further up the stack as
933 * it avoids pushing loads of bus dependent stuff up the stack. If size
934 * is zero, any existing resource will be freed.
936 retval = tsi148_alloc_resource(image, size);
938 spin_unlock(&image->lock);
939 dev_err(tsi148_bridge->parent, "Unable to allocate memory for "
949 pcibios_resource_to_bus(pdev->bus, ®ion,
950 &image->bus_resource);
951 pci_base = region.start;
954 * Bound address is a valid address for the window, adjust
955 * according to window granularity.
957 pci_bound = pci_base + (size - 0x10000);
958 vme_offset = vme_base - pci_base;
961 /* Convert 64-bit variables to 2x 32-bit variables */
962 reg_split(pci_base, &pci_base_high, &pci_base_low);
963 reg_split(pci_bound, &pci_bound_high, &pci_bound_low);
964 reg_split(vme_offset, &vme_offset_high, &vme_offset_low);
966 if (pci_base_low & 0xFFFF) {
967 spin_unlock(&image->lock);
968 dev_err(tsi148_bridge->parent, "Invalid PCI base alignment\n");
972 if (pci_bound_low & 0xFFFF) {
973 spin_unlock(&image->lock);
974 dev_err(tsi148_bridge->parent, "Invalid PCI bound alignment\n");
978 if (vme_offset_low & 0xFFFF) {
979 spin_unlock(&image->lock);
980 dev_err(tsi148_bridge->parent, "Invalid VME Offset "
988 /* Disable while we are mucking around */
989 temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
990 TSI148_LCSR_OFFSET_OTAT);
991 temp_ctl &= ~TSI148_LCSR_OTAT_EN;
992 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
993 TSI148_LCSR_OFFSET_OTAT);
995 /* Setup 2eSST speeds */
996 temp_ctl &= ~TSI148_LCSR_OTAT_2eSSTM_M;
997 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
999 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_160;
1002 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_267;
1005 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_320;
1009 /* Setup cycle types */
1010 if (cycle & VME_BLT) {
1011 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1012 temp_ctl |= TSI148_LCSR_OTAT_TM_BLT;
1014 if (cycle & VME_MBLT) {
1015 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1016 temp_ctl |= TSI148_LCSR_OTAT_TM_MBLT;
1018 if (cycle & VME_2eVME) {
1019 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1020 temp_ctl |= TSI148_LCSR_OTAT_TM_2eVME;
1022 if (cycle & VME_2eSST) {
1023 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1024 temp_ctl |= TSI148_LCSR_OTAT_TM_2eSST;
1026 if (cycle & VME_2eSSTB) {
1027 dev_warn(tsi148_bridge->parent, "Currently not setting "
1028 "Broadcast Select Registers\n");
1029 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1030 temp_ctl |= TSI148_LCSR_OTAT_TM_2eSSTB;
1033 /* Setup data width */
1034 temp_ctl &= ~TSI148_LCSR_OTAT_DBW_M;
1037 temp_ctl |= TSI148_LCSR_OTAT_DBW_16;
1040 temp_ctl |= TSI148_LCSR_OTAT_DBW_32;
1043 spin_unlock(&image->lock);
1044 dev_err(tsi148_bridge->parent, "Invalid data width\n");
1049 /* Setup address space */
1050 temp_ctl &= ~TSI148_LCSR_OTAT_AMODE_M;
1053 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A16;
1056 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A24;
1059 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A32;
1062 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A64;
1065 temp_ctl |= TSI148_LCSR_OTAT_AMODE_CRCSR;
1068 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER1;
1071 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER2;
1074 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER3;
1077 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER4;
1080 spin_unlock(&image->lock);
1081 dev_err(tsi148_bridge->parent, "Invalid address space\n");
1087 temp_ctl &= ~(3<<4);
1088 if (cycle & VME_SUPER)
1089 temp_ctl |= TSI148_LCSR_OTAT_SUP;
1090 if (cycle & VME_PROG)
1091 temp_ctl |= TSI148_LCSR_OTAT_PGM;
1094 iowrite32be(pci_base_high, bridge->base + TSI148_LCSR_OT[i] +
1095 TSI148_LCSR_OFFSET_OTSAU);
1096 iowrite32be(pci_base_low, bridge->base + TSI148_LCSR_OT[i] +
1097 TSI148_LCSR_OFFSET_OTSAL);
1098 iowrite32be(pci_bound_high, bridge->base + TSI148_LCSR_OT[i] +
1099 TSI148_LCSR_OFFSET_OTEAU);
1100 iowrite32be(pci_bound_low, bridge->base + TSI148_LCSR_OT[i] +
1101 TSI148_LCSR_OFFSET_OTEAL);
1102 iowrite32be(vme_offset_high, bridge->base + TSI148_LCSR_OT[i] +
1103 TSI148_LCSR_OFFSET_OTOFU);
1104 iowrite32be(vme_offset_low, bridge->base + TSI148_LCSR_OT[i] +
1105 TSI148_LCSR_OFFSET_OTOFL);
1107 /* Write ctl reg without enable */
1108 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
1109 TSI148_LCSR_OFFSET_OTAT);
1112 temp_ctl |= TSI148_LCSR_OTAT_EN;
1114 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
1115 TSI148_LCSR_OFFSET_OTAT);
1117 spin_unlock(&image->lock);
1123 tsi148_free_resource(image);
1131 * Set the attributes of an outbound window.
1133 * XXX Not parsing prefetch information.
1135 static int __tsi148_master_get(struct vme_master_resource *image, int *enabled,
1136 unsigned long long *vme_base, unsigned long long *size, u32 *aspace,
1137 u32 *cycle, u32 *dwidth)
1139 unsigned int i, ctl;
1140 unsigned int pci_base_low, pci_base_high;
1141 unsigned int pci_bound_low, pci_bound_high;
1142 unsigned int vme_offset_low, vme_offset_high;
1144 unsigned long long pci_base, pci_bound, vme_offset;
1145 struct tsi148_driver *bridge;
1147 bridge = image->parent->driver_priv;
1151 ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1152 TSI148_LCSR_OFFSET_OTAT);
1154 pci_base_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1155 TSI148_LCSR_OFFSET_OTSAU);
1156 pci_base_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1157 TSI148_LCSR_OFFSET_OTSAL);
1158 pci_bound_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1159 TSI148_LCSR_OFFSET_OTEAU);
1160 pci_bound_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1161 TSI148_LCSR_OFFSET_OTEAL);
1162 vme_offset_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1163 TSI148_LCSR_OFFSET_OTOFU);
1164 vme_offset_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1165 TSI148_LCSR_OFFSET_OTOFL);
1167 /* Convert 64-bit variables to 2x 32-bit variables */
1168 reg_join(pci_base_high, pci_base_low, &pci_base);
1169 reg_join(pci_bound_high, pci_bound_low, &pci_bound);
1170 reg_join(vme_offset_high, vme_offset_low, &vme_offset);
1172 *vme_base = pci_base + vme_offset;
1173 *size = (unsigned long long)(pci_bound - pci_base) + 0x10000;
1180 if (ctl & TSI148_LCSR_OTAT_EN)
1183 /* Setup address space */
1184 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A16)
1186 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A24)
1188 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A32)
1190 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A64)
1192 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_CRCSR)
1193 *aspace |= VME_CRCSR;
1194 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER1)
1195 *aspace |= VME_USER1;
1196 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER2)
1197 *aspace |= VME_USER2;
1198 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER3)
1199 *aspace |= VME_USER3;
1200 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER4)
1201 *aspace |= VME_USER4;
1203 /* Setup 2eSST speeds */
1204 if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_160)
1205 *cycle |= VME_2eSST160;
1206 if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_267)
1207 *cycle |= VME_2eSST267;
1208 if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_320)
1209 *cycle |= VME_2eSST320;
1211 /* Setup cycle types */
1212 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_SCT)
1214 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_BLT)
1216 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_MBLT)
1218 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eVME)
1219 *cycle |= VME_2eVME;
1220 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eSST)
1221 *cycle |= VME_2eSST;
1222 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eSSTB)
1223 *cycle |= VME_2eSSTB;
1225 if (ctl & TSI148_LCSR_OTAT_SUP)
1226 *cycle |= VME_SUPER;
1230 if (ctl & TSI148_LCSR_OTAT_PGM)
1235 /* Setup data width */
1236 if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_16)
1238 if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_32)
1245 static int tsi148_master_get(struct vme_master_resource *image, int *enabled,
1246 unsigned long long *vme_base, unsigned long long *size, u32 *aspace,
1247 u32 *cycle, u32 *dwidth)
1251 spin_lock(&image->lock);
1253 retval = __tsi148_master_get(image, enabled, vme_base, size, aspace,
1256 spin_unlock(&image->lock);
1261 static ssize_t tsi148_master_read(struct vme_master_resource *image, void *buf,
1262 size_t count, loff_t offset)
1264 int retval, enabled;
1265 unsigned long long vme_base, size;
1266 u32 aspace, cycle, dwidth;
1267 struct vme_bus_error *vme_err = NULL;
1268 struct vme_bridge *tsi148_bridge;
1269 void __iomem *addr = image->kern_base + offset;
1270 unsigned int done = 0;
1271 unsigned int count32;
1273 tsi148_bridge = image->parent;
1275 spin_lock(&image->lock);
1277 /* The following code handles VME address alignment. We cannot use
1278 * memcpy_xxx here because it may cut data transfers in to 8-bit
1279 * cycles when D16 or D32 cycles are required on the VME bus.
1280 * On the other hand, the bridge itself assures that the maximum data
1281 * cycle configured for the transfer is used and splits it
1282 * automatically for non-aligned addresses, so we don't want the
1283 * overhead of needlessly forcing small transfers for the entire cycle.
1285 if ((uintptr_t)addr & 0x1) {
1286 *(u8 *)buf = ioread8(addr);
1291 if ((uintptr_t)(addr + done) & 0x2) {
1292 if ((count - done) < 2) {
1293 *(u8 *)(buf + done) = ioread8(addr + done);
1297 *(u16 *)(buf + done) = ioread16(addr + done);
1302 count32 = (count - done) & ~0x3;
1303 while (done < count32) {
1304 *(u32 *)(buf + done) = ioread32(addr + done);
1308 if ((count - done) & 0x2) {
1309 *(u16 *)(buf + done) = ioread16(addr + done);
1312 if ((count - done) & 0x1) {
1313 *(u8 *)(buf + done) = ioread8(addr + done);
1323 __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle,
1326 vme_err = tsi148_find_error(tsi148_bridge, aspace, vme_base + offset,
1328 if (vme_err != NULL) {
1329 dev_err(image->parent->parent, "First VME read error detected "
1330 "an at address 0x%llx\n", vme_err->address);
1331 retval = vme_err->address - (vme_base + offset);
1332 /* Clear down save errors in this address range */
1333 tsi148_clear_errors(tsi148_bridge, aspace, vme_base + offset,
1338 spin_unlock(&image->lock);
1344 static ssize_t tsi148_master_write(struct vme_master_resource *image, void *buf,
1345 size_t count, loff_t offset)
1347 int retval = 0, enabled;
1348 unsigned long long vme_base, size;
1349 u32 aspace, cycle, dwidth;
1350 void __iomem *addr = image->kern_base + offset;
1351 unsigned int done = 0;
1352 unsigned int count32;
1354 struct vme_bus_error *vme_err = NULL;
1355 struct vme_bridge *tsi148_bridge;
1356 struct tsi148_driver *bridge;
1358 tsi148_bridge = image->parent;
1360 bridge = tsi148_bridge->driver_priv;
1362 spin_lock(&image->lock);
1364 /* Here we apply for the same strategy we do in master_read
1365 * function in order to assure the correct cycles.
1367 if ((uintptr_t)addr & 0x1) {
1368 iowrite8(*(u8 *)buf, addr);
1373 if ((uintptr_t)(addr + done) & 0x2) {
1374 if ((count - done) < 2) {
1375 iowrite8(*(u8 *)(buf + done), addr + done);
1379 iowrite16(*(u16 *)(buf + done), addr + done);
1384 count32 = (count - done) & ~0x3;
1385 while (done < count32) {
1386 iowrite32(*(u32 *)(buf + done), addr + done);
1390 if ((count - done) & 0x2) {
1391 iowrite16(*(u16 *)(buf + done), addr + done);
1394 if ((count - done) & 0x1) {
1395 iowrite8(*(u8 *)(buf + done), addr + done);
1403 * Writes are posted. We need to do a read on the VME bus to flush out
1404 * all of the writes before we check for errors. We can't guarantee
1405 * that reading the data we have just written is safe. It is believed
1406 * that there isn't any read, write re-ordering, so we can read any
1407 * location in VME space, so lets read the Device ID from the tsi148's
1408 * own registers as mapped into CR/CSR space.
1410 * We check for saved errors in the written address range/space.
1417 * Get window info first, to maximise the time that the buffers may
1418 * fluch on their own
1420 __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle,
1423 ioread16(bridge->flush_image->kern_base + 0x7F000);
1425 vme_err = tsi148_find_error(tsi148_bridge, aspace, vme_base + offset,
1427 if (vme_err != NULL) {
1428 dev_warn(tsi148_bridge->parent, "First VME write error detected"
1429 " an at address 0x%llx\n", vme_err->address);
1430 retval = vme_err->address - (vme_base + offset);
1431 /* Clear down save errors in this address range */
1432 tsi148_clear_errors(tsi148_bridge, aspace, vme_base + offset,
1437 spin_unlock(&image->lock);
1443 * Perform an RMW cycle on the VME bus.
1445 * Requires a previously configured master window, returns final value.
1447 static unsigned int tsi148_master_rmw(struct vme_master_resource *image,
1448 unsigned int mask, unsigned int compare, unsigned int swap,
1451 unsigned long long pci_addr;
1452 unsigned int pci_addr_high, pci_addr_low;
1455 struct tsi148_driver *bridge;
1457 bridge = image->parent->driver_priv;
1459 /* Find the PCI address that maps to the desired VME address */
1462 /* Locking as we can only do one of these at a time */
1463 mutex_lock(&bridge->vme_rmw);
1466 spin_lock(&image->lock);
1468 pci_addr_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1469 TSI148_LCSR_OFFSET_OTSAU);
1470 pci_addr_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1471 TSI148_LCSR_OFFSET_OTSAL);
1473 reg_join(pci_addr_high, pci_addr_low, &pci_addr);
1474 reg_split(pci_addr + offset, &pci_addr_high, &pci_addr_low);
1476 /* Configure registers */
1477 iowrite32be(mask, bridge->base + TSI148_LCSR_RMWEN);
1478 iowrite32be(compare, bridge->base + TSI148_LCSR_RMWC);
1479 iowrite32be(swap, bridge->base + TSI148_LCSR_RMWS);
1480 iowrite32be(pci_addr_high, bridge->base + TSI148_LCSR_RMWAU);
1481 iowrite32be(pci_addr_low, bridge->base + TSI148_LCSR_RMWAL);
1484 tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);
1485 tmp |= TSI148_LCSR_VMCTRL_RMWEN;
1486 iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);
1488 /* Kick process off with a read to the required address. */
1489 result = ioread32be(image->kern_base + offset);
1492 tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);
1493 tmp &= ~TSI148_LCSR_VMCTRL_RMWEN;
1494 iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);
1496 spin_unlock(&image->lock);
1498 mutex_unlock(&bridge->vme_rmw);
1503 static int tsi148_dma_set_vme_src_attributes(struct device *dev, __be32 *attr,
1504 u32 aspace, u32 cycle, u32 dwidth)
1508 val = be32_to_cpu(*attr);
1510 /* Setup 2eSST speeds */
1511 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
1513 val |= TSI148_LCSR_DSAT_2eSSTM_160;
1516 val |= TSI148_LCSR_DSAT_2eSSTM_267;
1519 val |= TSI148_LCSR_DSAT_2eSSTM_320;
1523 /* Setup cycle types */
1524 if (cycle & VME_SCT)
1525 val |= TSI148_LCSR_DSAT_TM_SCT;
1527 if (cycle & VME_BLT)
1528 val |= TSI148_LCSR_DSAT_TM_BLT;
1530 if (cycle & VME_MBLT)
1531 val |= TSI148_LCSR_DSAT_TM_MBLT;
1533 if (cycle & VME_2eVME)
1534 val |= TSI148_LCSR_DSAT_TM_2eVME;
1536 if (cycle & VME_2eSST)
1537 val |= TSI148_LCSR_DSAT_TM_2eSST;
1539 if (cycle & VME_2eSSTB) {
1540 dev_err(dev, "Currently not setting Broadcast Select "
1542 val |= TSI148_LCSR_DSAT_TM_2eSSTB;
1545 /* Setup data width */
1548 val |= TSI148_LCSR_DSAT_DBW_16;
1551 val |= TSI148_LCSR_DSAT_DBW_32;
1554 dev_err(dev, "Invalid data width\n");
1558 /* Setup address space */
1561 val |= TSI148_LCSR_DSAT_AMODE_A16;
1564 val |= TSI148_LCSR_DSAT_AMODE_A24;
1567 val |= TSI148_LCSR_DSAT_AMODE_A32;
1570 val |= TSI148_LCSR_DSAT_AMODE_A64;
1573 val |= TSI148_LCSR_DSAT_AMODE_CRCSR;
1576 val |= TSI148_LCSR_DSAT_AMODE_USER1;
1579 val |= TSI148_LCSR_DSAT_AMODE_USER2;
1582 val |= TSI148_LCSR_DSAT_AMODE_USER3;
1585 val |= TSI148_LCSR_DSAT_AMODE_USER4;
1588 dev_err(dev, "Invalid address space\n");
1593 if (cycle & VME_SUPER)
1594 val |= TSI148_LCSR_DSAT_SUP;
1595 if (cycle & VME_PROG)
1596 val |= TSI148_LCSR_DSAT_PGM;
1598 *attr = cpu_to_be32(val);
1603 static int tsi148_dma_set_vme_dest_attributes(struct device *dev, __be32 *attr,
1604 u32 aspace, u32 cycle, u32 dwidth)
1608 val = be32_to_cpu(*attr);
1610 /* Setup 2eSST speeds */
1611 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
1613 val |= TSI148_LCSR_DDAT_2eSSTM_160;
1616 val |= TSI148_LCSR_DDAT_2eSSTM_267;
1619 val |= TSI148_LCSR_DDAT_2eSSTM_320;
1623 /* Setup cycle types */
1624 if (cycle & VME_SCT)
1625 val |= TSI148_LCSR_DDAT_TM_SCT;
1627 if (cycle & VME_BLT)
1628 val |= TSI148_LCSR_DDAT_TM_BLT;
1630 if (cycle & VME_MBLT)
1631 val |= TSI148_LCSR_DDAT_TM_MBLT;
1633 if (cycle & VME_2eVME)
1634 val |= TSI148_LCSR_DDAT_TM_2eVME;
1636 if (cycle & VME_2eSST)
1637 val |= TSI148_LCSR_DDAT_TM_2eSST;
1639 if (cycle & VME_2eSSTB) {
1640 dev_err(dev, "Currently not setting Broadcast Select "
1642 val |= TSI148_LCSR_DDAT_TM_2eSSTB;
1645 /* Setup data width */
1648 val |= TSI148_LCSR_DDAT_DBW_16;
1651 val |= TSI148_LCSR_DDAT_DBW_32;
1654 dev_err(dev, "Invalid data width\n");
1658 /* Setup address space */
1661 val |= TSI148_LCSR_DDAT_AMODE_A16;
1664 val |= TSI148_LCSR_DDAT_AMODE_A24;
1667 val |= TSI148_LCSR_DDAT_AMODE_A32;
1670 val |= TSI148_LCSR_DDAT_AMODE_A64;
1673 val |= TSI148_LCSR_DDAT_AMODE_CRCSR;
1676 val |= TSI148_LCSR_DDAT_AMODE_USER1;
1679 val |= TSI148_LCSR_DDAT_AMODE_USER2;
1682 val |= TSI148_LCSR_DDAT_AMODE_USER3;
1685 val |= TSI148_LCSR_DDAT_AMODE_USER4;
1688 dev_err(dev, "Invalid address space\n");
1693 if (cycle & VME_SUPER)
1694 val |= TSI148_LCSR_DDAT_SUP;
1695 if (cycle & VME_PROG)
1696 val |= TSI148_LCSR_DDAT_PGM;
1698 *attr = cpu_to_be32(val);
1704 * Add a link list descriptor to the list
1706 * Note: DMA engine expects the DMA descriptor to be big endian.
1708 static int tsi148_dma_list_add(struct vme_dma_list *list,
1709 struct vme_dma_attr *src, struct vme_dma_attr *dest, size_t count)
1711 struct tsi148_dma_entry *entry, *prev;
1712 u32 address_high, address_low, val;
1713 struct vme_dma_pattern *pattern_attr;
1714 struct vme_dma_pci *pci_attr;
1715 struct vme_dma_vme *vme_attr;
1717 struct vme_bridge *tsi148_bridge;
1719 tsi148_bridge = list->parent->parent;
1721 /* Descriptor must be aligned on 64-bit boundaries */
1722 entry = kmalloc(sizeof(struct tsi148_dma_entry), GFP_KERNEL);
1723 if (entry == NULL) {
1724 dev_err(tsi148_bridge->parent, "Failed to allocate memory for "
1725 "dma resource structure\n");
1730 /* Test descriptor alignment */
1731 if ((unsigned long)&entry->descriptor & 0x7) {
1732 dev_err(tsi148_bridge->parent, "Descriptor not aligned to 8 "
1733 "byte boundary as required: %p\n",
1734 &entry->descriptor);
1739 /* Given we are going to fill out the structure, we probably don't
1740 * need to zero it, but better safe than sorry for now.
1742 memset(&entry->descriptor, 0, sizeof(struct tsi148_dma_descriptor));
1744 /* Fill out source part */
1745 switch (src->type) {
1746 case VME_DMA_PATTERN:
1747 pattern_attr = src->private;
1749 entry->descriptor.dsal = cpu_to_be32(pattern_attr->pattern);
1751 val = TSI148_LCSR_DSAT_TYP_PAT;
1753 /* Default behaviour is 32 bit pattern */
1754 if (pattern_attr->type & VME_DMA_PATTERN_BYTE)
1755 val |= TSI148_LCSR_DSAT_PSZ;
1757 /* It seems that the default behaviour is to increment */
1758 if ((pattern_attr->type & VME_DMA_PATTERN_INCREMENT) == 0)
1759 val |= TSI148_LCSR_DSAT_NIN;
1760 entry->descriptor.dsat = cpu_to_be32(val);
1763 pci_attr = src->private;
1765 reg_split((unsigned long long)pci_attr->address, &address_high,
1767 entry->descriptor.dsau = cpu_to_be32(address_high);
1768 entry->descriptor.dsal = cpu_to_be32(address_low);
1769 entry->descriptor.dsat = cpu_to_be32(TSI148_LCSR_DSAT_TYP_PCI);
1772 vme_attr = src->private;
1774 reg_split((unsigned long long)vme_attr->address, &address_high,
1776 entry->descriptor.dsau = cpu_to_be32(address_high);
1777 entry->descriptor.dsal = cpu_to_be32(address_low);
1778 entry->descriptor.dsat = cpu_to_be32(TSI148_LCSR_DSAT_TYP_VME);
1780 retval = tsi148_dma_set_vme_src_attributes(
1781 tsi148_bridge->parent, &entry->descriptor.dsat,
1782 vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth);
1787 dev_err(tsi148_bridge->parent, "Invalid source type\n");
1793 /* Assume last link - this will be over-written by adding another */
1794 entry->descriptor.dnlau = cpu_to_be32(0);
1795 entry->descriptor.dnlal = cpu_to_be32(TSI148_LCSR_DNLAL_LLA);
1797 /* Fill out destination part */
1798 switch (dest->type) {
1800 pci_attr = dest->private;
1802 reg_split((unsigned long long)pci_attr->address, &address_high,
1804 entry->descriptor.ddau = cpu_to_be32(address_high);
1805 entry->descriptor.ddal = cpu_to_be32(address_low);
1806 entry->descriptor.ddat = cpu_to_be32(TSI148_LCSR_DDAT_TYP_PCI);
1809 vme_attr = dest->private;
1811 reg_split((unsigned long long)vme_attr->address, &address_high,
1813 entry->descriptor.ddau = cpu_to_be32(address_high);
1814 entry->descriptor.ddal = cpu_to_be32(address_low);
1815 entry->descriptor.ddat = cpu_to_be32(TSI148_LCSR_DDAT_TYP_VME);
1817 retval = tsi148_dma_set_vme_dest_attributes(
1818 tsi148_bridge->parent, &entry->descriptor.ddat,
1819 vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth);
1824 dev_err(tsi148_bridge->parent, "Invalid destination type\n");
1830 /* Fill out count */
1831 entry->descriptor.dcnt = cpu_to_be32((u32)count);
1834 list_add_tail(&entry->list, &list->entries);
1836 entry->dma_handle = dma_map_single(tsi148_bridge->parent,
1838 sizeof(struct tsi148_dma_descriptor), DMA_TO_DEVICE);
1839 if (dma_mapping_error(tsi148_bridge->parent, entry->dma_handle)) {
1840 dev_err(tsi148_bridge->parent, "DMA mapping error\n");
1845 /* Fill out previous descriptors "Next Address" */
1846 if (entry->list.prev != &list->entries) {
1847 reg_split((unsigned long long)entry->dma_handle, &address_high,
1849 prev = list_entry(entry->list.prev, struct tsi148_dma_entry,
1851 prev->descriptor.dnlau = cpu_to_be32(address_high);
1852 prev->descriptor.dnlal = cpu_to_be32(address_low);
1868 * Check to see if the provided DMA channel is busy.
1870 static int tsi148_dma_busy(struct vme_bridge *tsi148_bridge, int channel)
1873 struct tsi148_driver *bridge;
1875 bridge = tsi148_bridge->driver_priv;
1877 tmp = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
1878 TSI148_LCSR_OFFSET_DSTA);
1880 if (tmp & TSI148_LCSR_DSTA_BSY)
1888 * Execute a previously generated link list
1890 * XXX Need to provide control register configuration.
1892 static int tsi148_dma_list_exec(struct vme_dma_list *list)
1894 struct vme_dma_resource *ctrlr;
1895 int channel, retval = 0;
1896 struct tsi148_dma_entry *entry;
1897 u32 bus_addr_high, bus_addr_low;
1898 u32 val, dctlreg = 0;
1899 struct vme_bridge *tsi148_bridge;
1900 struct tsi148_driver *bridge;
1902 ctrlr = list->parent;
1904 tsi148_bridge = ctrlr->parent;
1906 bridge = tsi148_bridge->driver_priv;
1908 mutex_lock(&ctrlr->mtx);
1910 channel = ctrlr->number;
1912 if (!list_empty(&ctrlr->running)) {
1914 * XXX We have an active DMA transfer and currently haven't
1915 * sorted out the mechanism for "pending" DMA transfers.
1918 /* Need to add to pending here */
1919 mutex_unlock(&ctrlr->mtx);
1922 list_add(&list->list, &ctrlr->running);
1925 /* Get first bus address and write into registers */
1926 entry = list_first_entry(&list->entries, struct tsi148_dma_entry,
1929 mutex_unlock(&ctrlr->mtx);
1931 reg_split(entry->dma_handle, &bus_addr_high, &bus_addr_low);
1933 iowrite32be(bus_addr_high, bridge->base +
1934 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAU);
1935 iowrite32be(bus_addr_low, bridge->base +
1936 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAL);
1938 dctlreg = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
1939 TSI148_LCSR_OFFSET_DCTL);
1941 /* Start the operation */
1942 iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, bridge->base +
1943 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL);
1945 wait_event_interruptible(bridge->dma_queue[channel],
1946 tsi148_dma_busy(ctrlr->parent, channel));
1949 * Read status register, this register is valid until we kick off a
1952 val = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
1953 TSI148_LCSR_OFFSET_DSTA);
1955 if (val & TSI148_LCSR_DSTA_VBE) {
1956 dev_err(tsi148_bridge->parent, "DMA Error. DSTA=%08X\n", val);
1960 /* Remove list from running list */
1961 mutex_lock(&ctrlr->mtx);
1962 list_del(&list->list);
1963 mutex_unlock(&ctrlr->mtx);
1969 * Clean up a previously generated link list
1971 * We have a separate function, don't assume that the chain can't be reused.
1973 static int tsi148_dma_list_empty(struct vme_dma_list *list)
1975 struct list_head *pos, *temp;
1976 struct tsi148_dma_entry *entry;
1978 struct vme_bridge *tsi148_bridge = list->parent->parent;
1980 /* detach and free each entry */
1981 list_for_each_safe(pos, temp, &list->entries) {
1983 entry = list_entry(pos, struct tsi148_dma_entry, list);
1985 dma_unmap_single(tsi148_bridge->parent, entry->dma_handle,
1986 sizeof(struct tsi148_dma_descriptor), DMA_TO_DEVICE);
1994 * All 4 location monitors reside at the same base - this is therefore a
1995 * system wide configuration.
1997 * This does not enable the LM monitor - that should be done when the first
1998 * callback is attached and disabled when the last callback is removed.
2000 static int tsi148_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base,
2001 u32 aspace, u32 cycle)
2003 u32 lm_base_high, lm_base_low, lm_ctl = 0;
2005 struct vme_bridge *tsi148_bridge;
2006 struct tsi148_driver *bridge;
2008 tsi148_bridge = lm->parent;
2010 bridge = tsi148_bridge->driver_priv;
2012 mutex_lock(&lm->mtx);
2014 /* If we already have a callback attached, we can't move it! */
2015 for (i = 0; i < lm->monitors; i++) {
2016 if (bridge->lm_callback[i] != NULL) {
2017 mutex_unlock(&lm->mtx);
2018 dev_err(tsi148_bridge->parent, "Location monitor "
2019 "callback attached, can't reset\n");
2026 lm_ctl |= TSI148_LCSR_LMAT_AS_A16;
2029 lm_ctl |= TSI148_LCSR_LMAT_AS_A24;
2032 lm_ctl |= TSI148_LCSR_LMAT_AS_A32;
2035 lm_ctl |= TSI148_LCSR_LMAT_AS_A64;
2038 mutex_unlock(&lm->mtx);
2039 dev_err(tsi148_bridge->parent, "Invalid address space\n");
2044 if (cycle & VME_SUPER)
2045 lm_ctl |= TSI148_LCSR_LMAT_SUPR ;
2046 if (cycle & VME_USER)
2047 lm_ctl |= TSI148_LCSR_LMAT_NPRIV;
2048 if (cycle & VME_PROG)
2049 lm_ctl |= TSI148_LCSR_LMAT_PGM;
2050 if (cycle & VME_DATA)
2051 lm_ctl |= TSI148_LCSR_LMAT_DATA;
2053 reg_split(lm_base, &lm_base_high, &lm_base_low);
2055 iowrite32be(lm_base_high, bridge->base + TSI148_LCSR_LMBAU);
2056 iowrite32be(lm_base_low, bridge->base + TSI148_LCSR_LMBAL);
2057 iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);
2059 mutex_unlock(&lm->mtx);
2064 /* Get configuration of the callback monitor and return whether it is enabled
2067 static int tsi148_lm_get(struct vme_lm_resource *lm,
2068 unsigned long long *lm_base, u32 *aspace, u32 *cycle)
2070 u32 lm_base_high, lm_base_low, lm_ctl, enabled = 0;
2071 struct tsi148_driver *bridge;
2073 bridge = lm->parent->driver_priv;
2075 mutex_lock(&lm->mtx);
2077 lm_base_high = ioread32be(bridge->base + TSI148_LCSR_LMBAU);
2078 lm_base_low = ioread32be(bridge->base + TSI148_LCSR_LMBAL);
2079 lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);
2081 reg_join(lm_base_high, lm_base_low, lm_base);
2083 if (lm_ctl & TSI148_LCSR_LMAT_EN)
2086 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A16)
2089 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A24)
2092 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A32)
2095 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A64)
2099 if (lm_ctl & TSI148_LCSR_LMAT_SUPR)
2100 *cycle |= VME_SUPER;
2101 if (lm_ctl & TSI148_LCSR_LMAT_NPRIV)
2103 if (lm_ctl & TSI148_LCSR_LMAT_PGM)
2105 if (lm_ctl & TSI148_LCSR_LMAT_DATA)
2108 mutex_unlock(&lm->mtx);
2114 * Attach a callback to a specific location monitor.
2116 * Callback will be passed the monitor triggered.
2118 static int tsi148_lm_attach(struct vme_lm_resource *lm, int monitor,
2119 void (*callback)(int))
2122 struct vme_bridge *tsi148_bridge;
2123 struct tsi148_driver *bridge;
2125 tsi148_bridge = lm->parent;
2127 bridge = tsi148_bridge->driver_priv;
2129 mutex_lock(&lm->mtx);
2131 /* Ensure that the location monitor is configured - need PGM or DATA */
2132 lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);
2133 if ((lm_ctl & (TSI148_LCSR_LMAT_PGM | TSI148_LCSR_LMAT_DATA)) == 0) {
2134 mutex_unlock(&lm->mtx);
2135 dev_err(tsi148_bridge->parent, "Location monitor not properly "
2140 /* Check that a callback isn't already attached */
2141 if (bridge->lm_callback[monitor] != NULL) {
2142 mutex_unlock(&lm->mtx);
2143 dev_err(tsi148_bridge->parent, "Existing callback attached\n");
2147 /* Attach callback */
2148 bridge->lm_callback[monitor] = callback;
2150 /* Enable Location Monitor interrupt */
2151 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
2152 tmp |= TSI148_LCSR_INTEN_LMEN[monitor];
2153 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
2155 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
2156 tmp |= TSI148_LCSR_INTEO_LMEO[monitor];
2157 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
2159 /* Ensure that global Location Monitor Enable set */
2160 if ((lm_ctl & TSI148_LCSR_LMAT_EN) == 0) {
2161 lm_ctl |= TSI148_LCSR_LMAT_EN;
2162 iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);
2165 mutex_unlock(&lm->mtx);
2171 * Detach a callback function forn a specific location monitor.
2173 static int tsi148_lm_detach(struct vme_lm_resource *lm, int monitor)
2176 struct tsi148_driver *bridge;
2178 bridge = lm->parent->driver_priv;
2180 mutex_lock(&lm->mtx);
2182 /* Disable Location Monitor and ensure previous interrupts are clear */
2183 lm_en = ioread32be(bridge->base + TSI148_LCSR_INTEN);
2184 lm_en &= ~TSI148_LCSR_INTEN_LMEN[monitor];
2185 iowrite32be(lm_en, bridge->base + TSI148_LCSR_INTEN);
2187 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
2188 tmp &= ~TSI148_LCSR_INTEO_LMEO[monitor];
2189 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
2191 iowrite32be(TSI148_LCSR_INTC_LMC[monitor],
2192 bridge->base + TSI148_LCSR_INTC);
2194 /* Detach callback */
2195 bridge->lm_callback[monitor] = NULL;
2197 /* If all location monitors disabled, disable global Location Monitor */
2198 if ((lm_en & (TSI148_LCSR_INTS_LM0S | TSI148_LCSR_INTS_LM1S |
2199 TSI148_LCSR_INTS_LM2S | TSI148_LCSR_INTS_LM3S)) == 0) {
2200 tmp = ioread32be(bridge->base + TSI148_LCSR_LMAT);
2201 tmp &= ~TSI148_LCSR_LMAT_EN;
2202 iowrite32be(tmp, bridge->base + TSI148_LCSR_LMAT);
2205 mutex_unlock(&lm->mtx);
2211 * Determine Geographical Addressing
2213 static int tsi148_slot_get(struct vme_bridge *tsi148_bridge)
2216 struct tsi148_driver *bridge;
2218 bridge = tsi148_bridge->driver_priv;
2221 slot = ioread32be(bridge->base + TSI148_LCSR_VSTAT);
2222 slot = slot & TSI148_LCSR_VSTAT_GA_M;
2229 static void *tsi148_alloc_consistent(struct device *parent, size_t size,
2232 struct pci_dev *pdev;
2234 /* Find pci_dev container of dev */
2235 pdev = to_pci_dev(parent);
2237 return pci_alloc_consistent(pdev, size, dma);
2240 static void tsi148_free_consistent(struct device *parent, size_t size,
2241 void *vaddr, dma_addr_t dma)
2243 struct pci_dev *pdev;
2245 /* Find pci_dev container of dev */
2246 pdev = to_pci_dev(parent);
2248 pci_free_consistent(pdev, size, vaddr, dma);
2252 * Configure CR/CSR space
2254 * Access to the CR/CSR can be configured at power-up. The location of the
2255 * CR/CSR registers in the CR/CSR address space is determined by the boards
2256 * Auto-ID or Geographic address. This function ensures that the window is
2257 * enabled at an offset consistent with the boards geopgraphic address.
2259 * Each board has a 512kB window, with the highest 4kB being used for the
2260 * boards registers, this means there is a fix length 508kB window which must
2261 * be mapped onto PCI memory.
2263 static int tsi148_crcsr_init(struct vme_bridge *tsi148_bridge,
2264 struct pci_dev *pdev)
2266 u32 cbar, crat, vstat;
2267 u32 crcsr_bus_high, crcsr_bus_low;
2269 struct tsi148_driver *bridge;
2271 bridge = tsi148_bridge->driver_priv;
2273 /* Allocate mem for CR/CSR image */
2274 bridge->crcsr_kernel = pci_zalloc_consistent(pdev, VME_CRCSR_BUF_SIZE,
2275 &bridge->crcsr_bus);
2276 if (bridge->crcsr_kernel == NULL) {
2277 dev_err(tsi148_bridge->parent, "Failed to allocate memory for "
2282 reg_split(bridge->crcsr_bus, &crcsr_bus_high, &crcsr_bus_low);
2284 iowrite32be(crcsr_bus_high, bridge->base + TSI148_LCSR_CROU);
2285 iowrite32be(crcsr_bus_low, bridge->base + TSI148_LCSR_CROL);
2287 /* Ensure that the CR/CSR is configured at the correct offset */
2288 cbar = ioread32be(bridge->base + TSI148_CBAR);
2289 cbar = (cbar & TSI148_CRCSR_CBAR_M)>>3;
2291 vstat = tsi148_slot_get(tsi148_bridge);
2293 if (cbar != vstat) {
2295 dev_info(tsi148_bridge->parent, "Setting CR/CSR offset\n");
2296 iowrite32be(cbar<<3, bridge->base + TSI148_CBAR);
2298 dev_info(tsi148_bridge->parent, "CR/CSR Offset: %d\n", cbar);
2300 crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
2301 if (crat & TSI148_LCSR_CRAT_EN)
2302 dev_info(tsi148_bridge->parent, "CR/CSR already enabled\n");
2304 dev_info(tsi148_bridge->parent, "Enabling CR/CSR space\n");
2305 iowrite32be(crat | TSI148_LCSR_CRAT_EN,
2306 bridge->base + TSI148_LCSR_CRAT);
2309 /* If we want flushed, error-checked writes, set up a window
2310 * over the CR/CSR registers. We read from here to safely flush
2311 * through VME writes.
2314 retval = tsi148_master_set(bridge->flush_image, 1,
2315 (vstat * 0x80000), 0x80000, VME_CRCSR, VME_SCT,
2318 dev_err(tsi148_bridge->parent, "Configuring flush image"
2326 static void tsi148_crcsr_exit(struct vme_bridge *tsi148_bridge,
2327 struct pci_dev *pdev)
2330 struct tsi148_driver *bridge;
2332 bridge = tsi148_bridge->driver_priv;
2334 /* Turn off CR/CSR space */
2335 crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
2336 iowrite32be(crat & ~TSI148_LCSR_CRAT_EN,
2337 bridge->base + TSI148_LCSR_CRAT);
2340 iowrite32be(0, bridge->base + TSI148_LCSR_CROU);
2341 iowrite32be(0, bridge->base + TSI148_LCSR_CROL);
2343 pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel,
2347 static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2349 int retval, i, master_num;
2351 struct list_head *pos = NULL, *n;
2352 struct vme_bridge *tsi148_bridge;
2353 struct tsi148_driver *tsi148_device;
2354 struct vme_master_resource *master_image;
2355 struct vme_slave_resource *slave_image;
2356 struct vme_dma_resource *dma_ctrlr;
2357 struct vme_lm_resource *lm;
2359 /* If we want to support more than one of each bridge, we need to
2360 * dynamically generate this so we get one per device
2362 tsi148_bridge = kzalloc(sizeof(struct vme_bridge), GFP_KERNEL);
2363 if (tsi148_bridge == NULL) {
2364 dev_err(&pdev->dev, "Failed to allocate memory for device "
2370 tsi148_device = kzalloc(sizeof(struct tsi148_driver), GFP_KERNEL);
2371 if (tsi148_device == NULL) {
2372 dev_err(&pdev->dev, "Failed to allocate memory for device "
2378 tsi148_bridge->driver_priv = tsi148_device;
2380 /* Enable the device */
2381 retval = pci_enable_device(pdev);
2383 dev_err(&pdev->dev, "Unable to enable device\n");
2388 retval = pci_request_regions(pdev, driver_name);
2390 dev_err(&pdev->dev, "Unable to reserve resources\n");
2394 /* map registers in BAR 0 */
2395 tsi148_device->base = ioremap_nocache(pci_resource_start(pdev, 0),
2397 if (!tsi148_device->base) {
2398 dev_err(&pdev->dev, "Unable to remap CRG region\n");
2403 /* Check to see if the mapping worked out */
2404 data = ioread32(tsi148_device->base + TSI148_PCFS_ID) & 0x0000FFFF;
2405 if (data != PCI_VENDOR_ID_TUNDRA) {
2406 dev_err(&pdev->dev, "CRG region check failed\n");
2411 /* Initialize wait queues & mutual exclusion flags */
2412 init_waitqueue_head(&tsi148_device->dma_queue[0]);
2413 init_waitqueue_head(&tsi148_device->dma_queue[1]);
2414 init_waitqueue_head(&tsi148_device->iack_queue);
2415 mutex_init(&tsi148_device->vme_int);
2416 mutex_init(&tsi148_device->vme_rmw);
2418 tsi148_bridge->parent = &pdev->dev;
2419 strcpy(tsi148_bridge->name, driver_name);
2422 retval = tsi148_irq_init(tsi148_bridge);
2424 dev_err(&pdev->dev, "Chip Initialization failed.\n");
2428 /* If we are going to flush writes, we need to read from the VME bus.
2429 * We need to do this safely, thus we read the devices own CR/CSR
2430 * register. To do this we must set up a window in CR/CSR space and
2431 * hence have one less master window resource available.
2433 master_num = TSI148_MAX_MASTER;
2437 tsi148_device->flush_image =
2438 kmalloc(sizeof(struct vme_master_resource), GFP_KERNEL);
2439 if (tsi148_device->flush_image == NULL) {
2440 dev_err(&pdev->dev, "Failed to allocate memory for "
2441 "flush resource structure\n");
2445 tsi148_device->flush_image->parent = tsi148_bridge;
2446 spin_lock_init(&tsi148_device->flush_image->lock);
2447 tsi148_device->flush_image->locked = 1;
2448 tsi148_device->flush_image->number = master_num;
2449 memset(&tsi148_device->flush_image->bus_resource, 0,
2450 sizeof(struct resource));
2451 tsi148_device->flush_image->kern_base = NULL;
2454 /* Add master windows to list */
2455 INIT_LIST_HEAD(&tsi148_bridge->master_resources);
2456 for (i = 0; i < master_num; i++) {
2457 master_image = kmalloc(sizeof(struct vme_master_resource),
2459 if (master_image == NULL) {
2460 dev_err(&pdev->dev, "Failed to allocate memory for "
2461 "master resource structure\n");
2465 master_image->parent = tsi148_bridge;
2466 spin_lock_init(&master_image->lock);
2467 master_image->locked = 0;
2468 master_image->number = i;
2469 master_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
2470 VME_A64 | VME_CRCSR | VME_USER1 | VME_USER2 |
2471 VME_USER3 | VME_USER4;
2472 master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
2473 VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 |
2474 VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
2475 VME_PROG | VME_DATA;
2476 master_image->width_attr = VME_D16 | VME_D32;
2477 memset(&master_image->bus_resource, 0,
2478 sizeof(struct resource));
2479 master_image->kern_base = NULL;
2480 list_add_tail(&master_image->list,
2481 &tsi148_bridge->master_resources);
2484 /* Add slave windows to list */
2485 INIT_LIST_HEAD(&tsi148_bridge->slave_resources);
2486 for (i = 0; i < TSI148_MAX_SLAVE; i++) {
2487 slave_image = kmalloc(sizeof(struct vme_slave_resource),
2489 if (slave_image == NULL) {
2490 dev_err(&pdev->dev, "Failed to allocate memory for "
2491 "slave resource structure\n");
2495 slave_image->parent = tsi148_bridge;
2496 mutex_init(&slave_image->mtx);
2497 slave_image->locked = 0;
2498 slave_image->number = i;
2499 slave_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
2501 slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
2502 VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 |
2503 VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
2504 VME_PROG | VME_DATA;
2505 list_add_tail(&slave_image->list,
2506 &tsi148_bridge->slave_resources);
2509 /* Add dma engines to list */
2510 INIT_LIST_HEAD(&tsi148_bridge->dma_resources);
2511 for (i = 0; i < TSI148_MAX_DMA; i++) {
2512 dma_ctrlr = kmalloc(sizeof(struct vme_dma_resource),
2514 if (dma_ctrlr == NULL) {
2515 dev_err(&pdev->dev, "Failed to allocate memory for "
2516 "dma resource structure\n");
2520 dma_ctrlr->parent = tsi148_bridge;
2521 mutex_init(&dma_ctrlr->mtx);
2522 dma_ctrlr->locked = 0;
2523 dma_ctrlr->number = i;
2524 dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM |
2525 VME_DMA_MEM_TO_VME | VME_DMA_VME_TO_VME |
2526 VME_DMA_MEM_TO_MEM | VME_DMA_PATTERN_TO_VME |
2527 VME_DMA_PATTERN_TO_MEM;
2528 INIT_LIST_HEAD(&dma_ctrlr->pending);
2529 INIT_LIST_HEAD(&dma_ctrlr->running);
2530 list_add_tail(&dma_ctrlr->list,
2531 &tsi148_bridge->dma_resources);
2534 /* Add location monitor to list */
2535 INIT_LIST_HEAD(&tsi148_bridge->lm_resources);
2536 lm = kmalloc(sizeof(struct vme_lm_resource), GFP_KERNEL);
2538 dev_err(&pdev->dev, "Failed to allocate memory for "
2539 "location monitor resource structure\n");
2543 lm->parent = tsi148_bridge;
2544 mutex_init(&lm->mtx);
2548 list_add_tail(&lm->list, &tsi148_bridge->lm_resources);
2550 tsi148_bridge->slave_get = tsi148_slave_get;
2551 tsi148_bridge->slave_set = tsi148_slave_set;
2552 tsi148_bridge->master_get = tsi148_master_get;
2553 tsi148_bridge->master_set = tsi148_master_set;
2554 tsi148_bridge->master_read = tsi148_master_read;
2555 tsi148_bridge->master_write = tsi148_master_write;
2556 tsi148_bridge->master_rmw = tsi148_master_rmw;
2557 tsi148_bridge->dma_list_add = tsi148_dma_list_add;
2558 tsi148_bridge->dma_list_exec = tsi148_dma_list_exec;
2559 tsi148_bridge->dma_list_empty = tsi148_dma_list_empty;
2560 tsi148_bridge->irq_set = tsi148_irq_set;
2561 tsi148_bridge->irq_generate = tsi148_irq_generate;
2562 tsi148_bridge->lm_set = tsi148_lm_set;
2563 tsi148_bridge->lm_get = tsi148_lm_get;
2564 tsi148_bridge->lm_attach = tsi148_lm_attach;
2565 tsi148_bridge->lm_detach = tsi148_lm_detach;
2566 tsi148_bridge->slot_get = tsi148_slot_get;
2567 tsi148_bridge->alloc_consistent = tsi148_alloc_consistent;
2568 tsi148_bridge->free_consistent = tsi148_free_consistent;
2570 data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT);
2571 dev_info(&pdev->dev, "Board is%s the VME system controller\n",
2572 (data & TSI148_LCSR_VSTAT_SCONS) ? "" : " not");
2574 dev_info(&pdev->dev, "VME geographical address is %d\n",
2575 data & TSI148_LCSR_VSTAT_GA_M);
2577 dev_info(&pdev->dev, "VME geographical address is set to %d\n",
2580 dev_info(&pdev->dev, "VME Write and flush and error check is %s\n",
2581 err_chk ? "enabled" : "disabled");
2583 retval = tsi148_crcsr_init(tsi148_bridge, pdev);
2585 dev_err(&pdev->dev, "CR/CSR configuration failed.\n");
2589 retval = vme_register_bridge(tsi148_bridge);
2591 dev_err(&pdev->dev, "Chip Registration failed.\n");
2595 pci_set_drvdata(pdev, tsi148_bridge);
2597 /* Clear VME bus "board fail", and "power-up reset" lines */
2598 data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT);
2599 data &= ~TSI148_LCSR_VSTAT_BRDFL;
2600 data |= TSI148_LCSR_VSTAT_CPURST;
2601 iowrite32be(data, tsi148_device->base + TSI148_LCSR_VSTAT);
2606 tsi148_crcsr_exit(tsi148_bridge, pdev);
2609 /* resources are stored in link list */
2610 list_for_each_safe(pos, n, &tsi148_bridge->lm_resources) {
2611 lm = list_entry(pos, struct vme_lm_resource, list);
2616 /* resources are stored in link list */
2617 list_for_each_safe(pos, n, &tsi148_bridge->dma_resources) {
2618 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
2623 /* resources are stored in link list */
2624 list_for_each_safe(pos, n, &tsi148_bridge->slave_resources) {
2625 slave_image = list_entry(pos, struct vme_slave_resource, list);
2630 /* resources are stored in link list */
2631 list_for_each_safe(pos, n, &tsi148_bridge->master_resources) {
2632 master_image = list_entry(pos, struct vme_master_resource,
2635 kfree(master_image);
2638 tsi148_irq_exit(tsi148_bridge, pdev);
2641 iounmap(tsi148_device->base);
2643 pci_release_regions(pdev);
2645 pci_disable_device(pdev);
2647 kfree(tsi148_device);
2649 kfree(tsi148_bridge);
2655 static void tsi148_remove(struct pci_dev *pdev)
2657 struct list_head *pos = NULL;
2658 struct list_head *tmplist;
2659 struct vme_master_resource *master_image;
2660 struct vme_slave_resource *slave_image;
2661 struct vme_dma_resource *dma_ctrlr;
2663 struct tsi148_driver *bridge;
2664 struct vme_bridge *tsi148_bridge = pci_get_drvdata(pdev);
2666 bridge = tsi148_bridge->driver_priv;
2669 dev_dbg(&pdev->dev, "Driver is being unloaded.\n");
2672 * Shutdown all inbound and outbound windows.
2674 for (i = 0; i < 8; i++) {
2675 iowrite32be(0, bridge->base + TSI148_LCSR_IT[i] +
2676 TSI148_LCSR_OFFSET_ITAT);
2677 iowrite32be(0, bridge->base + TSI148_LCSR_OT[i] +
2678 TSI148_LCSR_OFFSET_OTAT);
2682 * Shutdown Location monitor.
2684 iowrite32be(0, bridge->base + TSI148_LCSR_LMAT);
2689 iowrite32be(0, bridge->base + TSI148_LCSR_CSRAT);
2692 * Clear error status.
2694 iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_EDPAT);
2695 iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_VEAT);
2696 iowrite32be(0x07000700, bridge->base + TSI148_LCSR_PSTAT);
2699 * Remove VIRQ interrupt (if any)
2701 if (ioread32be(bridge->base + TSI148_LCSR_VICR) & 0x800)
2702 iowrite32be(0x8000, bridge->base + TSI148_LCSR_VICR);
2705 * Map all Interrupts to PCI INTA
2707 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM1);
2708 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM2);
2710 tsi148_irq_exit(tsi148_bridge, pdev);
2712 vme_unregister_bridge(tsi148_bridge);
2714 tsi148_crcsr_exit(tsi148_bridge, pdev);
2716 /* resources are stored in link list */
2717 list_for_each_safe(pos, tmplist, &tsi148_bridge->dma_resources) {
2718 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
2723 /* resources are stored in link list */
2724 list_for_each_safe(pos, tmplist, &tsi148_bridge->slave_resources) {
2725 slave_image = list_entry(pos, struct vme_slave_resource, list);
2730 /* resources are stored in link list */
2731 list_for_each_safe(pos, tmplist, &tsi148_bridge->master_resources) {
2732 master_image = list_entry(pos, struct vme_master_resource,
2735 kfree(master_image);
2738 iounmap(bridge->base);
2740 pci_release_regions(pdev);
2742 pci_disable_device(pdev);
2744 kfree(tsi148_bridge->driver_priv);
2746 kfree(tsi148_bridge);
2749 module_pci_driver(tsi148_driver);
2751 MODULE_PARM_DESC(err_chk, "Check for VME errors on reads and writes");
2752 module_param(err_chk, bool, 0);
2754 MODULE_PARM_DESC(geoid, "Override geographical addressing");
2755 module_param(geoid, int, 0);
2757 MODULE_DESCRIPTION("VME driver for the Tundra Tempe VME bridge");
2758 MODULE_LICENSE("GPL");