drivers/w1/masters/ds1wm.c

   1 /*
   2  * 1-wire busmaster driver for DS1WM and ASICs with embedded DS1WMs
   3  * such as HP iPAQs (including h5xxx, h2200, and devices with ASIC3
   4  * like hx4700).
   5  *
   6  * Copyright (c) 2004-2005, Szabolcs Gyurko <szabolcs.gyurko@tlt.hu>
   7  * Copyright (c) 2004-2007, Matt Reimer <mreimer@vpop.net>
   8  *
   9  * Use consistent with the GNU GPL is permitted,
  10  * provided that this copyright notice is
  11  * preserved in its entirety in all copies and derived works.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/pm.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/clk.h>
  20 #include <linux/err.h>
  21 #include <linux/delay.h>
  22 #include <linux/mfd/core.h>
  23 #include <linux/mfd/ds1wm.h>
  24
  25 #include <asm/io.h>
  26
  27 #include "../w1.h"
  28 #include "../w1_int.h"
  29
  30
  31 #define DS1WM_CMD       0x00    /* R/W 4 bits command */
  32 #define DS1WM_DATA      0x01    /* R/W 8 bits, transmit/receive buffer */
  33 #define DS1WM_INT       0x02    /* R/W interrupt status */
  34 #define DS1WM_INT_EN    0x03    /* R/W interrupt enable */
  35 #define DS1WM_CLKDIV    0x04    /* R/W 5 bits of divisor and pre-scale */
  36
  37 #define DS1WM_CMD_1W_RESET  (1 << 0)    /* force reset on 1-wire bus */
  38 #define DS1WM_CMD_SRA       (1 << 1)    /* enable Search ROM accelerator mode */
  39 #define DS1WM_CMD_DQ_OUTPUT (1 << 2)    /* write only - forces bus low */
  40 #define DS1WM_CMD_DQ_INPUT  (1 << 3)    /* read only - reflects state of bus */
  41 #define DS1WM_CMD_RST       (1 << 5)    /* software reset */
  42 #define DS1WM_CMD_OD        (1 << 7)    /* overdrive */
  43
  44 #define DS1WM_INT_PD        (1 << 0)    /* presence detect */
  45 #define DS1WM_INT_PDR       (1 << 1)    /* presence detect result */
  46 #define DS1WM_INT_TBE       (1 << 2)    /* tx buffer empty */
  47 #define DS1WM_INT_TSRE      (1 << 3)    /* tx shift register empty */
  48 #define DS1WM_INT_RBF       (1 << 4)    /* rx buffer full */
  49 #define DS1WM_INT_RSRF      (1 << 5)    /* rx shift register full */
  50
  51 #define DS1WM_INTEN_EPD     (1 << 0)    /* enable presence detect int */
  52 #define DS1WM_INTEN_IAS     (1 << 1)    /* INTR active state */
  53 #define DS1WM_INTEN_ETBE    (1 << 2)    /* enable tx buffer empty int */
  54 #define DS1WM_INTEN_ETMT    (1 << 3)    /* enable tx shift register empty int */
  55 #define DS1WM_INTEN_ERBF    (1 << 4)    /* enable rx buffer full int */
  56 #define DS1WM_INTEN_ERSRF   (1 << 5)    /* enable rx shift register full int */
  57 #define DS1WM_INTEN_DQO     (1 << 6)    /* enable direct bus driving ops */
  58
  59
  60 #define DS1WM_TIMEOUT (HZ * 5)
  61
  62 static struct {
  63         unsigned long freq;
  64         unsigned long divisor;
  65 } freq[] = {
  66         { 4000000, 0x8 },
  67         { 5000000, 0x2 },
  68         { 6000000, 0x5 },
  69         { 7000000, 0x3 },
  70         { 8000000, 0xc },
  71         { 10000000, 0x6 },
  72         { 12000000, 0x9 },
  73         { 14000000, 0x7 },
  74         { 16000000, 0x10 },
  75         { 20000000, 0xa },
  76         { 24000000, 0xd },
  77         { 28000000, 0xb },
  78         { 32000000, 0x14 },
  79         { 40000000, 0xe },
  80         { 48000000, 0x11 },
  81         { 56000000, 0xf },
  82         { 64000000, 0x18 },
  83         { 80000000, 0x12 },
  84         { 96000000, 0x15 },
  85         { 112000000, 0x13 },
  86         { 128000000, 0x1c },
  87 };
  88
  89 struct ds1wm_data {
  90         void            __iomem *map;
  91         int             bus_shift; /* # of shifts to calc register offsets */
  92         struct platform_device *pdev;
  93         struct mfd_cell *cell;
  94         int             irq;
  95         int             active_high;
  96         struct clk      *clk;
  97         int             slave_present;
  98         void            *reset_complete;
  99         void            *read_complete;
 100         void            *write_complete;
 101         u8              read_byte; /* last byte received */
 102 };
 103
 104 static inline void ds1wm_write_register(struct ds1wm_data *ds1wm_data, u32 reg,
 105                                         u8 val)
 106 {
 107         __raw_writeb(val, ds1wm_data->map + (reg << ds1wm_data->bus_shift));
 108 }
 109
 110 static inline u8 ds1wm_read_register(struct ds1wm_data *ds1wm_data, u32 reg)
 111 {
 112         return __raw_readb(ds1wm_data->map + (reg << ds1wm_data->bus_shift));
 113 }
 114
 115
 116 static irqreturn_t ds1wm_isr(int isr, void *data)
 117 {
 118         struct ds1wm_data *ds1wm_data = data;
 119         u8 intr = ds1wm_read_register(ds1wm_data, DS1WM_INT);
 120
 121         ds1wm_data->slave_present = (intr & DS1WM_INT_PDR) ? 0 : 1;
 122
 123         if ((intr & DS1WM_INT_PD) && ds1wm_data->reset_complete)
 124                 complete(ds1wm_data->reset_complete);
 125
 126         if ((intr & DS1WM_INT_TSRE) && ds1wm_data->write_complete)
 127                 complete(ds1wm_data->write_complete);
 128
 129         if (intr & DS1WM_INT_RBF) {
 130                 ds1wm_data->read_byte = ds1wm_read_register(ds1wm_data,
 131                                                             DS1WM_DATA);
 132                 if (ds1wm_data->read_complete)
 133                         complete(ds1wm_data->read_complete);
 134         }
 135
 136         return IRQ_HANDLED;
 137 }
 138
 139 static int ds1wm_reset(struct ds1wm_data *ds1wm_data)
 140 {
 141         unsigned long timeleft;
 142         DECLARE_COMPLETION_ONSTACK(reset_done);
 143
 144         ds1wm_data->reset_complete = &reset_done;
 145
 146         ds1wm_write_register(ds1wm_data, DS1WM_INT_EN, DS1WM_INTEN_EPD |
 147                 (ds1wm_data->active_high ? DS1WM_INTEN_IAS : 0));
 148
 149         ds1wm_write_register(ds1wm_data, DS1WM_CMD, DS1WM_CMD_1W_RESET);
 150
 151         timeleft = wait_for_completion_timeout(&reset_done, DS1WM_TIMEOUT);
 152         ds1wm_data->reset_complete = NULL;
 153         if (!timeleft) {
 154                 dev_err(&ds1wm_data->pdev->dev, "reset failed\n");
 155                 return 1;
 156         }
 157
 158         /* Wait for the end of the reset. According to the specs, the time
 159          * from when the interrupt is asserted to the end of the reset is:
 160          *     tRSTH  - tPDH  - tPDL - tPDI
 161          *     625 us - 60 us - 240 us - 100 ns = 324.9 us
 162          *
 163          * We'll wait a bit longer just to be sure.
 164          * Was udelay(500), but if it is going to busywait the cpu that long,
 165          * might as well come back later.
 166          */
 167         msleep(1);
 168
 169         ds1wm_write_register(ds1wm_data, DS1WM_INT_EN,
 170                 DS1WM_INTEN_ERBF | DS1WM_INTEN_ETMT | DS1WM_INTEN_EPD |
 171                 (ds1wm_data->active_high ? DS1WM_INTEN_IAS : 0));
 172
 173         if (!ds1wm_data->slave_present) {
 174                 dev_dbg(&ds1wm_data->pdev->dev, "reset: no devices found\n");
 175                 return 1;
 176         }
 177
 178         return 0;
 179 }
 180
 181 static int ds1wm_write(struct ds1wm_data *ds1wm_data, u8 data)
 182 {
 183         DECLARE_COMPLETION_ONSTACK(write_done);
 184         ds1wm_data->write_complete = &write_done;
 185
 186         ds1wm_write_register(ds1wm_data, DS1WM_DATA, data);
 187
 188         wait_for_completion_timeout(&write_done, DS1WM_TIMEOUT);
 189         ds1wm_data->write_complete = NULL;
 190
 191         return 0;
 192 }
 193
 194 static int ds1wm_read(struct ds1wm_data *ds1wm_data, unsigned char write_data)
 195 {
 196         DECLARE_COMPLETION_ONSTACK(read_done);
 197         ds1wm_data->read_complete = &read_done;
 198
 199         ds1wm_write(ds1wm_data, write_data);
 200         wait_for_completion_timeout(&read_done, DS1WM_TIMEOUT);
 201         ds1wm_data->read_complete = NULL;
 202
 203         return ds1wm_data->read_byte;
 204 }
 205
 206 static int ds1wm_find_divisor(int gclk)
 207 {
 208         int i;
 209
 210         for (i = 0; i < ARRAY_SIZE(freq); i++)
 211                 if (gclk <= freq[i].freq)
 212                         return freq[i].divisor;
 213
 214         return 0;
 215 }
 216
 217 static void ds1wm_up(struct ds1wm_data *ds1wm_data)
 218 {
 219         int gclk, divisor;
 220
 221         if (ds1wm_data->cell->enable)
 222                 ds1wm_data->cell->enable(ds1wm_data->pdev);
 223
 224         gclk = clk_get_rate(ds1wm_data->clk);
 225         clk_enable(ds1wm_data->clk);
 226         divisor = ds1wm_find_divisor(gclk);
 227         if (divisor == 0) {
 228                 dev_err(&ds1wm_data->pdev->dev,
 229                         "no suitable divisor for %dHz clock\n", gclk);
 230                 return;
 231         }
 232         ds1wm_write_register(ds1wm_data, DS1WM_CLKDIV, divisor);
 233
 234         /* Let the w1 clock stabilize. */
 235         msleep(1);
 236
 237         ds1wm_reset(ds1wm_data);
 238 }
 239
 240 static void ds1wm_down(struct ds1wm_data *ds1wm_data)
 241 {
 242         ds1wm_reset(ds1wm_data);
 243
 244         /* Disable interrupts. */
 245         ds1wm_write_register(ds1wm_data, DS1WM_INT_EN,
 246                              ds1wm_data->active_high ? DS1WM_INTEN_IAS : 0);
 247
 248         if (ds1wm_data->cell->disable)
 249                 ds1wm_data->cell->disable(ds1wm_data->pdev);
 250
 251         clk_disable(ds1wm_data->clk);
 252 }
 253
 254 /* --------------------------------------------------------------------- */
 255 /* w1 methods */
 256
 257 static u8 ds1wm_read_byte(void *data)
 258 {
 259         struct ds1wm_data *ds1wm_data = data;
 260
 261         return ds1wm_read(ds1wm_data, 0xff);
 262 }
 263
 264 static void ds1wm_write_byte(void *data, u8 byte)
 265 {
 266         struct ds1wm_data *ds1wm_data = data;
 267
 268         ds1wm_write(ds1wm_data, byte);
 269 }
 270
 271 static u8 ds1wm_reset_bus(void *data)
 272 {
 273         struct ds1wm_data *ds1wm_data = data;
 274
 275         ds1wm_reset(ds1wm_data);
 276
 277         return 0;
 278 }
 279
 280 static void ds1wm_search(void *data, struct w1_master *master_dev,
 281                         u8 search_type, w1_slave_found_callback slave_found)
 282 {
 283         struct ds1wm_data *ds1wm_data = data;
 284         int i;
 285         unsigned long long rom_id;
 286
 287         /* XXX We need to iterate for multiple devices per the DS1WM docs.
 288          * See http://www.maxim-ic.com/appnotes.cfm/appnote_number/120. */
 289         if (ds1wm_reset(ds1wm_data))
 290                 return;
 291
 292         ds1wm_write(ds1wm_data, search_type);
 293         ds1wm_write_register(ds1wm_data, DS1WM_CMD, DS1WM_CMD_SRA);
 294
 295         for (rom_id = 0, i = 0; i < 16; i++) {
 296
 297                 unsigned char resp, r, d;
 298
 299                 resp = ds1wm_read(ds1wm_data, 0x00);
 300
 301                 r = ((resp & 0x02) >> 1) |
 302                     ((resp & 0x08) >> 2) |
 303                     ((resp & 0x20) >> 3) |
 304                     ((resp & 0x80) >> 4);
 305
 306                 d = ((resp & 0x01) >> 0) |
 307                     ((resp & 0x04) >> 1) |
 308                     ((resp & 0x10) >> 2) |
 309                     ((resp & 0x40) >> 3);
 310
 311                 rom_id |= (unsigned long long) r << (i * 4);
 312
 313         }
 314         dev_dbg(&ds1wm_data->pdev->dev, "found 0x%08llX\n", rom_id);
 315
 316         ds1wm_write_register(ds1wm_data, DS1WM_CMD, ~DS1WM_CMD_SRA);
 317         ds1wm_reset(ds1wm_data);
 318
 319         slave_found(master_dev, rom_id);
 320 }
 321
 322 /* --------------------------------------------------------------------- */
 323
 324 static struct w1_bus_master ds1wm_master = {
 325         .read_byte  = ds1wm_read_byte,
 326         .write_byte = ds1wm_write_byte,
 327         .reset_bus  = ds1wm_reset_bus,
 328         .search     = ds1wm_search,
 329 };
 330
 331 static int ds1wm_probe(struct platform_device *pdev)
 332 {
 333         struct ds1wm_data *ds1wm_data;
 334         struct ds1wm_driver_data *plat;
 335         struct resource *res;
 336         struct mfd_cell *cell;
 337         int ret;
 338
 339         if (!pdev)
 340                 return -ENODEV;
 341
 342         cell = pdev->dev.platform_data;
 343         if (!cell)
 344                 return -ENODEV;
 345
 346         ds1wm_data = kzalloc(sizeof(*ds1wm_data), GFP_KERNEL);
 347         if (!ds1wm_data)
 348                 return -ENOMEM;
 349
 350         platform_set_drvdata(pdev, ds1wm_data);
 351
 352         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 353         if (!res) {
 354                 ret = -ENXIO;
 355                 goto err0;
 356         }
 357         ds1wm_data->map = ioremap(res->start, resource_size(res));
 358         if (!ds1wm_data->map) {
 359                 ret = -ENOMEM;
 360                 goto err0;
 361         }
 362         plat = cell->driver_data;
 363
 364         /* calculate bus shift from mem resource */
 365         ds1wm_data->bus_shift = resource_size(res) >> 3;
 366
 367         ds1wm_data->pdev = pdev;
 368         ds1wm_data->cell = cell;
 369
 370         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 371         if (!res) {
 372                 ret = -ENXIO;
 373                 goto err1;
 374         }
 375         ds1wm_data->irq = res->start;
 376         ds1wm_data->active_high = plat->active_high;
 377
 378         if (res->flags & IORESOURCE_IRQ_HIGHEDGE)
 379                 set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_RISING);
 380         if (res->flags & IORESOURCE_IRQ_LOWEDGE)
 381                 set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_FALLING);
 382
 383         ret = request_irq(ds1wm_data->irq, ds1wm_isr, IRQF_DISABLED,
 384                           "ds1wm", ds1wm_data);
 385         if (ret)
 386                 goto err1;
 387
 388         ds1wm_data->clk = clk_get(&pdev->dev, "ds1wm");
 389         if (IS_ERR(ds1wm_data->clk)) {
 390                 ret = PTR_ERR(ds1wm_data->clk);
 391                 goto err2;
 392         }
 393
 394         ds1wm_up(ds1wm_data);
 395
 396         ds1wm_master.data = (void *)ds1wm_data;
 397
 398         ret = w1_add_master_device(&ds1wm_master);
 399         if (ret)
 400                 goto err3;
 401
 402         return 0;
 403
 404 err3:
 405         ds1wm_down(ds1wm_data);
 406         clk_put(ds1wm_data->clk);
 407 err2:
 408         free_irq(ds1wm_data->irq, ds1wm_data);
 409 err1:
 410         iounmap(ds1wm_data->map);
 411 err0:
 412         kfree(ds1wm_data);
 413
 414         return ret;
 415 }
 416
 417 #ifdef CONFIG_PM
 418 static int ds1wm_suspend(struct platform_device *pdev, pm_message_t state)
 419 {
 420         struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev);
 421
 422         ds1wm_down(ds1wm_data);
 423
 424         return 0;
 425 }
 426
 427 static int ds1wm_resume(struct platform_device *pdev)
 428 {
 429         struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev);
 430
 431         ds1wm_up(ds1wm_data);
 432
 433         return 0;
 434 }
 435 #else
 436 #define ds1wm_suspend NULL
 437 #define ds1wm_resume NULL
 438 #endif
 439
 440 static int ds1wm_remove(struct platform_device *pdev)
 441 {
 442         struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev);
 443
 444         w1_remove_master_device(&ds1wm_master);
 445         ds1wm_down(ds1wm_data);
 446         clk_put(ds1wm_data->clk);
 447         free_irq(ds1wm_data->irq, ds1wm_data);
 448         iounmap(ds1wm_data->map);
 449         kfree(ds1wm_data);
 450
 451         return 0;
 452 }
 453
 454 static struct platform_driver ds1wm_driver = {
 455         .driver   = {
 456                 .name = "ds1wm",
 457         },
 458         .probe    = ds1wm_probe,
 459         .remove   = ds1wm_remove,
 460         .suspend  = ds1wm_suspend,
 461         .resume   = ds1wm_resume
 462 };
 463
 464 static int __init ds1wm_init(void)
 465 {
 466         printk("DS1WM w1 busmaster driver - (c) 2004 Szabolcs Gyurko\n");
 467         return platform_driver_register(&ds1wm_driver);
 468 }
 469
 470 static void __exit ds1wm_exit(void)
 471 {
 472         platform_driver_unregister(&ds1wm_driver);
 473 }
 474
 475 module_init(ds1wm_init);
 476 module_exit(ds1wm_exit);
 477
 478 MODULE_LICENSE("GPL");
 479 MODULE_AUTHOR("Szabolcs Gyurko <szabolcs.gyurko@tlt.hu>, "
 480               "Matt Reimer <mreimer@vpop.net>");
 481 MODULE_DESCRIPTION("DS1WM w1 busmaster driver");