drivers/watchdog/s3c2410_wdt.c

   1 /* linux/drivers/char/watchdog/s3c2410_wdt.c
   2  *
   3  * Copyright (c) 2004 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C2410 Watchdog Timer Support
   7  *
   8  * Based on, softdog.c by Alan Cox,
   9  *     (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  24 */
  25
  26 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  27
  28 #include <linux/module.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/types.h>
  31 #include <linux/timer.h>
  32 #include <linux/watchdog.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/clk.h>
  36 #include <linux/uaccess.h>
  37 #include <linux/io.h>
  38 #include <linux/cpufreq.h>
  39 #include <linux/slab.h>
  40 #include <linux/err.h>
  41 #include <linux/of.h>
  42 #include <linux/mfd/syscon.h>
  43 #include <linux/regmap.h>
  44
  45 #define S3C2410_WTCON           0x00
  46 #define S3C2410_WTDAT           0x04
  47 #define S3C2410_WTCNT           0x08
  48
  49 #define S3C2410_WTCON_RSTEN     (1 << 0)
  50 #define S3C2410_WTCON_INTEN     (1 << 2)
  51 #define S3C2410_WTCON_ENABLE    (1 << 5)
  52
  53 #define S3C2410_WTCON_DIV16     (0 << 3)
  54 #define S3C2410_WTCON_DIV32     (1 << 3)
  55 #define S3C2410_WTCON_DIV64     (2 << 3)
  56 #define S3C2410_WTCON_DIV128    (3 << 3)
  57
  58 #define S3C2410_WTCON_PRESCALE(x)       ((x) << 8)
  59 #define S3C2410_WTCON_PRESCALE_MASK     (0xff << 8)
  60
  61 #define CONFIG_S3C2410_WATCHDOG_ATBOOT          (0)
  62 #define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME    (15)
  63
  64 #define EXYNOS5_RST_STAT_REG_OFFSET             0x0404
  65 #define EXYNOS5_WDT_DISABLE_REG_OFFSET          0x0408
  66 #define EXYNOS5_WDT_MASK_RESET_REG_OFFSET       0x040c
  67 #define QUIRK_HAS_PMU_CONFIG                    (1 << 0)
  68 #define QUIRK_HAS_RST_STAT                      (1 << 1)
  69
  70 /* These quirks require that we have a PMU register map */
  71 #define QUIRKS_HAVE_PMUREG                      (QUIRK_HAS_PMU_CONFIG | \
  72                                                  QUIRK_HAS_RST_STAT)
  73
  74 static bool nowayout    = WATCHDOG_NOWAYOUT;
  75 static int tmr_margin;
  76 static int tmr_atboot   = CONFIG_S3C2410_WATCHDOG_ATBOOT;
  77 static int soft_noboot;
  78 static int debug;
  79
  80 module_param(tmr_margin,  int, 0);
  81 module_param(tmr_atboot,  int, 0);
  82 module_param(nowayout,   bool, 0);
  83 module_param(soft_noboot, int, 0);
  84 module_param(debug,       int, 0);
  85
  86 MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default="
  87                 __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME) ")");
  88 MODULE_PARM_DESC(tmr_atboot,
  89                 "Watchdog is started at boot time if set to 1, default="
  90                         __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_ATBOOT));
  91 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  92                         __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  93 MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, "
  94                         "0 to reboot (default 0)");
  95 MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug (default 0)");
  96
  97 /**
  98  * struct s3c2410_wdt_variant - Per-variant config data
  99  *
 100  * @disable_reg: Offset in pmureg for the register that disables the watchdog
 101  * timer reset functionality.
 102  * @mask_reset_reg: Offset in pmureg for the register that masks the watchdog
 103  * timer reset functionality.
 104  * @mask_bit: Bit number for the watchdog timer in the disable register and the
 105  * mask reset register.
 106  * @rst_stat_reg: Offset in pmureg for the register that has the reset status.
 107  * @rst_stat_bit: Bit number in the rst_stat register indicating a watchdog
 108  * reset.
 109  * @quirks: A bitfield of quirks.
 110  */
 111
 112 struct s3c2410_wdt_variant {
 113         int disable_reg;
 114         int mask_reset_reg;
 115         int mask_bit;
 116         int rst_stat_reg;
 117         int rst_stat_bit;
 118         u32 quirks;
 119 };
 120
 121 struct s3c2410_wdt {
 122         struct device           *dev;
 123         struct clk              *clock;
 124         void __iomem            *reg_base;
 125         unsigned int            count;
 126         spinlock_t              lock;
 127         unsigned long           wtcon_save;
 128         unsigned long           wtdat_save;
 129         struct watchdog_device  wdt_device;
 130         struct notifier_block   freq_transition;
 131         struct s3c2410_wdt_variant *drv_data;
 132         struct regmap *pmureg;
 133 };
 134
 135 static const struct s3c2410_wdt_variant drv_data_s3c2410 = {
 136         .quirks = 0
 137 };
 138
 139 #ifdef CONFIG_OF
 140 static const struct s3c2410_wdt_variant drv_data_exynos5250  = {
 141         .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
 142         .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
 143         .mask_bit = 20,
 144         .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
 145         .rst_stat_bit = 20,
 146         .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT,
 147 };
 148
 149 static const struct s3c2410_wdt_variant drv_data_exynos5420 = {
 150         .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
 151         .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
 152         .mask_bit = 0,
 153         .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
 154         .rst_stat_bit = 9,
 155         .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT,
 156 };
 157
 158 static const struct s3c2410_wdt_variant drv_data_exynos7 = {
 159         .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
 160         .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
 161         .mask_bit = 0,
 162         .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
 163         .rst_stat_bit = 23,     /* A57 WDTRESET */
 164         .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT,
 165 };
 166
 167 static const struct of_device_id s3c2410_wdt_match[] = {
 168         { .compatible = "samsung,s3c2410-wdt",
 169           .data = &drv_data_s3c2410 },
 170         { .compatible = "samsung,exynos5250-wdt",
 171           .data = &drv_data_exynos5250 },
 172         { .compatible = "samsung,exynos5420-wdt",
 173           .data = &drv_data_exynos5420 },
 174         { .compatible = "samsung,exynos7-wdt",
 175           .data = &drv_data_exynos7 },
 176         {},
 177 };
 178 MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
 179 #endif
 180
 181 static const struct platform_device_id s3c2410_wdt_ids[] = {
 182         {
 183                 .name = "s3c2410-wdt",
 184                 .driver_data = (unsigned long)&drv_data_s3c2410,
 185         },
 186         {}
 187 };
 188 MODULE_DEVICE_TABLE(platform, s3c2410_wdt_ids);
 189
 190 /* watchdog control routines */
 191
 192 #define DBG(fmt, ...)                                   \
 193 do {                                                    \
 194         if (debug)                                      \
 195                 pr_info(fmt, ##__VA_ARGS__);            \
 196 } while (0)
 197
 198 /* functions */
 199
 200 static inline struct s3c2410_wdt *freq_to_wdt(struct notifier_block *nb)
 201 {
 202         return container_of(nb, struct s3c2410_wdt, freq_transition);
 203 }
 204
 205 static int s3c2410wdt_mask_and_disable_reset(struct s3c2410_wdt *wdt, bool mask)
 206 {
 207         int ret;
 208         u32 mask_val = 1 << wdt->drv_data->mask_bit;
 209         u32 val = 0;
 210
 211         /* No need to do anything if no PMU CONFIG needed */
 212         if (!(wdt->drv_data->quirks & QUIRK_HAS_PMU_CONFIG))
 213                 return 0;
 214
 215         if (mask)
 216                 val = mask_val;
 217
 218         ret = regmap_update_bits(wdt->pmureg,
 219                         wdt->drv_data->disable_reg,
 220                         mask_val, val);
 221         if (ret < 0)
 222                 goto error;
 223
 224         ret = regmap_update_bits(wdt->pmureg,
 225                         wdt->drv_data->mask_reset_reg,
 226                         mask_val, val);
 227  error:
 228         if (ret < 0)
 229                 dev_err(wdt->dev, "failed to update reg(%d)\n", ret);
 230
 231         return ret;
 232 }
 233
 234 static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
 235 {
 236         struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
 237
 238         spin_lock(&wdt->lock);
 239         writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
 240         spin_unlock(&wdt->lock);
 241
 242         return 0;
 243 }
 244
 245 static void __s3c2410wdt_stop(struct s3c2410_wdt *wdt)
 246 {
 247         unsigned long wtcon;
 248
 249         wtcon = readl(wdt->reg_base + S3C2410_WTCON);
 250         wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN);
 251         writel(wtcon, wdt->reg_base + S3C2410_WTCON);
 252 }
 253
 254 static int s3c2410wdt_stop(struct watchdog_device *wdd)
 255 {
 256         struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
 257
 258         spin_lock(&wdt->lock);
 259         __s3c2410wdt_stop(wdt);
 260         spin_unlock(&wdt->lock);
 261
 262         return 0;
 263 }
 264
 265 static int s3c2410wdt_start(struct watchdog_device *wdd)
 266 {
 267         unsigned long wtcon;
 268         struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
 269
 270         spin_lock(&wdt->lock);
 271
 272         __s3c2410wdt_stop(wdt);
 273
 274         wtcon = readl(wdt->reg_base + S3C2410_WTCON);
 275         wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128;
 276
 277         if (soft_noboot) {
 278                 wtcon |= S3C2410_WTCON_INTEN;
 279                 wtcon &= ~S3C2410_WTCON_RSTEN;
 280         } else {
 281                 wtcon &= ~S3C2410_WTCON_INTEN;
 282                 wtcon |= S3C2410_WTCON_RSTEN;
 283         }
 284
 285         DBG("%s: count=0x%08x, wtcon=%08lx\n",
 286             __func__, wdt->count, wtcon);
 287
 288         writel(wdt->count, wdt->reg_base + S3C2410_WTDAT);
 289         writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
 290         writel(wtcon, wdt->reg_base + S3C2410_WTCON);
 291         spin_unlock(&wdt->lock);
 292
 293         return 0;
 294 }
 295
 296 static inline int s3c2410wdt_is_running(struct s3c2410_wdt *wdt)
 297 {
 298         return readl(wdt->reg_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE;
 299 }
 300
 301 static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd, unsigned timeout)
 302 {
 303         struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
 304         unsigned long freq = clk_get_rate(wdt->clock);
 305         unsigned int count;
 306         unsigned int divisor = 1;
 307         unsigned long wtcon;
 308
 309         if (timeout < 1)
 310                 return -EINVAL;
 311
 312         freq = DIV_ROUND_UP(freq, 128);
 313         count = timeout * freq;
 314
 315         DBG("%s: count=%d, timeout=%d, freq=%lu\n",
 316             __func__, count, timeout, freq);
 317
 318         /* if the count is bigger than the watchdog register,
 319            then work out what we need to do (and if) we can
 320            actually make this value
 321         */
 322
 323         if (count >= 0x10000) {
 324                 divisor = DIV_ROUND_UP(count, 0xffff);
 325
 326                 if (divisor > 0x100) {
 327                         dev_err(wdt->dev, "timeout %d too big\n", timeout);
 328                         return -EINVAL;
 329                 }
 330         }
 331
 332         DBG("%s: timeout=%d, divisor=%d, count=%d (%08x)\n",
 333             __func__, timeout, divisor, count, DIV_ROUND_UP(count, divisor));
 334
 335         count = DIV_ROUND_UP(count, divisor);
 336         wdt->count = count;
 337
 338         /* update the pre-scaler */
 339         wtcon = readl(wdt->reg_base + S3C2410_WTCON);
 340         wtcon &= ~S3C2410_WTCON_PRESCALE_MASK;
 341         wtcon |= S3C2410_WTCON_PRESCALE(divisor-1);
 342
 343         writel(count, wdt->reg_base + S3C2410_WTDAT);
 344         writel(wtcon, wdt->reg_base + S3C2410_WTCON);
 345
 346         wdd->timeout = (count * divisor) / freq;
 347
 348         return 0;
 349 }
 350
 351 #define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
 352
 353 static const struct watchdog_info s3c2410_wdt_ident = {
 354         .options          =     OPTIONS,
 355         .firmware_version =     0,
 356         .identity         =     "S3C2410 Watchdog",
 357 };
 358
 359 static struct watchdog_ops s3c2410wdt_ops = {
 360         .owner = THIS_MODULE,
 361         .start = s3c2410wdt_start,
 362         .stop = s3c2410wdt_stop,
 363         .ping = s3c2410wdt_keepalive,
 364         .set_timeout = s3c2410wdt_set_heartbeat,
 365 };
 366
 367 static struct watchdog_device s3c2410_wdd = {
 368         .info = &s3c2410_wdt_ident,
 369         .ops = &s3c2410wdt_ops,
 370         .timeout = CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME,
 371 };
 372
 373 /* interrupt handler code */
 374
 375 static irqreturn_t s3c2410wdt_irq(int irqno, void *param)
 376 {
 377         struct s3c2410_wdt *wdt = platform_get_drvdata(param);
 378
 379         dev_info(wdt->dev, "watchdog timer expired (irq)\n");
 380
 381         s3c2410wdt_keepalive(&wdt->wdt_device);
 382         return IRQ_HANDLED;
 383 }
 384
 385 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
 386
 387 static int s3c2410wdt_cpufreq_transition(struct notifier_block *nb,
 388                                           unsigned long val, void *data)
 389 {
 390         int ret;
 391         struct s3c2410_wdt *wdt = freq_to_wdt(nb);
 392
 393         if (!s3c2410wdt_is_running(wdt))
 394                 goto done;
 395
 396         if (val == CPUFREQ_PRECHANGE) {
 397                 /* To ensure that over the change we don't cause the
 398                  * watchdog to trigger, we perform an keep-alive if
 399                  * the watchdog is running.
 400                  */
 401
 402                 s3c2410wdt_keepalive(&wdt->wdt_device);
 403         } else if (val == CPUFREQ_POSTCHANGE) {
 404                 s3c2410wdt_stop(&wdt->wdt_device);
 405
 406                 ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
 407                                                 wdt->wdt_device.timeout);
 408
 409                 if (ret >= 0)
 410                         s3c2410wdt_start(&wdt->wdt_device);
 411                 else
 412                         goto err;
 413         }
 414
 415 done:
 416         return 0;
 417
 418  err:
 419         dev_err(wdt->dev, "cannot set new value for timeout %d\n",
 420                                 wdt->wdt_device.timeout);
 421         return ret;
 422 }
 423
 424 static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt)
 425 {
 426         wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition;
 427
 428         return cpufreq_register_notifier(&wdt->freq_transition,
 429                                          CPUFREQ_TRANSITION_NOTIFIER);
 430 }
 431
 432 static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt)
 433 {
 434         wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition;
 435
 436         cpufreq_unregister_notifier(&wdt->freq_transition,
 437                                     CPUFREQ_TRANSITION_NOTIFIER);
 438 }
 439
 440 #else
 441
 442 static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt)
 443 {
 444         return 0;
 445 }
 446
 447 static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt)
 448 {
 449 }
 450 #endif
 451
 452 static inline unsigned int s3c2410wdt_get_bootstatus(struct s3c2410_wdt *wdt)
 453 {
 454         unsigned int rst_stat;
 455         int ret;
 456
 457         if (!(wdt->drv_data->quirks & QUIRK_HAS_RST_STAT))
 458                 return 0;
 459
 460         ret = regmap_read(wdt->pmureg, wdt->drv_data->rst_stat_reg, &rst_stat);
 461         if (ret)
 462                 dev_warn(wdt->dev, "Couldn't get RST_STAT register\n");
 463         else if (rst_stat & BIT(wdt->drv_data->rst_stat_bit))
 464                 return WDIOF_CARDRESET;
 465
 466         return 0;
 467 }
 468
 469 /* s3c2410_get_wdt_driver_data */
 470 static inline struct s3c2410_wdt_variant *
 471 get_wdt_drv_data(struct platform_device *pdev)
 472 {
 473         if (pdev->dev.of_node) {
 474                 const struct of_device_id *match;
 475                 match = of_match_node(s3c2410_wdt_match, pdev->dev.of_node);
 476                 return (struct s3c2410_wdt_variant *)match->data;
 477         } else {
 478                 return (struct s3c2410_wdt_variant *)
 479                         platform_get_device_id(pdev)->driver_data;
 480         }
 481 }
 482
 483 static int s3c2410wdt_probe(struct platform_device *pdev)
 484 {
 485         struct device *dev;
 486         struct s3c2410_wdt *wdt;
 487         struct resource *wdt_mem;
 488         struct resource *wdt_irq;
 489         unsigned int wtcon;
 490         int started = 0;
 491         int ret;
 492
 493         DBG("%s: probe=%p\n", __func__, pdev);
 494
 495         dev = &pdev->dev;
 496
 497         wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
 498         if (!wdt)
 499                 return -ENOMEM;
 500
 501         wdt->dev = &pdev->dev;
 502         spin_lock_init(&wdt->lock);
 503         wdt->wdt_device = s3c2410_wdd;
 504
 505         wdt->drv_data = get_wdt_drv_data(pdev);
 506         if (wdt->drv_data->quirks & QUIRKS_HAVE_PMUREG) {
 507                 wdt->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
 508                                                 "samsung,syscon-phandle");
 509                 if (IS_ERR(wdt->pmureg)) {
 510                         dev_err(dev, "syscon regmap lookup failed.\n");
 511                         return PTR_ERR(wdt->pmureg);
 512                 }
 513         }
 514
 515         wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 516         if (wdt_irq == NULL) {
 517                 dev_err(dev, "no irq resource specified\n");
 518                 ret = -ENOENT;
 519                 goto err;
 520         }
 521
 522         /* get the memory region for the watchdog timer */
 523         wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 524         wdt->reg_base = devm_ioremap_resource(dev, wdt_mem);
 525         if (IS_ERR(wdt->reg_base)) {
 526                 ret = PTR_ERR(wdt->reg_base);
 527                 goto err;
 528         }
 529
 530         DBG("probe: mapped reg_base=%p\n", wdt->reg_base);
 531
 532         wdt->clock = devm_clk_get(dev, "watchdog");
 533         if (IS_ERR(wdt->clock)) {
 534                 dev_err(dev, "failed to find watchdog clock source\n");
 535                 ret = PTR_ERR(wdt->clock);
 536                 goto err;
 537         }
 538
 539         ret = clk_prepare_enable(wdt->clock);
 540         if (ret < 0) {
 541                 dev_err(dev, "failed to enable clock\n");
 542                 return ret;
 543         }
 544
 545         ret = s3c2410wdt_cpufreq_register(wdt);
 546         if (ret < 0) {
 547                 dev_err(dev, "failed to register cpufreq\n");
 548                 goto err_clk;
 549         }
 550
 551         watchdog_set_drvdata(&wdt->wdt_device, wdt);
 552
 553         /* see if we can actually set the requested timer margin, and if
 554          * not, try the default value */
 555
 556         watchdog_init_timeout(&wdt->wdt_device, tmr_margin, &pdev->dev);
 557         ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
 558                                         wdt->wdt_device.timeout);
 559         if (ret) {
 560                 started = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
 561                                         CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
 562
 563                 if (started == 0)
 564                         dev_info(dev,
 565                            "tmr_margin value out of range, default %d used\n",
 566                                CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
 567                 else
 568                         dev_info(dev, "default timer value is out of range, "
 569                                                         "cannot start\n");
 570         }
 571
 572         ret = devm_request_irq(dev, wdt_irq->start, s3c2410wdt_irq, 0,
 573                                 pdev->name, pdev);
 574         if (ret != 0) {
 575                 dev_err(dev, "failed to install irq (%d)\n", ret);
 576                 goto err_cpufreq;
 577         }
 578
 579         watchdog_set_nowayout(&wdt->wdt_device, nowayout);
 580
 581         wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt);
 582
 583         ret = watchdog_register_device(&wdt->wdt_device);
 584         if (ret) {
 585                 dev_err(dev, "cannot register watchdog (%d)\n", ret);
 586                 goto err_cpufreq;
 587         }
 588
 589         ret = s3c2410wdt_mask_and_disable_reset(wdt, false);
 590         if (ret < 0)
 591                 goto err_unregister;
 592
 593         if (tmr_atboot && started == 0) {
 594                 dev_info(dev, "starting watchdog timer\n");
 595                 s3c2410wdt_start(&wdt->wdt_device);
 596         } else if (!tmr_atboot) {
 597                 /* if we're not enabling the watchdog, then ensure it is
 598                  * disabled if it has been left running from the bootloader
 599                  * or other source */
 600
 601                 s3c2410wdt_stop(&wdt->wdt_device);
 602         }
 603
 604         platform_set_drvdata(pdev, wdt);
 605
 606         /* print out a statement of readiness */
 607
 608         wtcon = readl(wdt->reg_base + S3C2410_WTCON);
 609
 610         dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n",
 611                  (wtcon & S3C2410_WTCON_ENABLE) ?  "" : "in",
 612                  (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis",
 613                  (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis");
 614
 615         return 0;
 616
 617  err_unregister:
 618         watchdog_unregister_device(&wdt->wdt_device);
 619
 620  err_cpufreq:
 621         s3c2410wdt_cpufreq_deregister(wdt);
 622
 623  err_clk:
 624         clk_disable_unprepare(wdt->clock);
 625
 626  err:
 627         return ret;
 628 }
 629
 630 static int s3c2410wdt_remove(struct platform_device *dev)
 631 {
 632         int ret;
 633         struct s3c2410_wdt *wdt = platform_get_drvdata(dev);
 634
 635         ret = s3c2410wdt_mask_and_disable_reset(wdt, true);
 636         if (ret < 0)
 637                 return ret;
 638
 639         watchdog_unregister_device(&wdt->wdt_device);
 640
 641         s3c2410wdt_cpufreq_deregister(wdt);
 642
 643         clk_disable_unprepare(wdt->clock);
 644
 645         return 0;
 646 }
 647
 648 static void s3c2410wdt_shutdown(struct platform_device *dev)
 649 {
 650         struct s3c2410_wdt *wdt = platform_get_drvdata(dev);
 651
 652         s3c2410wdt_mask_and_disable_reset(wdt, true);
 653
 654         s3c2410wdt_stop(&wdt->wdt_device);
 655 }
 656
 657 #ifdef CONFIG_PM_SLEEP
 658
 659 static int s3c2410wdt_suspend(struct device *dev)
 660 {
 661         int ret;
 662         struct s3c2410_wdt *wdt = dev_get_drvdata(dev);
 663
 664         /* Save watchdog state, and turn it off. */
 665         wdt->wtcon_save = readl(wdt->reg_base + S3C2410_WTCON);
 666         wdt->wtdat_save = readl(wdt->reg_base + S3C2410_WTDAT);
 667
 668         ret = s3c2410wdt_mask_and_disable_reset(wdt, true);
 669         if (ret < 0)
 670                 return ret;
 671
 672         /* Note that WTCNT doesn't need to be saved. */
 673         s3c2410wdt_stop(&wdt->wdt_device);
 674
 675         return 0;
 676 }
 677
 678 static int s3c2410wdt_resume(struct device *dev)
 679 {
 680         int ret;
 681         struct s3c2410_wdt *wdt = dev_get_drvdata(dev);
 682
 683         /* Restore watchdog state. */
 684         writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTDAT);
 685         writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTCNT);/* Reset count */
 686         writel(wdt->wtcon_save, wdt->reg_base + S3C2410_WTCON);
 687
 688         ret = s3c2410wdt_mask_and_disable_reset(wdt, false);
 689         if (ret < 0)
 690                 return ret;
 691
 692         dev_info(dev, "watchdog %sabled\n",
 693                 (wdt->wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis");
 694
 695         return 0;
 696 }
 697 #endif
 698
 699 static SIMPLE_DEV_PM_OPS(s3c2410wdt_pm_ops, s3c2410wdt_suspend,
 700                         s3c2410wdt_resume);
 701
 702 static struct platform_driver s3c2410wdt_driver = {
 703         .probe          = s3c2410wdt_probe,
 704         .remove         = s3c2410wdt_remove,
 705         .shutdown       = s3c2410wdt_shutdown,
 706         .id_table       = s3c2410_wdt_ids,
 707         .driver         = {
 708                 .owner  = THIS_MODULE,
 709                 .name   = "s3c2410-wdt",
 710                 .pm     = &s3c2410wdt_pm_ops,
 711                 .of_match_table = of_match_ptr(s3c2410_wdt_match),
 712         },
 713 };
 714
 715 module_platform_driver(s3c2410wdt_driver);
 716
 717 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, "
 718               "Dimitry Andric <dimitry.andric@tomtom.com>");
 719 MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver");
 720 MODULE_LICENSE("GPL");