1 /* linux/drivers/char/watchdog/s3c2410_wdt.c
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2410 Watchdog Timer Support
8 * Based on, softdog.c by Alan Cox,
9 * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
28 #include <linux/module.h>
29 #include <linux/moduleparam.h>
30 #include <linux/types.h>
31 #include <linux/timer.h>
32 #include <linux/watchdog.h>
33 #include <linux/platform_device.h>
34 #include <linux/interrupt.h>
35 #include <linux/clk.h>
36 #include <linux/uaccess.h>
38 #include <linux/cpufreq.h>
39 #include <linux/slab.h>
40 #include <linux/err.h>
42 #include <linux/mfd/syscon.h>
43 #include <linux/regmap.h>
45 #define S3C2410_WTCON 0x00
46 #define S3C2410_WTDAT 0x04
47 #define S3C2410_WTCNT 0x08
49 #define S3C2410_WTCON_RSTEN (1 << 0)
50 #define S3C2410_WTCON_INTEN (1 << 2)
51 #define S3C2410_WTCON_ENABLE (1 << 5)
53 #define S3C2410_WTCON_DIV16 (0 << 3)
54 #define S3C2410_WTCON_DIV32 (1 << 3)
55 #define S3C2410_WTCON_DIV64 (2 << 3)
56 #define S3C2410_WTCON_DIV128 (3 << 3)
58 #define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
59 #define S3C2410_WTCON_PRESCALE_MASK (0xff << 8)
61 #define CONFIG_S3C2410_WATCHDOG_ATBOOT (0)
62 #define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME (15)
64 #define EXYNOS5_RST_STAT_REG_OFFSET 0x0404
65 #define EXYNOS5_WDT_DISABLE_REG_OFFSET 0x0408
66 #define EXYNOS5_WDT_MASK_RESET_REG_OFFSET 0x040c
67 #define QUIRK_HAS_PMU_CONFIG (1 << 0)
68 #define QUIRK_HAS_RST_STAT (1 << 1)
70 /* These quirks require that we have a PMU register map */
71 #define QUIRKS_HAVE_PMUREG (QUIRK_HAS_PMU_CONFIG | \
74 static bool nowayout = WATCHDOG_NOWAYOUT;
75 static int tmr_margin;
76 static int tmr_atboot = CONFIG_S3C2410_WATCHDOG_ATBOOT;
77 static int soft_noboot;
80 module_param(tmr_margin, int, 0);
81 module_param(tmr_atboot, int, 0);
82 module_param(nowayout, bool, 0);
83 module_param(soft_noboot, int, 0);
84 module_param(debug, int, 0);
86 MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default="
87 __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME) ")");
88 MODULE_PARM_DESC(tmr_atboot,
89 "Watchdog is started at boot time if set to 1, default="
90 __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_ATBOOT));
91 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
92 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
93 MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, "
94 "0 to reboot (default 0)");
95 MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug (default 0)");
98 * struct s3c2410_wdt_variant - Per-variant config data
100 * @disable_reg: Offset in pmureg for the register that disables the watchdog
101 * timer reset functionality.
102 * @mask_reset_reg: Offset in pmureg for the register that masks the watchdog
103 * timer reset functionality.
104 * @mask_bit: Bit number for the watchdog timer in the disable register and the
105 * mask reset register.
106 * @rst_stat_reg: Offset in pmureg for the register that has the reset status.
107 * @rst_stat_bit: Bit number in the rst_stat register indicating a watchdog
109 * @quirks: A bitfield of quirks.
112 struct s3c2410_wdt_variant {
124 void __iomem *reg_base;
127 unsigned long wtcon_save;
128 unsigned long wtdat_save;
129 struct watchdog_device wdt_device;
130 struct notifier_block freq_transition;
131 struct s3c2410_wdt_variant *drv_data;
132 struct regmap *pmureg;
135 static const struct s3c2410_wdt_variant drv_data_s3c2410 = {
140 static const struct s3c2410_wdt_variant drv_data_exynos5250 = {
141 .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
142 .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
144 .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
146 .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT,
149 static const struct s3c2410_wdt_variant drv_data_exynos5420 = {
150 .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
151 .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
153 .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
155 .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT,
158 static const struct s3c2410_wdt_variant drv_data_exynos7 = {
159 .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
160 .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
162 .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
163 .rst_stat_bit = 23, /* A57 WDTRESET */
164 .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT,
167 static const struct of_device_id s3c2410_wdt_match[] = {
168 { .compatible = "samsung,s3c2410-wdt",
169 .data = &drv_data_s3c2410 },
170 { .compatible = "samsung,exynos5250-wdt",
171 .data = &drv_data_exynos5250 },
172 { .compatible = "samsung,exynos5420-wdt",
173 .data = &drv_data_exynos5420 },
174 { .compatible = "samsung,exynos7-wdt",
175 .data = &drv_data_exynos7 },
178 MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
181 static const struct platform_device_id s3c2410_wdt_ids[] = {
183 .name = "s3c2410-wdt",
184 .driver_data = (unsigned long)&drv_data_s3c2410,
188 MODULE_DEVICE_TABLE(platform, s3c2410_wdt_ids);
190 /* watchdog control routines */
192 #define DBG(fmt, ...) \
195 pr_info(fmt, ##__VA_ARGS__); \
200 static inline struct s3c2410_wdt *freq_to_wdt(struct notifier_block *nb)
202 return container_of(nb, struct s3c2410_wdt, freq_transition);
205 static int s3c2410wdt_mask_and_disable_reset(struct s3c2410_wdt *wdt, bool mask)
208 u32 mask_val = 1 << wdt->drv_data->mask_bit;
211 /* No need to do anything if no PMU CONFIG needed */
212 if (!(wdt->drv_data->quirks & QUIRK_HAS_PMU_CONFIG))
218 ret = regmap_update_bits(wdt->pmureg,
219 wdt->drv_data->disable_reg,
224 ret = regmap_update_bits(wdt->pmureg,
225 wdt->drv_data->mask_reset_reg,
229 dev_err(wdt->dev, "failed to update reg(%d)\n", ret);
234 static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
236 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
238 spin_lock(&wdt->lock);
239 writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
240 spin_unlock(&wdt->lock);
245 static void __s3c2410wdt_stop(struct s3c2410_wdt *wdt)
249 wtcon = readl(wdt->reg_base + S3C2410_WTCON);
250 wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN);
251 writel(wtcon, wdt->reg_base + S3C2410_WTCON);
254 static int s3c2410wdt_stop(struct watchdog_device *wdd)
256 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
258 spin_lock(&wdt->lock);
259 __s3c2410wdt_stop(wdt);
260 spin_unlock(&wdt->lock);
265 static int s3c2410wdt_start(struct watchdog_device *wdd)
268 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
270 spin_lock(&wdt->lock);
272 __s3c2410wdt_stop(wdt);
274 wtcon = readl(wdt->reg_base + S3C2410_WTCON);
275 wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128;
278 wtcon |= S3C2410_WTCON_INTEN;
279 wtcon &= ~S3C2410_WTCON_RSTEN;
281 wtcon &= ~S3C2410_WTCON_INTEN;
282 wtcon |= S3C2410_WTCON_RSTEN;
285 DBG("%s: count=0x%08x, wtcon=%08lx\n",
286 __func__, wdt->count, wtcon);
288 writel(wdt->count, wdt->reg_base + S3C2410_WTDAT);
289 writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
290 writel(wtcon, wdt->reg_base + S3C2410_WTCON);
291 spin_unlock(&wdt->lock);
296 static inline int s3c2410wdt_is_running(struct s3c2410_wdt *wdt)
298 return readl(wdt->reg_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE;
301 static int s3c2410wdt_set_heartbeat(struct watchdog_device *wdd, unsigned timeout)
303 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
304 unsigned long freq = clk_get_rate(wdt->clock);
306 unsigned int divisor = 1;
312 freq = DIV_ROUND_UP(freq, 128);
313 count = timeout * freq;
315 DBG("%s: count=%d, timeout=%d, freq=%lu\n",
316 __func__, count, timeout, freq);
318 /* if the count is bigger than the watchdog register,
319 then work out what we need to do (and if) we can
320 actually make this value
323 if (count >= 0x10000) {
324 divisor = DIV_ROUND_UP(count, 0xffff);
326 if (divisor > 0x100) {
327 dev_err(wdt->dev, "timeout %d too big\n", timeout);
332 DBG("%s: timeout=%d, divisor=%d, count=%d (%08x)\n",
333 __func__, timeout, divisor, count, DIV_ROUND_UP(count, divisor));
335 count = DIV_ROUND_UP(count, divisor);
338 /* update the pre-scaler */
339 wtcon = readl(wdt->reg_base + S3C2410_WTCON);
340 wtcon &= ~S3C2410_WTCON_PRESCALE_MASK;
341 wtcon |= S3C2410_WTCON_PRESCALE(divisor-1);
343 writel(count, wdt->reg_base + S3C2410_WTDAT);
344 writel(wtcon, wdt->reg_base + S3C2410_WTCON);
346 wdd->timeout = (count * divisor) / freq;
351 #define OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
353 static const struct watchdog_info s3c2410_wdt_ident = {
355 .firmware_version = 0,
356 .identity = "S3C2410 Watchdog",
359 static struct watchdog_ops s3c2410wdt_ops = {
360 .owner = THIS_MODULE,
361 .start = s3c2410wdt_start,
362 .stop = s3c2410wdt_stop,
363 .ping = s3c2410wdt_keepalive,
364 .set_timeout = s3c2410wdt_set_heartbeat,
367 static struct watchdog_device s3c2410_wdd = {
368 .info = &s3c2410_wdt_ident,
369 .ops = &s3c2410wdt_ops,
370 .timeout = CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME,
373 /* interrupt handler code */
375 static irqreturn_t s3c2410wdt_irq(int irqno, void *param)
377 struct s3c2410_wdt *wdt = platform_get_drvdata(param);
379 dev_info(wdt->dev, "watchdog timer expired (irq)\n");
381 s3c2410wdt_keepalive(&wdt->wdt_device);
385 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
387 static int s3c2410wdt_cpufreq_transition(struct notifier_block *nb,
388 unsigned long val, void *data)
391 struct s3c2410_wdt *wdt = freq_to_wdt(nb);
393 if (!s3c2410wdt_is_running(wdt))
396 if (val == CPUFREQ_PRECHANGE) {
397 /* To ensure that over the change we don't cause the
398 * watchdog to trigger, we perform an keep-alive if
399 * the watchdog is running.
402 s3c2410wdt_keepalive(&wdt->wdt_device);
403 } else if (val == CPUFREQ_POSTCHANGE) {
404 s3c2410wdt_stop(&wdt->wdt_device);
406 ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
407 wdt->wdt_device.timeout);
410 s3c2410wdt_start(&wdt->wdt_device);
419 dev_err(wdt->dev, "cannot set new value for timeout %d\n",
420 wdt->wdt_device.timeout);
424 static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt)
426 wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition;
428 return cpufreq_register_notifier(&wdt->freq_transition,
429 CPUFREQ_TRANSITION_NOTIFIER);
432 static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt)
434 wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition;
436 cpufreq_unregister_notifier(&wdt->freq_transition,
437 CPUFREQ_TRANSITION_NOTIFIER);
442 static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt)
447 static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt)
452 static inline unsigned int s3c2410wdt_get_bootstatus(struct s3c2410_wdt *wdt)
454 unsigned int rst_stat;
457 if (!(wdt->drv_data->quirks & QUIRK_HAS_RST_STAT))
460 ret = regmap_read(wdt->pmureg, wdt->drv_data->rst_stat_reg, &rst_stat);
462 dev_warn(wdt->dev, "Couldn't get RST_STAT register\n");
463 else if (rst_stat & BIT(wdt->drv_data->rst_stat_bit))
464 return WDIOF_CARDRESET;
469 /* s3c2410_get_wdt_driver_data */
470 static inline struct s3c2410_wdt_variant *
471 get_wdt_drv_data(struct platform_device *pdev)
473 if (pdev->dev.of_node) {
474 const struct of_device_id *match;
475 match = of_match_node(s3c2410_wdt_match, pdev->dev.of_node);
476 return (struct s3c2410_wdt_variant *)match->data;
478 return (struct s3c2410_wdt_variant *)
479 platform_get_device_id(pdev)->driver_data;
483 static int s3c2410wdt_probe(struct platform_device *pdev)
486 struct s3c2410_wdt *wdt;
487 struct resource *wdt_mem;
488 struct resource *wdt_irq;
493 DBG("%s: probe=%p\n", __func__, pdev);
497 wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
501 wdt->dev = &pdev->dev;
502 spin_lock_init(&wdt->lock);
503 wdt->wdt_device = s3c2410_wdd;
505 wdt->drv_data = get_wdt_drv_data(pdev);
506 if (wdt->drv_data->quirks & QUIRKS_HAVE_PMUREG) {
507 wdt->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
508 "samsung,syscon-phandle");
509 if (IS_ERR(wdt->pmureg)) {
510 dev_err(dev, "syscon regmap lookup failed.\n");
511 return PTR_ERR(wdt->pmureg);
515 wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
516 if (wdt_irq == NULL) {
517 dev_err(dev, "no irq resource specified\n");
522 /* get the memory region for the watchdog timer */
523 wdt_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
524 wdt->reg_base = devm_ioremap_resource(dev, wdt_mem);
525 if (IS_ERR(wdt->reg_base)) {
526 ret = PTR_ERR(wdt->reg_base);
530 DBG("probe: mapped reg_base=%p\n", wdt->reg_base);
532 wdt->clock = devm_clk_get(dev, "watchdog");
533 if (IS_ERR(wdt->clock)) {
534 dev_err(dev, "failed to find watchdog clock source\n");
535 ret = PTR_ERR(wdt->clock);
539 ret = clk_prepare_enable(wdt->clock);
541 dev_err(dev, "failed to enable clock\n");
545 ret = s3c2410wdt_cpufreq_register(wdt);
547 dev_err(dev, "failed to register cpufreq\n");
551 watchdog_set_drvdata(&wdt->wdt_device, wdt);
553 /* see if we can actually set the requested timer margin, and if
554 * not, try the default value */
556 watchdog_init_timeout(&wdt->wdt_device, tmr_margin, &pdev->dev);
557 ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
558 wdt->wdt_device.timeout);
560 started = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
561 CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
565 "tmr_margin value out of range, default %d used\n",
566 CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
568 dev_info(dev, "default timer value is out of range, "
572 ret = devm_request_irq(dev, wdt_irq->start, s3c2410wdt_irq, 0,
575 dev_err(dev, "failed to install irq (%d)\n", ret);
579 watchdog_set_nowayout(&wdt->wdt_device, nowayout);
581 wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt);
583 ret = watchdog_register_device(&wdt->wdt_device);
585 dev_err(dev, "cannot register watchdog (%d)\n", ret);
589 ret = s3c2410wdt_mask_and_disable_reset(wdt, false);
593 if (tmr_atboot && started == 0) {
594 dev_info(dev, "starting watchdog timer\n");
595 s3c2410wdt_start(&wdt->wdt_device);
596 } else if (!tmr_atboot) {
597 /* if we're not enabling the watchdog, then ensure it is
598 * disabled if it has been left running from the bootloader
601 s3c2410wdt_stop(&wdt->wdt_device);
604 platform_set_drvdata(pdev, wdt);
606 /* print out a statement of readiness */
608 wtcon = readl(wdt->reg_base + S3C2410_WTCON);
610 dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n",
611 (wtcon & S3C2410_WTCON_ENABLE) ? "" : "in",
612 (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis",
613 (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis");
618 watchdog_unregister_device(&wdt->wdt_device);
621 s3c2410wdt_cpufreq_deregister(wdt);
624 clk_disable_unprepare(wdt->clock);
630 static int s3c2410wdt_remove(struct platform_device *dev)
633 struct s3c2410_wdt *wdt = platform_get_drvdata(dev);
635 ret = s3c2410wdt_mask_and_disable_reset(wdt, true);
639 watchdog_unregister_device(&wdt->wdt_device);
641 s3c2410wdt_cpufreq_deregister(wdt);
643 clk_disable_unprepare(wdt->clock);
648 static void s3c2410wdt_shutdown(struct platform_device *dev)
650 struct s3c2410_wdt *wdt = platform_get_drvdata(dev);
652 s3c2410wdt_mask_and_disable_reset(wdt, true);
654 s3c2410wdt_stop(&wdt->wdt_device);
657 #ifdef CONFIG_PM_SLEEP
659 static int s3c2410wdt_suspend(struct device *dev)
662 struct s3c2410_wdt *wdt = dev_get_drvdata(dev);
664 /* Save watchdog state, and turn it off. */
665 wdt->wtcon_save = readl(wdt->reg_base + S3C2410_WTCON);
666 wdt->wtdat_save = readl(wdt->reg_base + S3C2410_WTDAT);
668 ret = s3c2410wdt_mask_and_disable_reset(wdt, true);
672 /* Note that WTCNT doesn't need to be saved. */
673 s3c2410wdt_stop(&wdt->wdt_device);
678 static int s3c2410wdt_resume(struct device *dev)
681 struct s3c2410_wdt *wdt = dev_get_drvdata(dev);
683 /* Restore watchdog state. */
684 writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTDAT);
685 writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTCNT);/* Reset count */
686 writel(wdt->wtcon_save, wdt->reg_base + S3C2410_WTCON);
688 ret = s3c2410wdt_mask_and_disable_reset(wdt, false);
692 dev_info(dev, "watchdog %sabled\n",
693 (wdt->wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis");
699 static SIMPLE_DEV_PM_OPS(s3c2410wdt_pm_ops, s3c2410wdt_suspend,
702 static struct platform_driver s3c2410wdt_driver = {
703 .probe = s3c2410wdt_probe,
704 .remove = s3c2410wdt_remove,
705 .shutdown = s3c2410wdt_shutdown,
706 .id_table = s3c2410_wdt_ids,
708 .owner = THIS_MODULE,
709 .name = "s3c2410-wdt",
710 .pm = &s3c2410wdt_pm_ops,
711 .of_match_table = of_match_ptr(s3c2410_wdt_match),
715 module_platform_driver(s3c2410wdt_driver);
717 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, "
718 "Dimitry Andric <dimitry.andric@tomtom.com>");
719 MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver");
720 MODULE_LICENSE("GPL");