2 * sp5100_tco : TCO timer driver for sp5100 chipsets
4 * (c) Copyright 2009 Google Inc., All Rights Reserved.
7 * (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights
9 * http://www.kernelconcepts.de
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
16 * See AMD Publication 43009 "AMD SB700/710/750 Register Reference Guide",
17 * AMD Publication 45482 "AMD SB800-Series Southbridges Register
22 * Includes, defines, variables, module parameters, ...
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27 #include <linux/module.h>
28 #include <linux/moduleparam.h>
29 #include <linux/types.h>
30 #include <linux/miscdevice.h>
31 #include <linux/watchdog.h>
32 #include <linux/init.h>
34 #include <linux/pci.h>
35 #include <linux/ioport.h>
36 #include <linux/platform_device.h>
37 #include <linux/uaccess.h>
40 #include "sp5100_tco.h"
42 /* Module and version information */
43 #define TCO_VERSION "0.03"
44 #define TCO_MODULE_NAME "SP5100 TCO timer"
45 #define TCO_DRIVER_NAME TCO_MODULE_NAME ", v" TCO_VERSION
47 /* internal variables */
48 static u32 tcobase_phys;
49 static u32 resbase_phys;
50 static u32 tco_wdt_fired;
51 static void __iomem *tcobase;
52 static unsigned int pm_iobase;
53 static DEFINE_SPINLOCK(tco_lock); /* Guards the hardware */
54 static unsigned long timer_alive;
55 static char tco_expect_close;
56 static struct pci_dev *sp5100_tco_pci;
57 static struct resource wdt_res = {
58 .name = "Watchdog Timer",
59 .flags = IORESOURCE_MEM,
62 /* the watchdog platform device */
63 static struct platform_device *sp5100_tco_platform_device;
65 /* module parameters */
67 #define WATCHDOG_HEARTBEAT 60 /* 60 sec default heartbeat. */
68 static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
69 module_param(heartbeat, int, 0);
70 MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (default="
71 __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
73 static bool nowayout = WATCHDOG_NOWAYOUT;
74 module_param(nowayout, bool, 0);
75 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started."
76 " (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
78 static unsigned int force_addr;
79 module_param(force_addr, uint, 0);
80 MODULE_PARM_DESC(force_addr, "Force the use of specified MMIO address."
81 " ONLY USE THIS PARAMETER IF YOU REALLY KNOW"
82 " WHAT YOU ARE DOING (default=none)");
85 * Some TCO specific functions
87 static void tco_timer_start(void)
92 spin_lock_irqsave(&tco_lock, flags);
93 val = readl(SP5100_WDT_CONTROL(tcobase));
94 val |= SP5100_WDT_START_STOP_BIT;
95 writel(val, SP5100_WDT_CONTROL(tcobase));
96 spin_unlock_irqrestore(&tco_lock, flags);
99 static void tco_timer_stop(void)
104 spin_lock_irqsave(&tco_lock, flags);
105 val = readl(SP5100_WDT_CONTROL(tcobase));
106 val &= ~SP5100_WDT_START_STOP_BIT;
107 writel(val, SP5100_WDT_CONTROL(tcobase));
108 spin_unlock_irqrestore(&tco_lock, flags);
111 static void tco_timer_keepalive(void)
116 spin_lock_irqsave(&tco_lock, flags);
117 val = readl(SP5100_WDT_CONTROL(tcobase));
118 val |= SP5100_WDT_TRIGGER_BIT;
119 writel(val, SP5100_WDT_CONTROL(tcobase));
120 spin_unlock_irqrestore(&tco_lock, flags);
123 static int tco_timer_set_heartbeat(int t)
127 if (t < 0 || t > 0xffff)
130 /* Write new heartbeat to watchdog */
131 spin_lock_irqsave(&tco_lock, flags);
132 writel(t, SP5100_WDT_COUNT(tcobase));
133 spin_unlock_irqrestore(&tco_lock, flags);
139 static void tco_timer_enable(void)
143 if (sp5100_tco_pci->revision >= 0x40) {
144 /* For SB800 or later */
145 /* Set the Watchdog timer resolution to 1 sec */
146 outb(SB800_PM_WATCHDOG_CONFIG, SB800_IO_PM_INDEX_REG);
147 val = inb(SB800_IO_PM_DATA_REG);
148 val |= SB800_PM_WATCHDOG_SECOND_RES;
149 outb(val, SB800_IO_PM_DATA_REG);
151 /* Enable watchdog decode bit and watchdog timer */
152 outb(SB800_PM_WATCHDOG_CONTROL, SB800_IO_PM_INDEX_REG);
153 val = inb(SB800_IO_PM_DATA_REG);
154 val |= SB800_PCI_WATCHDOG_DECODE_EN;
155 val &= ~SB800_PM_WATCHDOG_DISABLE;
156 outb(val, SB800_IO_PM_DATA_REG);
158 /* For SP5100 or SB7x0 */
159 /* Enable watchdog decode bit */
160 pci_read_config_dword(sp5100_tco_pci,
161 SP5100_PCI_WATCHDOG_MISC_REG,
164 val |= SP5100_PCI_WATCHDOG_DECODE_EN;
166 pci_write_config_dword(sp5100_tco_pci,
167 SP5100_PCI_WATCHDOG_MISC_REG,
170 /* Enable Watchdog timer and set the resolution to 1 sec */
171 outb(SP5100_PM_WATCHDOG_CONTROL, SP5100_IO_PM_INDEX_REG);
172 val = inb(SP5100_IO_PM_DATA_REG);
173 val |= SP5100_PM_WATCHDOG_SECOND_RES;
174 val &= ~SP5100_PM_WATCHDOG_DISABLE;
175 outb(val, SP5100_IO_PM_DATA_REG);
179 static void tco_timer_disable(void)
183 if (sp5100_tco_pci->revision >= 0x40) {
184 /* For SB800 or later */
185 /* Enable watchdog decode bit and Disable watchdog timer */
186 outb(SB800_PM_WATCHDOG_CONTROL, SB800_IO_PM_INDEX_REG);
187 val = inb(SB800_IO_PM_DATA_REG);
188 val |= SB800_PCI_WATCHDOG_DECODE_EN;
189 val |= SB800_PM_WATCHDOG_DISABLE;
190 outb(val, SB800_IO_PM_DATA_REG);
192 /* For SP5100 or SB7x0 */
193 /* Enable watchdog decode bit */
194 pci_read_config_dword(sp5100_tco_pci,
195 SP5100_PCI_WATCHDOG_MISC_REG,
198 val |= SP5100_PCI_WATCHDOG_DECODE_EN;
200 pci_write_config_dword(sp5100_tco_pci,
201 SP5100_PCI_WATCHDOG_MISC_REG,
204 /* Disable Watchdog timer */
205 outb(SP5100_PM_WATCHDOG_CONTROL, SP5100_IO_PM_INDEX_REG);
206 val = inb(SP5100_IO_PM_DATA_REG);
207 val |= SP5100_PM_WATCHDOG_DISABLE;
208 outb(val, SP5100_IO_PM_DATA_REG);
213 * /dev/watchdog handling
216 static int sp5100_tco_open(struct inode *inode, struct file *file)
218 /* /dev/watchdog can only be opened once */
219 if (test_and_set_bit(0, &timer_alive))
222 /* Reload and activate timer */
224 tco_timer_keepalive();
225 return nonseekable_open(inode, file);
228 static int sp5100_tco_release(struct inode *inode, struct file *file)
230 /* Shut off the timer. */
231 if (tco_expect_close == 42) {
234 pr_crit("Unexpected close, not stopping watchdog!\n");
235 tco_timer_keepalive();
237 clear_bit(0, &timer_alive);
238 tco_expect_close = 0;
242 static ssize_t sp5100_tco_write(struct file *file, const char __user *data,
243 size_t len, loff_t *ppos)
245 /* See if we got the magic character 'V' and reload the timer */
250 /* note: just in case someone wrote the magic character
251 * five months ago... */
252 tco_expect_close = 0;
254 /* scan to see whether or not we got the magic character
256 for (i = 0; i != len; i++) {
258 if (get_user(c, data + i))
261 tco_expect_close = 42;
265 /* someone wrote to us, we should reload the timer */
266 tco_timer_keepalive();
271 static long sp5100_tco_ioctl(struct file *file, unsigned int cmd,
274 int new_options, retval = -EINVAL;
276 void __user *argp = (void __user *)arg;
277 int __user *p = argp;
278 static const struct watchdog_info ident = {
279 .options = WDIOF_SETTIMEOUT |
280 WDIOF_KEEPALIVEPING |
282 .firmware_version = 0,
283 .identity = TCO_MODULE_NAME,
287 case WDIOC_GETSUPPORT:
288 return copy_to_user(argp, &ident,
289 sizeof(ident)) ? -EFAULT : 0;
290 case WDIOC_GETSTATUS:
291 case WDIOC_GETBOOTSTATUS:
292 return put_user(0, p);
293 case WDIOC_SETOPTIONS:
294 if (get_user(new_options, p))
296 if (new_options & WDIOS_DISABLECARD) {
300 if (new_options & WDIOS_ENABLECARD) {
302 tco_timer_keepalive();
306 case WDIOC_KEEPALIVE:
307 tco_timer_keepalive();
309 case WDIOC_SETTIMEOUT:
310 if (get_user(new_heartbeat, p))
312 if (tco_timer_set_heartbeat(new_heartbeat))
314 tco_timer_keepalive();
316 case WDIOC_GETTIMEOUT:
317 return put_user(heartbeat, p);
327 static const struct file_operations sp5100_tco_fops = {
328 .owner = THIS_MODULE,
330 .write = sp5100_tco_write,
331 .unlocked_ioctl = sp5100_tco_ioctl,
332 .open = sp5100_tco_open,
333 .release = sp5100_tco_release,
336 static struct miscdevice sp5100_tco_miscdev = {
337 .minor = WATCHDOG_MINOR,
339 .fops = &sp5100_tco_fops,
343 * Data for PCI driver interface
345 * This data only exists for exporting the supported
346 * PCI ids via MODULE_DEVICE_TABLE. We do not actually
347 * register a pci_driver, because someone else might
348 * want to register another driver on the same PCI id.
350 static DEFINE_PCI_DEVICE_TABLE(sp5100_tco_pci_tbl) = {
351 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, PCI_ANY_ID,
353 { 0, }, /* End of list */
355 MODULE_DEVICE_TABLE(pci, sp5100_tco_pci_tbl);
358 * Init & exit routines
360 static unsigned char sp5100_tco_setupdevice(void)
362 struct pci_dev *dev = NULL;
363 const char *dev_name = NULL;
365 u32 index_reg, data_reg, base_addr;
367 /* Match the PCI device */
368 for_each_pci_dev(dev) {
369 if (pci_match_id(sp5100_tco_pci_tbl, dev) != NULL) {
370 sp5100_tco_pci = dev;
378 pr_info("PCI Revision ID: 0x%x\n", sp5100_tco_pci->revision);
381 * Determine type of southbridge chipset.
383 if (sp5100_tco_pci->revision >= 0x40) {
384 dev_name = SB800_DEVNAME;
385 index_reg = SB800_IO_PM_INDEX_REG;
386 data_reg = SB800_IO_PM_DATA_REG;
387 base_addr = SB800_PM_WATCHDOG_BASE;
389 dev_name = SP5100_DEVNAME;
390 index_reg = SP5100_IO_PM_INDEX_REG;
391 data_reg = SP5100_IO_PM_DATA_REG;
392 base_addr = SP5100_PM_WATCHDOG_BASE;
395 /* Request the IO ports used by this driver */
396 pm_iobase = SP5100_IO_PM_INDEX_REG;
397 if (!request_region(pm_iobase, SP5100_PM_IOPORTS_SIZE, dev_name)) {
398 pr_err("I/O address 0x%04x already in use\n", pm_iobase);
403 * First, Find the watchdog timer MMIO address from indirect I/O.
405 outb(base_addr+3, index_reg);
407 outb(base_addr+2, index_reg);
408 val = val << 8 | inb(data_reg);
409 outb(base_addr+1, index_reg);
410 val = val << 8 | inb(data_reg);
411 outb(base_addr+0, index_reg);
412 /* Low three bits of BASE are reserved */
413 val = val << 8 | (inb(data_reg) & 0xf8);
415 pr_debug("Got 0x%04x from indirect I/O\n", val);
417 /* Check MMIO address conflict */
418 if (request_mem_region_exclusive(val, SP5100_WDT_MEM_MAP_SIZE,
422 pr_debug("MMIO address 0x%04x already in use\n", val);
425 * Secondly, Find the watchdog timer MMIO address
426 * from SBResource_MMIO register.
428 if (sp5100_tco_pci->revision >= 0x40) {
429 /* Read SBResource_MMIO from AcpiMmioEn(PM_Reg: 24h) */
430 outb(SB800_PM_ACPI_MMIO_EN+3, SB800_IO_PM_INDEX_REG);
431 val = inb(SB800_IO_PM_DATA_REG);
432 outb(SB800_PM_ACPI_MMIO_EN+2, SB800_IO_PM_INDEX_REG);
433 val = val << 8 | inb(SB800_IO_PM_DATA_REG);
434 outb(SB800_PM_ACPI_MMIO_EN+1, SB800_IO_PM_INDEX_REG);
435 val = val << 8 | inb(SB800_IO_PM_DATA_REG);
436 outb(SB800_PM_ACPI_MMIO_EN+0, SB800_IO_PM_INDEX_REG);
437 val = val << 8 | inb(SB800_IO_PM_DATA_REG);
439 /* Read SBResource_MMIO from PCI config(PCI_Reg: 9Ch) */
440 pci_read_config_dword(sp5100_tco_pci,
441 SP5100_SB_RESOURCE_MMIO_BASE, &val);
444 /* The SBResource_MMIO is enabled and mapped memory space? */
445 if ((val & (SB800_ACPI_MMIO_DECODE_EN | SB800_ACPI_MMIO_SEL)) ==
446 SB800_ACPI_MMIO_DECODE_EN) {
447 /* Clear unnecessary the low twelve bits */
449 /* Add the Watchdog Timer offset to base address. */
450 val += SB800_PM_WDT_MMIO_OFFSET;
451 /* Check MMIO address conflict */
452 if (request_mem_region_exclusive(val, SP5100_WDT_MEM_MAP_SIZE,
454 pr_debug("Got 0x%04x from SBResource_MMIO register\n",
458 pr_debug("MMIO address 0x%04x already in use\n", val);
460 pr_debug("SBResource_MMIO is disabled(0x%04x)\n", val);
463 * Lastly re-programming the watchdog timer MMIO address,
464 * This method is a last resort...
466 * Before re-programming, to ensure that the watchdog timer
467 * is disabled, disable the watchdog timer.
473 * Force the use of watchdog timer MMIO address, and aligned to
479 pr_info("Force the use of 0x%04x as MMIO address\n", val);
482 * Get empty slot into the resource tree for watchdog timer.
484 if (allocate_resource(&iomem_resource,
486 SP5100_WDT_MEM_MAP_SIZE,
492 pr_err("MMIO allocation failed\n");
496 val = resbase_phys = wdt_res.start;
497 pr_debug("Got 0x%04x from resource tree\n", val);
500 /* Restore to the low three bits */
501 outb(base_addr+0, index_reg);
502 tmp_val = val | (inb(data_reg) & 0x7);
504 /* Re-programming the watchdog timer base address */
505 outb(base_addr+0, index_reg);
506 outb((tmp_val >> 0) & 0xff, data_reg);
507 outb(base_addr+1, index_reg);
508 outb((tmp_val >> 8) & 0xff, data_reg);
509 outb(base_addr+2, index_reg);
510 outb((tmp_val >> 16) & 0xff, data_reg);
511 outb(base_addr+3, index_reg);
512 outb((tmp_val >> 24) & 0xff, data_reg);
514 if (!request_mem_region_exclusive(val, SP5100_WDT_MEM_MAP_SIZE,
516 pr_err("MMIO address 0x%04x already in use\n", val);
523 tcobase = ioremap(val, SP5100_WDT_MEM_MAP_SIZE);
525 pr_err("failed to get tcobase address\n");
526 goto unreg_mem_region;
529 pr_info("Using 0x%04x for watchdog MMIO address\n", val);
531 /* Setup the watchdog timer */
534 /* Check that the watchdog action is set to reset the system */
535 val = readl(SP5100_WDT_CONTROL(tcobase));
537 * Save WatchDogFired status, because WatchDogFired flag is
540 tco_wdt_fired = val & SP5100_PM_WATCHDOG_FIRED;
541 val &= ~SP5100_PM_WATCHDOG_ACTION_RESET;
542 writel(val, SP5100_WDT_CONTROL(tcobase));
544 /* Set a reasonable heartbeat before we stop the timer */
545 tco_timer_set_heartbeat(heartbeat);
548 * Stop the TCO before we change anything so we don't race with
557 release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE);
560 release_resource(&wdt_res);
562 release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE);
567 static int sp5100_tco_init(struct platform_device *dev)
573 * Check whether or not the hardware watchdog is there. If found, then
576 if (!sp5100_tco_setupdevice())
579 /* Check to see if last reboot was due to watchdog timeout */
580 pr_info("Last reboot was %striggered by watchdog.\n",
581 tco_wdt_fired ? "" : "not ");
584 * Check that the heartbeat value is within it's range.
585 * If not, reset to the default.
587 if (tco_timer_set_heartbeat(heartbeat)) {
588 heartbeat = WATCHDOG_HEARTBEAT;
589 tco_timer_set_heartbeat(heartbeat);
592 ret = misc_register(&sp5100_tco_miscdev);
594 pr_err("cannot register miscdev on minor=%d (err=%d)\n",
595 WATCHDOG_MINOR, ret);
599 clear_bit(0, &timer_alive);
601 /* Show module parameters */
602 if (force_addr == tcobase_phys)
603 /* The force_addr is vaild */
604 sprintf(addr_str, "0x%04x", force_addr);
606 strcpy(addr_str, "none");
608 pr_info("initialized (0x%p). heartbeat=%d sec (nowayout=%d, "
610 tcobase, heartbeat, nowayout, addr_str);
616 release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE);
618 release_resource(&wdt_res);
619 release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE);
623 static void sp5100_tco_cleanup(void)
625 /* Stop the timer before we leave */
630 misc_deregister(&sp5100_tco_miscdev);
632 release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE);
634 release_resource(&wdt_res);
635 release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE);
638 static int sp5100_tco_remove(struct platform_device *dev)
641 sp5100_tco_cleanup();
645 static void sp5100_tco_shutdown(struct platform_device *dev)
650 static struct platform_driver sp5100_tco_driver = {
651 .probe = sp5100_tco_init,
652 .remove = sp5100_tco_remove,
653 .shutdown = sp5100_tco_shutdown,
655 .owner = THIS_MODULE,
656 .name = TCO_MODULE_NAME,
660 static int __init sp5100_tco_init_module(void)
664 pr_info("SP5100/SB800 TCO WatchDog Timer Driver v%s\n", TCO_VERSION);
666 err = platform_driver_register(&sp5100_tco_driver);
670 sp5100_tco_platform_device = platform_device_register_simple(
671 TCO_MODULE_NAME, -1, NULL, 0);
672 if (IS_ERR(sp5100_tco_platform_device)) {
673 err = PTR_ERR(sp5100_tco_platform_device);
674 goto unreg_platform_driver;
679 unreg_platform_driver:
680 platform_driver_unregister(&sp5100_tco_driver);
684 static void __exit sp5100_tco_cleanup_module(void)
686 platform_device_unregister(sp5100_tco_platform_device);
687 platform_driver_unregister(&sp5100_tco_driver);
688 pr_info("SP5100/SB800 TCO Watchdog Module Unloaded\n");
691 module_init(sp5100_tco_init_module);
692 module_exit(sp5100_tco_cleanup_module);
694 MODULE_AUTHOR("Priyanka Gupta");
695 MODULE_DESCRIPTION("TCO timer driver for SP5100/SB800 chipset");
696 MODULE_LICENSE("GPL");
697 MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);