1 #ifndef _ASM_IA64_BITOPS_H
2 #define _ASM_IA64_BITOPS_H
5 * Copyright (C) 1998-2003 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
8 * 02/06/02 find_next_bit() and find_first_bit() added from Erich Focht's ia64
12 #include <linux/compiler.h>
13 #include <linux/types.h>
14 #include <asm/intrinsics.h>
17 * set_bit - Atomically set a bit in memory
19 * @addr: the address to start counting from
21 * This function is atomic and may not be reordered. See __set_bit()
22 * if you do not require the atomic guarantees.
23 * Note that @nr may be almost arbitrarily large; this function is not
24 * restricted to acting on a single-word quantity.
26 * The address must be (at least) "long" aligned.
27 * Note that there are driver (e.g., eepro100) which use these operations to
28 * operate on hw-defined data-structures, so we can't easily change these
29 * operations to force a bigger alignment.
31 * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
33 static __inline__ void
34 set_bit (int nr, volatile void *addr)
40 m = (volatile __u32 *) addr + (nr >> 5);
46 } while (cmpxchg_acq(m, old, new) != old);
50 * __set_bit - Set a bit in memory
52 * @addr: the address to start counting from
54 * Unlike set_bit(), this function is non-atomic and may be reordered.
55 * If it's called on the same region of memory simultaneously, the effect
56 * may be that only one operation succeeds.
58 static __inline__ void
59 __set_bit (int nr, volatile void *addr)
61 *((__u32 *) addr + (nr >> 5)) |= (1 << (nr & 31));
65 * clear_bit() has "acquire" semantics.
67 #define smp_mb__before_clear_bit() smp_mb()
68 #define smp_mb__after_clear_bit() do { /* skip */; } while (0)
71 * clear_bit - Clears a bit in memory
73 * @addr: Address to start counting from
75 * clear_bit() is atomic and may not be reordered. However, it does
76 * not contain a memory barrier, so if it is used for locking purposes,
77 * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
78 * in order to ensure changes are visible on other processors.
80 static __inline__ void
81 clear_bit (int nr, volatile void *addr)
87 m = (volatile __u32 *) addr + (nr >> 5);
88 mask = ~(1 << (nr & 31));
93 } while (cmpxchg_acq(m, old, new) != old);
97 * clear_bit_unlock - Clears a bit in memory with release
99 * @addr: Address to start counting from
101 * clear_bit_unlock() is atomic and may not be reordered. It does
102 * contain a memory barrier suitable for unlock type operations.
104 static __inline__ void
105 clear_bit_unlock (int nr, volatile void *addr)
107 __u32 mask, old, new;
109 CMPXCHG_BUGCHECK_DECL
111 m = (volatile __u32 *) addr + (nr >> 5);
112 mask = ~(1 << (nr & 31));
117 } while (cmpxchg_rel(m, old, new) != old);
121 * __clear_bit_unlock - Non-atomically clear a bit with release
123 * This is like clear_bit_unlock, but the implementation may use a non-atomic
124 * store (this one uses an atomic, however).
126 #define __clear_bit_unlock clear_bit_unlock
129 * __clear_bit - Clears a bit in memory (non-atomic version)
131 static __inline__ void
132 __clear_bit (int nr, volatile void *addr)
134 volatile __u32 *p = (__u32 *) addr + (nr >> 5);
135 __u32 m = 1 << (nr & 31);
140 * change_bit - Toggle a bit in memory
142 * @addr: Address to start counting from
144 * change_bit() is atomic and may not be reordered.
145 * Note that @nr may be almost arbitrarily large; this function is not
146 * restricted to acting on a single-word quantity.
148 static __inline__ void
149 change_bit (int nr, volatile void *addr)
153 CMPXCHG_BUGCHECK_DECL
155 m = (volatile __u32 *) addr + (nr >> 5);
156 bit = (1 << (nr & 31));
161 } while (cmpxchg_acq(m, old, new) != old);
165 * __change_bit - Toggle a bit in memory
166 * @nr: the bit to set
167 * @addr: the address to start counting from
169 * Unlike change_bit(), this function is non-atomic and may be reordered.
170 * If it's called on the same region of memory simultaneously, the effect
171 * may be that only one operation succeeds.
173 static __inline__ void
174 __change_bit (int nr, volatile void *addr)
176 *((__u32 *) addr + (nr >> 5)) ^= (1 << (nr & 31));
180 * test_and_set_bit - Set a bit and return its old value
182 * @addr: Address to count from
184 * This operation is atomic and cannot be reordered.
185 * It also implies a memory barrier.
187 static __inline__ int
188 test_and_set_bit (int nr, volatile void *addr)
192 CMPXCHG_BUGCHECK_DECL
194 m = (volatile __u32 *) addr + (nr >> 5);
195 bit = 1 << (nr & 31);
200 } while (cmpxchg_acq(m, old, new) != old);
201 return (old & bit) != 0;
205 * test_and_set_bit_lock - Set a bit and return its old value for lock
207 * @addr: Address to count from
209 * This is the same as test_and_set_bit on ia64
211 #define test_and_set_bit_lock test_and_set_bit
214 * __test_and_set_bit - Set a bit and return its old value
216 * @addr: Address to count from
218 * This operation is non-atomic and can be reordered.
219 * If two examples of this operation race, one can appear to succeed
220 * but actually fail. You must protect multiple accesses with a lock.
222 static __inline__ int
223 __test_and_set_bit (int nr, volatile void *addr)
225 __u32 *p = (__u32 *) addr + (nr >> 5);
226 __u32 m = 1 << (nr & 31);
227 int oldbitset = (*p & m) != 0;
234 * test_and_clear_bit - Clear a bit and return its old value
236 * @addr: Address to count from
238 * This operation is atomic and cannot be reordered.
239 * It also implies a memory barrier.
241 static __inline__ int
242 test_and_clear_bit (int nr, volatile void *addr)
244 __u32 mask, old, new;
246 CMPXCHG_BUGCHECK_DECL
248 m = (volatile __u32 *) addr + (nr >> 5);
249 mask = ~(1 << (nr & 31));
254 } while (cmpxchg_acq(m, old, new) != old);
255 return (old & ~mask) != 0;
259 * __test_and_clear_bit - Clear a bit and return its old value
261 * @addr: Address to count from
263 * This operation is non-atomic and can be reordered.
264 * If two examples of this operation race, one can appear to succeed
265 * but actually fail. You must protect multiple accesses with a lock.
267 static __inline__ int
268 __test_and_clear_bit(int nr, volatile void * addr)
270 __u32 *p = (__u32 *) addr + (nr >> 5);
271 __u32 m = 1 << (nr & 31);
272 int oldbitset = *p & m;
279 * test_and_change_bit - Change a bit and return its old value
281 * @addr: Address to count from
283 * This operation is atomic and cannot be reordered.
284 * It also implies a memory barrier.
286 static __inline__ int
287 test_and_change_bit (int nr, volatile void *addr)
291 CMPXCHG_BUGCHECK_DECL
293 m = (volatile __u32 *) addr + (nr >> 5);
294 bit = (1 << (nr & 31));
299 } while (cmpxchg_acq(m, old, new) != old);
300 return (old & bit) != 0;
304 * WARNING: non atomic version.
306 static __inline__ int
307 __test_and_change_bit (int nr, void *addr)
309 __u32 old, bit = (1 << (nr & 31));
310 __u32 *m = (__u32 *) addr + (nr >> 5);
314 return (old & bit) != 0;
317 static __inline__ int
318 test_bit (int nr, const volatile void *addr)
320 return 1 & (((const volatile __u32 *) addr)[nr >> 5] >> (nr & 31));
324 * ffz - find the first zero bit in a long word
325 * @x: The long word to find the bit in
327 * Returns the bit-number (0..63) of the first (least significant) zero bit.
328 * Undefined if no zero exists, so code should check against ~0UL first...
330 static inline unsigned long
331 ffz (unsigned long x)
333 unsigned long result;
335 result = ia64_popcnt(x & (~x - 1));
340 * __ffs - find first bit in word.
341 * @x: The word to search
343 * Undefined if no bit exists, so code should check against 0 first.
345 static __inline__ unsigned long
346 __ffs (unsigned long x)
348 unsigned long result;
350 result = ia64_popcnt((x-1) & ~x);
357 * Return bit number of last (most-significant) bit set. Undefined
358 * for x==0. Bits are numbered from 0..63 (e.g., ia64_fls(9) == 3).
360 static inline unsigned long
361 ia64_fls (unsigned long x)
366 exp = ia64_getf_exp(d);
371 * Find the last (most significant) bit set. Returns 0 for x==0 and
372 * bits are numbered from 1..32 (e.g., fls(9) == 4).
377 unsigned long x = t & 0xffffffffu;
386 return ia64_popcnt(x);
389 #include <asm-generic/bitops/fls64.h>
392 * ffs: find first bit set. This is defined the same way as the libc and
393 * compiler builtin ffs routines, therefore differs in spirit from the above
394 * ffz (man ffs): it operates on "int" values only and the result value is the
395 * bit number + 1. ffs(0) is defined to return zero.
397 #define ffs(x) __builtin_ffs(x)
400 * hweightN: returns the hamming weight (i.e. the number
401 * of bits set) of a N-bit word
403 static __inline__ unsigned long
404 hweight64 (unsigned long x)
406 unsigned long result;
407 result = ia64_popcnt(x);
411 #define hweight32(x) (unsigned int) hweight64((x) & 0xfffffffful)
412 #define hweight16(x) (unsigned int) hweight64((x) & 0xfffful)
413 #define hweight8(x) (unsigned int) hweight64((x) & 0xfful)
415 #endif /* __KERNEL__ */
417 #include <asm-generic/bitops/find.h>
421 #include <asm-generic/bitops/ext2-non-atomic.h>
423 #define ext2_set_bit_atomic(l,n,a) test_and_set_bit(n,a)
424 #define ext2_clear_bit_atomic(l,n,a) test_and_clear_bit(n,a)
426 #include <asm-generic/bitops/minix.h>
427 #include <asm-generic/bitops/sched.h>
429 #endif /* __KERNEL__ */
431 #endif /* _ASM_IA64_BITOPS_H */