1 #ifndef _ASM_POWERPC_PCI_BRIDGE_H
2 #define _ASM_POWERPC_PCI_BRIDGE_H
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
10 #include <linux/pci.h>
11 #include <linux/list.h>
12 #include <linux/ioport.h>
17 * Structure of a PCI controller (host bridge)
19 struct pci_controller {
25 struct device_node *dn;
26 struct list_head list_node;
27 struct device *parent;
35 void __iomem *io_base_virt;
39 resource_size_t io_base_phys;
41 /* Some machines (PReP) have a non 1:1 mapping of
42 * the PCI memory space in the CPU bus space
44 resource_size_t pci_mem_offset;
46 unsigned long pci_io_size;
50 volatile unsigned int __iomem *cfg_addr;
51 volatile void __iomem *cfg_data;
55 * Used for variants of PCI indirect handling and possible quirks:
56 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
57 * EXT_REG - provides access to PCI-e extended registers
58 * SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS
59 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
60 * to determine which bus number to match on when generating type0
62 * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
63 * hanging if we don't have link and try to do config cycles to
64 * anything but the PHB. Only allow talking to the PHB if this is
66 * BIG_ENDIAN - cfg_addr is a big endian register
68 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
69 #define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
70 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
71 #define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
72 #define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
74 #endif /* !CONFIG_PPC64 */
75 /* Currently, we limit ourselves to 1 IO range and 3 mem
76 * ranges since the common pci_bus structure can't handle more
78 struct resource io_resource;
79 struct resource mem_resources[3];
80 int global_number; /* PCI domain number */
83 unsigned long dma_window_base_cur;
84 unsigned long dma_window_size;
87 #endif /* CONFIG_PPC64 */
92 static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
97 static inline int isa_vaddr_is_ioport(void __iomem *address)
99 /* No specific ISA handling on ppc32 at this stage, it
100 * all goes through PCI
105 /* These are used for config access before all the PCI probing
107 extern int early_read_config_byte(struct pci_controller *hose, int bus,
108 int dev_fn, int where, u8 *val);
109 extern int early_read_config_word(struct pci_controller *hose, int bus,
110 int dev_fn, int where, u16 *val);
111 extern int early_read_config_dword(struct pci_controller *hose, int bus,
112 int dev_fn, int where, u32 *val);
113 extern int early_write_config_byte(struct pci_controller *hose, int bus,
114 int dev_fn, int where, u8 val);
115 extern int early_write_config_word(struct pci_controller *hose, int bus,
116 int dev_fn, int where, u16 val);
117 extern int early_write_config_dword(struct pci_controller *hose, int bus,
118 int dev_fn, int where, u32 val);
120 extern int early_find_capability(struct pci_controller *hose, int bus,
121 int dev_fn, int cap);
123 extern void setup_indirect_pci(struct pci_controller* hose,
124 resource_size_t cfg_addr,
125 resource_size_t cfg_data, u32 flags);
126 extern void setup_grackle(struct pci_controller *hose);
127 extern void __init update_bridge_resource(struct pci_dev *dev,
128 struct resource *res);
130 #else /* CONFIG_PPC64 */
133 * PCI stuff, for nodes representing PCI devices, pointed to
134 * by device_node->data.
139 int busno; /* pci bus number */
140 int bussubno; /* pci subordinate bus number */
141 int devfn; /* pci device and function number */
142 int class_code; /* pci device class */
144 struct pci_controller *phb; /* for pci devices */
145 struct iommu_table *iommu_table; /* for phb's or bridges */
146 struct pci_dev *pcidev; /* back-pointer to the pci device */
147 struct device_node *node; /* back-pointer to the device_node */
149 int pci_ext_config_space; /* for pci devices */
152 int eeh_mode; /* See eeh.h for possible EEH_MODEs */
154 int eeh_pe_config_addr; /* new-style partition endpoint address */
155 int eeh_check_count; /* # times driver ignored error */
156 int eeh_freeze_count; /* # times this device froze up. */
157 int eeh_false_positives; /* # times this device reported #ff's */
158 u32 config_space[16]; /* saved PCI config space */
162 /* Get the pointer to a device_node's pci_dn */
163 #define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
165 extern struct device_node *fetch_dev_dn(struct pci_dev *dev);
167 /* Get a device_node from a pci_dev. This code must be fast except
168 * in the case where the sysdata is incorrect and needs to be fixed
169 * up (this will only happen once).
170 * In this case the sysdata will have been inherited from a PCI host
171 * bridge or a PCI-PCI bridge further up the tree, so it will point
172 * to a valid struct pci_dn, just not the one we want.
174 static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev)
176 struct device_node *dn = dev->sysdata;
177 struct pci_dn *pdn = dn->data;
179 if (pdn && pdn->devfn == dev->devfn && pdn->busno == dev->bus->number)
180 return dn; /* fast path. sysdata is good */
181 return fetch_dev_dn(dev);
184 static inline int pci_device_from_OF_node(struct device_node *np,
189 *bus = PCI_DN(np)->busno;
190 *devfn = PCI_DN(np)->devfn;
194 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
197 return pci_device_to_OF_node(bus->self);
199 return bus->sysdata; /* Must be root bus (PHB) */
202 /** Find the bus corresponding to the indicated device node */
203 extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);
205 /** Remove all of the PCI devices under this bus */
206 extern void pcibios_remove_pci_devices(struct pci_bus *bus);
208 /** Discover new pci devices under this bus, and add them */
209 extern void pcibios_add_pci_devices(struct pci_bus *bus);
210 extern void pcibios_fixup_new_pci_devices(struct pci_bus *bus, int fix_bus);
212 extern int pcibios_remove_root_bus(struct pci_controller *phb);
214 static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
216 struct device_node *busdn = bus->sysdata;
218 BUG_ON(busdn == NULL);
219 return PCI_DN(busdn)->phb;
223 extern void isa_bridge_find_early(struct pci_controller *hose);
225 static inline int isa_vaddr_is_ioport(void __iomem *address)
227 /* Check if address hits the reserved legacy IO range */
228 unsigned long ea = (unsigned long)address;
229 return ea >= ISA_IO_BASE && ea < ISA_IO_END;
232 extern int pcibios_unmap_io_space(struct pci_bus *bus);
233 extern int pcibios_map_io_space(struct pci_bus *bus);
235 /* Return values for ppc_md.pci_probe_mode function */
236 #define PCI_PROBE_NONE -1 /* Don't look at this bus at all */
237 #define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */
238 #define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */
241 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
243 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
246 #endif /* CONFIG_PPC64 */
248 /* Get the PCI host controller for an OF device */
249 extern struct pci_controller *pci_find_hose_for_OF_device(
250 struct device_node* node);
252 /* Fill up host controller resources from the OF node */
253 extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
254 struct device_node *dev, int primary);
256 /* Allocate & free a PCI host bridge structure */
257 extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
258 extern void pcibios_free_controller(struct pci_controller *phb);
261 extern unsigned long pci_address_to_pio(phys_addr_t address);
262 extern int pcibios_vaddr_is_ioport(void __iomem *address);
264 static inline unsigned long pci_address_to_pio(phys_addr_t address)
266 return (unsigned long)-1;
268 static inline int pcibios_vaddr_is_ioport(void __iomem *address)
272 #endif /* CONFIG_PCI */
274 #endif /* __KERNEL__ */
275 #endif /* _ASM_POWERPC_PCI_BRIDGE_H */