1 #ifndef __ASM_SH_HW_IRQ_H
2 #define __ASM_SH_HW_IRQ_H
4 #include <linux/init.h>
5 #include <asm/atomic.h>
7 extern atomic_t irq_err_count;
11 unsigned char ipr_idx; /* Index for the IPR registered */
12 unsigned char shift; /* Number of bits to shift the data */
13 unsigned char priority; /* The priority */
17 unsigned long *ipr_offsets;
18 unsigned int nr_offsets;
19 struct ipr_data *ipr_data;
24 void register_ipr_controller(struct ipr_desc *);
26 typedef unsigned char intc_enum;
33 #define INTC_VECT(enum_id, vect) { enum_id, vect }
34 #define INTC_IRQ(enum_id, irq) INTC_VECT(enum_id, irq2evt(irq))
38 unsigned char priority;
41 #define INTC_PRIO(enum_id, prio) { enum_id, prio }
45 intc_enum enum_ids[32];
48 #define INTC_GROUP(enum_id, ids...) { enum_id, { ids } }
50 struct intc_mask_reg {
51 unsigned long set_reg, clr_reg, reg_width;
52 intc_enum enum_ids[32];
55 struct intc_prio_reg {
56 unsigned long set_reg, clr_reg, reg_width, field_width;
57 intc_enum enum_ids[16];
60 struct intc_sense_reg {
61 unsigned long reg, reg_width, field_width;
62 intc_enum enum_ids[16];
66 struct intc_vect *vectors;
67 unsigned int nr_vectors;
68 struct intc_group *groups;
69 unsigned int nr_groups;
70 struct intc_prio *priorities;
71 unsigned int nr_priorities;
72 struct intc_mask_reg *mask_regs;
73 unsigned int nr_mask_regs;
74 struct intc_prio_reg *prio_regs;
75 unsigned int nr_prio_regs;
76 struct intc_sense_reg *sense_regs;
77 unsigned int nr_sense_regs;
81 #define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
82 #define DECLARE_INTC_DESC(symbol, chipname, vectors, groups, \
83 priorities, mask_regs, prio_regs, sense_regs) \
84 struct intc_desc symbol __initdata = { \
85 _INTC_ARRAY(vectors), _INTC_ARRAY(groups), \
86 _INTC_ARRAY(priorities), \
87 _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
88 _INTC_ARRAY(sense_regs), \
92 void __init register_intc_controller(struct intc_desc *desc);
93 int intc_set_priority(unsigned int irq, unsigned int prio);
95 void __init plat_irq_setup(void);
97 enum { IRQ_MODE_IRQ, IRQ_MODE_IRQ7654, IRQ_MODE_IRQ3210,
98 IRQ_MODE_IRL7654_MASK, IRQ_MODE_IRL3210_MASK,
99 IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 };
100 void __init plat_irq_setup_pins(int mode);
102 #endif /* __ASM_SH_HW_IRQ_H */