1 #ifndef __ASM_X86_MSR_H_
2 #define __ASM_X86_MSR_H_
4 #include <asm/msr-index.h>
7 # include <linux/types.h>
12 static inline unsigned long long native_read_tscp(int *aux)
14 unsigned long low, high;
15 asm volatile (".byte 0x0f,0x01,0xf9"
16 : "=a" (low), "=d" (high), "=c" (*aux));
17 return low | ((u64)high >> 32);
20 #define rdtscp(low, high, aux) \
22 unsigned long long _val = native_read_tscp(&(aux)); \
24 (high) = (u32)(_val >> 32); \
27 #define rdtscpll(val, aux) (val) = native_read_tscp(&(aux))
36 #include <asm/errno.h>
38 static inline unsigned long long native_read_msr(unsigned int msr)
40 unsigned long long val;
42 asm volatile("rdmsr" : "=A" (val) : "c" (msr));
46 static inline unsigned long long native_read_msr_safe(unsigned int msr,
49 unsigned long long val;
51 asm volatile("2: rdmsr ; xorl %0,%0\n"
53 ".section .fixup,\"ax\"\n\t"
54 "3: movl %3,%0 ; jmp 1b\n\t"
56 ".section __ex_table,\"a\"\n"
60 : "=r" (*err), "=A" (val)
61 : "c" (msr), "i" (-EFAULT));
66 static inline void native_write_msr(unsigned int msr, unsigned long long val)
68 asm volatile("wrmsr" : : "c" (msr), "A"(val));
71 static inline int native_write_msr_safe(unsigned int msr,
72 unsigned long long val)
75 asm volatile("2: wrmsr ; xorl %0,%0\n"
77 ".section .fixup,\"ax\"\n\t"
78 "3: movl %4,%0 ; jmp 1b\n\t"
80 ".section __ex_table,\"a\"\n"
85 : "c" (msr), "0" ((u32)val), "d" ((u32)(val>>32)),
90 static inline unsigned long long native_read_tsc(void)
92 unsigned long long val;
93 asm volatile("rdtsc" : "=A" (val));
97 static inline unsigned long long native_read_pmc(void)
99 unsigned long long val;
100 asm volatile("rdpmc" : "=A" (val));
104 #ifdef CONFIG_PARAVIRT
105 #include <asm/paravirt.h>
107 #include <linux/errno.h>
109 * Access to machine-specific registers (available on 586 and better only)
110 * Note: the rd* operations modify the parameters directly (without using
111 * pointer indirection), this allows gcc to optimize better
114 #define rdmsr(msr,val1,val2) \
116 u64 __val = native_read_msr(msr); \
117 (val1) = (u32)__val; \
118 (val2) = (u32)(__val >> 32); \
121 static inline void wrmsr(u32 __msr, u32 __low, u32 __high)
123 native_write_msr(__msr, ((u64)__high << 32) | __low);
126 #define rdmsrl(msr,val) \
127 ((val) = native_read_msr(msr))
129 #define wrmsrl(msr,val) native_write_msr(msr, val)
131 /* wrmsr with exception handling */
132 static inline int wrmsr_safe(u32 __msr, u32 __low, u32 __high)
134 return native_write_msr_safe(__msr, ((u64)__high << 32) | __low);
137 /* rdmsr with exception handling */
138 #define rdmsr_safe(msr,p1,p2) \
141 u64 __val = native_read_msr_safe(msr, &__err); \
142 (*p1) = (u32)__val; \
143 (*p2) = (u32)(__val >> 32); \
147 #define rdtscl(low) \
148 ((low) = (u32)native_read_tsc())
150 #define rdtscll(val) \
151 ((val) = native_read_tsc())
153 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
155 #define rdpmc(counter,low,high) \
157 u64 _l = native_read_pmc(); \
159 (high) = (u32)(_l >> 32); \
161 #endif /* !CONFIG_PARAVIRT */
163 #endif /* ! __ASSEMBLY__ */
164 #endif /* __KERNEL__ */
169 #include <linux/errno.h>
171 * Access to machine-specific registers (available on 586 and better only)
172 * Note: the rd* operations modify the parameters directly (without using
173 * pointer indirection), this allows gcc to optimize better
176 #define rdmsr(msr,val1,val2) \
177 __asm__ __volatile__("rdmsr" \
178 : "=a" (val1), "=d" (val2) \
182 #define rdmsrl(msr,val) do { unsigned long a__,b__; \
183 __asm__ __volatile__("rdmsr" \
184 : "=a" (a__), "=d" (b__) \
186 val = a__ | (b__<<32); \
189 #define wrmsr(msr,val1,val2) \
190 __asm__ __volatile__("wrmsr" \
192 : "c" (msr), "a" (val1), "d" (val2))
194 #define wrmsrl(msr,val) wrmsr(msr,(__u32)((__u64)(val)),((__u64)(val))>>32)
196 #define rdtsc(low,high) \
197 __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
199 #define rdtscl(low) \
200 __asm__ __volatile__ ("rdtsc" : "=a" (low) : : "edx")
203 #define rdtscll(val) do { \
204 unsigned int __a,__d; \
205 __asm__ __volatile__("rdtsc" : "=a" (__a), "=d" (__d)); \
206 (val) = ((unsigned long)__a) | (((unsigned long)__d)<<32); \
209 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
211 #define write_rdtscp_aux(val) wrmsr(0xc0000103, val, 0)
213 #define rdpmc(counter,low,high) \
214 __asm__ __volatile__("rdpmc" \
215 : "=a" (low), "=d" (high) \
221 /* wrmsr with exception handling */
222 #define wrmsr_safe(msr,a,b) ({ int ret__; \
223 asm volatile("2: wrmsr ; xorl %0,%0\n" \
225 ".section .fixup,\"ax\"\n\t" \
226 "3: movl %4,%0 ; jmp 1b\n\t" \
228 ".section __ex_table,\"a\"\n" \
233 : "c" (msr), "0" (a), "d" (b), "i" (-EFAULT)); \
236 #define checking_wrmsrl(msr,val) wrmsr_safe(msr,(u32)(val),(u32)((val)>>32))
238 #define rdmsr_safe(msr,a,b) \
240 asm volatile ("1: rdmsr\n" \
242 ".section .fixup,\"ax\"\n" \
246 ".section __ex_table,\"a\"\n" \
249 ".previous":"=&bDS" (ret__), "=a"(*(a)), "=d"(*(b)) \
250 :"c"(msr), "i"(-EIO), "0"(0)); \
253 #endif /* __ASSEMBLY__ */
255 #endif /* !__i386__ */
260 void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
261 void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
262 int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
263 int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
264 #else /* CONFIG_SMP */
265 static inline void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
267 rdmsr(msr_no, *l, *h);
269 static inline void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
273 static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
275 return rdmsr_safe(msr_no, l, h);
277 static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
279 return wrmsr_safe(msr_no, l, h);
281 #endif /* CONFIG_SMP */
282 #endif /* __KERNEL__ */
283 #endif /* __ASSEMBLY__ */