2 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
3 * Author: Xing Zheng <zhengxing@rock-chips.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
17 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
19 #define RK3399_TWO_PLL_FOR_VOP
32 /* sclk gates (special clocks) */
48 #define SCLK_SARADC 80
53 #define SCLK_SPDIF_8CH 85
54 #define SCLK_I2S0_8CH 86
55 #define SCLK_I2S1_8CH 87
56 #define SCLK_I2S2_8CH 88
57 #define SCLK_I2S_8CH_OUT 89
58 #define SCLK_TIMER00 90
59 #define SCLK_TIMER01 91
60 #define SCLK_TIMER02 92
61 #define SCLK_TIMER03 93
62 #define SCLK_TIMER04 94
63 #define SCLK_TIMER05 95
64 #define SCLK_TIMER06 96
65 #define SCLK_TIMER07 97
66 #define SCLK_TIMER08 98
67 #define SCLK_TIMER09 99
68 #define SCLK_TIMER10 100
69 #define SCLK_TIMER11 101
70 #define SCLK_MACREF 102
71 #define SCLK_MAC_RX 103
72 #define SCLK_MAC_TX 104
74 #define SCLK_MACREF_OUT 106
75 #define SCLK_VOP0_PWM 107
76 #define SCLK_VOP1_PWM 108
77 #define SCLK_RGA_CORE 109
80 #define SCLK_HDMI_CEC 112
81 #define SCLK_HDMI_SFR 113
82 #define SCLK_DP_CORE 114
83 #define SCLK_PVTM_CORE_L 115
84 #define SCLK_PVTM_CORE_B 116
85 #define SCLK_PVTM_GPU 117
86 #define SCLK_PVTM_DDR 118
87 #define SCLK_MIPIDPHY_REF 119
88 #define SCLK_MIPIDPHY_CFG 120
89 #define SCLK_HSICPHY 121
90 #define SCLK_USBPHY480M 122
91 #define SCLK_USB2PHY0_REF 123
92 #define SCLK_USB2PHY1_REF 124
93 #define SCLK_UPHY0_TCPDPHY_REF 125
94 #define SCLK_UPHY0_TCPDCORE 126
95 #define SCLK_UPHY1_TCPDPHY_REF 127
96 #define SCLK_UPHY1_TCPDCORE 128
97 #define SCLK_USB3OTG0_REF 129
98 #define SCLK_USB3OTG1_REF 130
99 #define SCLK_USB3OTG0_SUSPEND 131
100 #define SCLK_USB3OTG1_SUSPEND 132
101 #define SCLK_CRYPTO0 133
102 #define SCLK_CRYPTO1 134
103 #define SCLK_CCI_TRACE 135
105 #define SCLK_CIF_OUT 137
106 #define SCLK_PCIEPHY_REF 138
107 #define SCLK_PCIE_CORE 139
108 #define SCLK_M0_PERILP 140
109 #define SCLK_M0_PERILP_DEC 141
110 #define SCLK_CM0S 142
111 #define SCLK_DBG_NOC 143
112 #define SCLK_DBG_PD_CORE_B 144
113 #define SCLK_DBG_PD_CORE_L 145
114 #define SCLK_DFIMON0_TIMER 146
115 #define SCLK_DFIMON1_TIMER 147
116 #define SCLK_INTMEM0 148
117 #define SCLK_INTMEM1 149
118 #define SCLK_INTMEM2 150
119 #define SCLK_INTMEM3 151
120 #define SCLK_INTMEM4 152
121 #define SCLK_INTMEM5 153
122 #define SCLK_SDMMC_DRV 154
123 #define SCLK_SDMMC_SAMPLE 155
124 #define SCLK_SDIO_DRV 156
125 #define SCLK_SDIO_SAMPLE 157
126 #define SCLK_VDU_CORE 158
127 #define SCLK_VDU_CA 159
128 #define SCLK_PCIE_PM 160
129 #define SCLK_SPDIF_REC_DPTX 161
130 #define SCLK_DPHY_PLL 162
131 #define SCLK_DPHY_TX0_CFG 163
132 #define SCLK_DPHY_TX1RX1_CFG 164
133 #define SCLK_DPHY_RX0_CFG 165
134 #define SCLK_RMII_SRC 166
135 #define SCLK_PCIEPHY_REF100M 167
136 #define SCLK_USBPHY0_480M_SRC 168
137 #define SCLK_USBPHY1_480M_SRC 169
138 #define SCLK_DDRCLK 170
139 #define SCLK_TESTOUT2 171
140 #define SCLK_UART0_SRC 172
141 #define SCLK_UART_SRC 173
142 #define SCLK_I2S0_DIV 174
143 #define SCLK_I2S1_DIV 175
144 #define SCLK_I2S2_DIV 176
145 #define SCLK_SPDIF_DIV 177
146 #define SCLK_I2S_8CH 178
149 #define DCLK_VOP0 180
150 #define DCLK_VOP1 181
151 #define DCLK_VOP0_DIV 182
152 #define DCLK_VOP1_DIV 183
153 #define DCLK_M0_PERILP 184
155 #define FCLK_CM0S 190
158 #define ACLK_PERIHP 192
159 #define ACLK_PERIHP_NOC 193
160 #define ACLK_PERILP0 194
161 #define ACLK_PERILP0_NOC 195
162 #define ACLK_PERF_PCIE 196
163 #define ACLK_PCIE 197
164 #define ACLK_INTMEM 198
165 #define ACLK_TZMA 199
168 #define ACLK_CCI_NOC0 202
169 #define ACLK_CCI_NOC1 203
170 #define ACLK_CCI_GRF 204
171 #define ACLK_CENTER 205
172 #define ACLK_CENTER_MAIN_NOC 206
173 #define ACLK_CENTER_PERI_NOC 207
175 #define ACLK_PERF_GPU 209
176 #define ACLK_GPU_GRF 210
177 #define ACLK_DMAC0_PERILP 211
178 #define ACLK_DMAC1_PERILP 212
179 #define ACLK_GMAC 213
180 #define ACLK_GMAC_NOC 214
181 #define ACLK_PERF_GMAC 215
182 #define ACLK_VOP0_NOC 216
183 #define ACLK_VOP0 217
184 #define ACLK_VOP1_NOC 218
185 #define ACLK_VOP1 219
187 #define ACLK_RGA_NOC 221
188 #define ACLK_HDCP 222
189 #define ACLK_HDCP_NOC 223
190 #define ACLK_HDCP22 224
192 #define ACLK_IEP_NOC 226
194 #define ACLK_VIO_NOC 228
195 #define ACLK_ISP0 229
196 #define ACLK_ISP1 230
197 #define ACLK_ISP0_NOC 231
198 #define ACLK_ISP1_NOC 232
199 #define ACLK_ISP0_WRAPPER 233
200 #define ACLK_ISP1_WRAPPER 234
201 #define ACLK_VCODEC 235
202 #define ACLK_VCODEC_NOC 236
204 #define ACLK_VDU_NOC 238
205 #define ACLK_PERI 239
206 #define ACLK_EMMC 240
207 #define ACLK_EMMC_CORE 241
208 #define ACLK_EMMC_NOC 242
209 #define ACLK_EMMC_GRF 243
210 #define ACLK_USB3 244
211 #define ACLK_USB3_NOC 245
212 #define ACLK_USB3OTG0 246
213 #define ACLK_USB3OTG1 247
214 #define ACLK_USB3_RKSOC_AXI_PERF 248
215 #define ACLK_USB3_GRF 249
217 #define ACLK_GIC_NOC 251
218 #define ACLK_GIC_ADB400_CORE_L_2_GIC 252
219 #define ACLK_GIC_ADB400_CORE_B_2_GIC 253
220 #define ACLK_GIC_ADB400_GIC_2_CORE_L 254
221 #define ACLK_GIC_ADB400_GIC_2_CORE_B 255
222 #define ACLK_CORE_ADB400_CORE_L_2_CCI500 256
223 #define ACLK_CORE_ADB400_CORE_B_2_CCI500 257
224 #define ACLK_ADB400M_PD_CORE_L 258
225 #define ACLK_ADB400M_PD_CORE_B 259
226 #define ACLK_PERF_CORE_L 260
227 #define ACLK_PERF_CORE_B 261
228 #define ACLK_GIC_PRE 262
229 #define ACLK_VOP0_PRE 263
230 #define ACLK_VOP1_PRE 264
233 #define PCLK_PERIHP 320
234 #define PCLK_PERIHP_NOC 321
235 #define PCLK_PERILP0 322
236 #define PCLK_PERILP1 323
237 #define PCLK_PERILP1_NOC 324
238 #define PCLK_PERILP_SGRF 325
239 #define PCLK_PERIHP_GRF 326
240 #define PCLK_PCIE 327
241 #define PCLK_SGRF 328
242 #define PCLK_INTR_ARB 329
243 #define PCLK_CENTER_MAIN_NOC 330
245 #define PCLK_COREDBG_B 332
246 #define PCLK_COREDBG_L 333
247 #define PCLK_DBG_CXCS_PD_CORE_B 334
249 #define PCLK_GPIO2 336
250 #define PCLK_GPIO3 337
251 #define PCLK_GPIO4 338
253 #define PCLK_HSICPHY 340
254 #define PCLK_I2C1 341
255 #define PCLK_I2C2 342
256 #define PCLK_I2C3 343
257 #define PCLK_I2C5 344
258 #define PCLK_I2C6 345
259 #define PCLK_I2C7 346
260 #define PCLK_SPI0 347
261 #define PCLK_SPI1 348
262 #define PCLK_SPI2 349
263 #define PCLK_SPI4 350
264 #define PCLK_SPI5 351
265 #define PCLK_UART0 352
266 #define PCLK_UART1 353
267 #define PCLK_UART2 354
268 #define PCLK_UART3 355
269 #define PCLK_TSADC 356
270 #define PCLK_SARADC 357
271 #define PCLK_GMAC 358
272 #define PCLK_GMAC_NOC 359
273 #define PCLK_TIMER0 360
274 #define PCLK_TIMER1 361
276 #define PCLK_EDP_NOC 363
277 #define PCLK_EDP_CTRL 364
279 #define PCLK_VIO_NOC 366
280 #define PCLK_VIO_GRF 367
281 #define PCLK_MIPI_DSI0 368
282 #define PCLK_MIPI_DSI1 369
283 #define PCLK_HDCP 370
284 #define PCLK_HDCP_NOC 371
285 #define PCLK_HDMI_CTRL 372
286 #define PCLK_DP_CTRL 373
287 #define PCLK_HDCP22 374
288 #define PCLK_GASKET 375
290 #define PCLK_DDR_MON 377
291 #define PCLK_DDR_SGRF 378
292 #define PCLK_ISP1_WRAPPER 379
294 #define PCLK_EFUSE1024NS 381
295 #define PCLK_EFUSE1024S 382
296 #define PCLK_PMU_INTR_ARB 383
297 #define PCLK_MAILBOX0 384
298 #define PCLK_USBPHY_MUX_G 385
299 #define PCLK_UPHY0_TCPHY_G 386
300 #define PCLK_UPHY0_TCPD_G 387
301 #define PCLK_UPHY1_TCPHY_G 388
302 #define PCLK_UPHY1_TCPD_G 389
303 #define PCLK_ALIVE 390
306 #define HCLK_PERIHP 448
307 #define HCLK_PERILP0 449
308 #define HCLK_PERILP1 450
309 #define HCLK_PERILP0_NOC 451
310 #define HCLK_PERILP1_NOC 452
311 #define HCLK_M0_PERILP 453
312 #define HCLK_M0_PERILP_NOC 454
313 #define HCLK_AHB1TOM 455
314 #define HCLK_HOST0 456
315 #define HCLK_HOST0_ARB 457
316 #define HCLK_HOST1 458
317 #define HCLK_HOST1_ARB 459
318 #define HCLK_HSIC 460
320 #define HCLK_SDMMC 462
321 #define HCLK_SDMMC_NOC 463
322 #define HCLK_M_CRYPTO0 464
323 #define HCLK_M_CRYPTO1 465
324 #define HCLK_S_CRYPTO0 466
325 #define HCLK_S_CRYPTO1 467
326 #define HCLK_I2S0_8CH 468
327 #define HCLK_I2S1_8CH 469
328 #define HCLK_I2S2_8CH 470
329 #define HCLK_SPDIF 471
330 #define HCLK_VOP0_NOC 472
331 #define HCLK_VOP0 473
332 #define HCLK_VOP1_NOC 474
333 #define HCLK_VOP1 475
336 #define HCLK_IEP_NOC 478
337 #define HCLK_ISP0 479
338 #define HCLK_ISP1 480
339 #define HCLK_ISP0_NOC 481
340 #define HCLK_ISP1_NOC 482
341 #define HCLK_ISP0_WRAPPER 483
342 #define HCLK_ISP1_WRAPPER 484
344 #define HCLK_RGA_NOC 486
345 #define HCLK_HDCP 487
346 #define HCLK_HDCP_NOC 488
347 #define HCLK_HDCP22 489
348 #define HCLK_VCODEC 490
349 #define HCLK_VCODEC_NOC 491
351 #define HCLK_VDU_NOC 493
352 #define HCLK_SDIO 494
353 #define HCLK_SDIO_NOC 495
354 #define HCLK_SDIOAUDIO_NOC 496
356 #define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1)
358 /* pmu-clocks indices */
362 #define SCLK_32K_SUSPEND_PMU 2
363 #define SCLK_SPI3_PMU 3
364 #define SCLK_TIMER12_PMU 4
365 #define SCLK_TIMER13_PMU 5
366 #define SCLK_UART4_PMU 6
367 #define SCLK_PVTM_PMU 7
368 #define SCLK_WIFI_PMU 8
369 #define SCLK_I2C0_PMU 9
370 #define SCLK_I2C4_PMU 10
371 #define SCLK_I2C8_PMU 11
373 #define PCLK_SRC_PMU 19
375 #define PCLK_PMUGRF_PMU 21
376 #define PCLK_INTMEM1_PMU 22
377 #define PCLK_GPIO0_PMU 23
378 #define PCLK_GPIO1_PMU 24
379 #define PCLK_SGRF_PMU 25
380 #define PCLK_NOC_PMU 26
381 #define PCLK_I2C0_PMU 27
382 #define PCLK_I2C4_PMU 28
383 #define PCLK_I2C8_PMU 29
384 #define PCLK_RKPWM_PMU 30
385 #define PCLK_SPI3_PMU 31
386 #define PCLK_TIMER_PMU 32
387 #define PCLK_MAILBOX_PMU 33
388 #define PCLK_UART4_PMU 34
389 #define PCLK_WDT_M0_PMU 35
391 #define FCLK_CM0S_SRC_PMU 44
392 #define FCLK_CM0S_PMU 45
393 #define SCLK_CM0S_PMU 46
394 #define HCLK_CM0S_PMU 47
395 #define DCLK_CM0S_PMU 48
396 #define PCLK_INTR_ARB_PMU 49
397 #define HCLK_NOC_PMU 50
399 #define CLKPMU_NR_CLKS (HCLK_NOC_PMU + 1)
401 /* soft-reset indices */
403 /* cru_softrst_con0 */
404 #define SRST_CORE_L0 0
405 #define SRST_CORE_B0 1
406 #define SRST_CORE_PO_L0 2
407 #define SRST_CORE_PO_B0 3
413 #define SRST_A_CCIM0_NOC 9
414 #define SRST_A_CCIM1_NOC 10
415 #define SRST_DBG_NOC 11
417 /* cru_softrst_con1 */
418 #define SRST_CORE_L0_T 16
419 #define SRST_CORE_L1 17
420 #define SRST_CORE_L2 18
421 #define SRST_CORE_L3 19
422 #define SRST_CORE_PO_L0_T 20
423 #define SRST_CORE_PO_L1 21
424 #define SRST_CORE_PO_L2 22
425 #define SRST_CORE_PO_L3 23
426 #define SRST_A_ADB400_GIC2COREL 24
427 #define SRST_A_ADB400_COREL2GIC 25
428 #define SRST_P_DBG_L 26
429 #define SRST_L2_L_T 28
430 #define SRST_ADB_L_T 29
431 #define SRST_A_RKPERF_L 30
432 #define SRST_PVTM_CORE_L 31
434 /* cru_softrst_con2 */
435 #define SRST_CORE_B0_T 32
436 #define SRST_CORE_B1 33
437 #define SRST_CORE_PO_B0_T 36
438 #define SRST_CORE_PO_B1 37
439 #define SRST_A_ADB400_GIC2COREB 40
440 #define SRST_A_ADB400_COREB2GIC 41
441 #define SRST_P_DBG_B 42
442 #define SRST_L2_B_T 43
443 #define SRST_ADB_B_T 45
444 #define SRST_A_RKPERF_B 46
445 #define SRST_PVTM_CORE_B 47
447 /* cru_softrst_con3 */
448 #define SRST_A_CCI_T 50
449 #define SRST_A_CCIM0_NOC_T 51
450 #define SRST_A_CCIM1_NOC_T 52
451 #define SRST_A_ADB400M_PD_CORE_B_T 53
452 #define SRST_A_ADB400M_PD_CORE_L_T 54
453 #define SRST_DBG_NOC_T 55
454 #define SRST_DBG_CXCS 56
455 #define SRST_CCI_TRACE 57
456 #define SRST_P_CCI_GRF 58
458 /* cru_softrst_con4 */
459 #define SRST_A_CENTER_MAIN_NOC 64
460 #define SRST_A_CENTER_PERI_NOC 65
461 #define SRST_P_CENTER_MAIN 66
462 #define SRST_P_DDRMON 67
463 #define SRST_P_CIC 68
464 #define SRST_P_CENTER_SGRF 69
465 #define SRST_DDR0_MSCH 70
466 #define SRST_DDRCFG0_MSCH 71
468 #define SRST_DDRPHY0 73
469 #define SRST_DDR1_MSCH 74
470 #define SRST_DDRCFG1_MSCH 75
472 #define SRST_DDRPHY1 77
473 #define SRST_DDR_CIC 78
474 #define SRST_PVTM_DDR 79
476 /* cru_softrst_con5 */
477 #define SRST_A_VCODEC_NOC 80
478 #define SRST_A_VCODEC 81
479 #define SRST_H_VCODEC_NOC 82
480 #define SRST_H_VCODEC 83
481 #define SRST_A_VDU_NOC 88
482 #define SRST_A_VDU 89
483 #define SRST_H_VDU_NOC 90
484 #define SRST_H_VDU 91
485 #define SRST_VDU_CORE 92
486 #define SRST_VDU_CA 93
488 /* cru_softrst_con6 */
489 #define SRST_A_IEP_NOC 96
490 #define SRST_A_VOP_IEP 97
491 #define SRST_A_IEP 98
492 #define SRST_H_IEP_NOC 99
493 #define SRST_H_IEP 100
494 #define SRST_A_RGA_NOC 102
495 #define SRST_A_RGA 103
496 #define SRST_H_RGA_NOC 104
497 #define SRST_H_RGA 105
498 #define SRST_RGA_CORE 106
499 #define SRST_EMMC_NOC 108
500 #define SRST_EMMC 109
501 #define SRST_EMMC_GRF 110
503 /* cru_softrst_con7 */
504 #define SRST_A_PERIHP_NOC 112
505 #define SRST_P_PERIHP_GRF 113
506 #define SRST_H_PERIHP_NOC 114
507 #define SRST_USBHOST0 115
508 #define SRST_HOSTC0_AUX 116
509 #define SRST_HOST0_ARB 117
510 #define SRST_USBHOST1 118
511 #define SRST_HOSTC1_AUX 119
512 #define SRST_HOST1_ARB 120
513 #define SRST_SDIO0 121
514 #define SRST_SDMMC 122
515 #define SRST_HSIC 123
516 #define SRST_HSIC_AUX 124
517 #define SRST_AHB1TOM 125
518 #define SRST_P_PERIHP_NOC 126
519 #define SRST_HSICPHY 127
521 /* cru_softrst_con8 */
522 #define SRST_A_PCIE 128
523 #define SRST_P_PCIE 129
524 #define SRST_PCIE_CORE 130
525 #define SRST_PCIE_MGMT 131
526 #define SRST_PCIE_MGMT_STICKY 132
527 #define SRST_PCIE_PIPE 133
528 #define SRST_PCIE_PM 134
529 #define SRST_PCIEPHY 135
530 #define SRST_A_GMAC_NOC 136
531 #define SRST_A_GMAC 137
532 #define SRST_P_GMAC_NOC 138
533 #define SRST_P_GMAC_GRF 140
534 #define SRST_HSICPHY_POR 142
535 #define SRST_HSICPHY_UTMI 143
537 /* cru_softrst_con9 */
538 #define SRST_USB2PHY0_POR 144
539 #define SRST_USB2PHY0_UTMI_PORT0 145
540 #define SRST_USB2PHY0_UTMI_PORT1 146
541 #define SRST_USB2PHY0_EHCIPHY 147
542 #define SRST_UPHY0_PIPE_L00 148
543 #define SRST_UPHY0 149
544 #define SRST_UPHY0_TCPDPWRUP 150
545 #define SRST_USB2PHY1_POR 152
546 #define SRST_USB2PHY1_UTMI_PORT0 153
547 #define SRST_USB2PHY1_UTMI_PORT1 154
548 #define SRST_USB2PHY1_EHCIPHY 155
549 #define SRST_UPHY1_PIPE_L00 156
550 #define SRST_UPHY1 157
551 #define SRST_UPHY1_TCPDPWRUP 158
553 /* cru_softrst_con10 */
554 #define SRST_A_PERILP0_NOC 160
555 #define SRST_A_DCF 161
556 #define SRST_GIC500 162
557 #define SRST_DMAC0_PERILP0 163
558 #define SRST_DMAC1_PERILP0 164
559 #define SRST_TZMA 165
560 #define SRST_INTMEM 166
561 #define SRST_ADB400_MST0 167
562 #define SRST_ADB400_MST1 168
563 #define SRST_ADB400_SLV0 169
564 #define SRST_ADB400_SLV1 170
565 #define SRST_H_PERILP0 171
566 #define SRST_H_PERILP0_NOC 172
568 #define SRST_CRYPTO_S 174
569 #define SRST_CRYPTO_M 175
571 /* cru_softrst_con11 */
572 #define SRST_P_DCF 176
573 #define SRST_CM0S_NOC 177
574 #define SRST_CM0S 178
575 #define SRST_CM0S_DBG 179
576 #define SRST_CM0S_PO 180
577 #define SRST_CRYPTO 181
578 #define SRST_P_PERILP1_SGRF 182
579 #define SRST_P_PERILP1_GRF 183
580 #define SRST_CRYPTO1_S 184
581 #define SRST_CRYPTO1_M 185
582 #define SRST_CRYPTO1 186
583 #define SRST_GIC_NOC 188
584 #define SRST_SD_NOC 189
585 #define SRST_SDIOAUDIO_BRG 190
587 /* cru_softrst_con12 */
588 #define SRST_H_PERILP1 192
589 #define SRST_H_PERILP1_NOC 193
590 #define SRST_H_I2S0_8CH 194
591 #define SRST_H_I2S1_8CH 195
592 #define SRST_H_I2S2_8CH 196
593 #define SRST_H_SPDIF_8CH 197
594 #define SRST_P_PERILP1_NOC 198
595 #define SRST_P_EFUSE_1024 199
596 #define SRST_P_EFUSE_1024S 200
597 #define SRST_P_I2C0 201
598 #define SRST_P_I2C1 202
599 #define SRST_P_I2C2 203
600 #define SRST_P_I2C3 204
601 #define SRST_P_I2C4 205
602 #define SRST_P_I2C5 206
603 #define SRST_P_MAILBOX0 207
605 /* cru_softrst_con13 */
606 #define SRST_P_UART0 208
607 #define SRST_P_UART1 209
608 #define SRST_P_UART2 210
609 #define SRST_P_UART3 211
610 #define SRST_P_SARADC 212
611 #define SRST_P_TSADC 213
612 #define SRST_P_SPI0 214
613 #define SRST_P_SPI1 215
614 #define SRST_P_SPI2 216
615 #define SRST_P_SPI4 217
616 #define SRST_P_SPI5 218
617 #define SRST_SPI0 219
618 #define SRST_SPI1 220
619 #define SRST_SPI2 221
620 #define SRST_SPI4 222
621 #define SRST_SPI5 223
623 /* cru_softrst_con14 */
624 #define SRST_I2S0_8CH 224
625 #define SRST_I2S1_8CH 225
626 #define SRST_I2S2_8CH 226
627 #define SRST_SPDIF_8CH 227
628 #define SRST_UART0 228
629 #define SRST_UART1 229
630 #define SRST_UART2 230
631 #define SRST_UART3 231
632 #define SRST_TSADC 232
633 #define SRST_I2C0 233
634 #define SRST_I2C1 234
635 #define SRST_I2C2 235
636 #define SRST_I2C3 236
637 #define SRST_I2C4 237
638 #define SRST_I2C5 238
639 #define SRST_SDIOAUDIO_NOC 239
641 /* cru_softrst_con15 */
642 #define SRST_A_VIO_NOC 240
643 #define SRST_A_HDCP_NOC 241
644 #define SRST_A_HDCP 242
645 #define SRST_H_HDCP_NOC 243
646 #define SRST_H_HDCP 244
647 #define SRST_P_HDCP_NOC 245
648 #define SRST_P_HDCP 246
649 #define SRST_P_HDMI_CTRL 247
650 #define SRST_P_DP_CTRL 248
651 #define SRST_S_DP_CTRL 249
652 #define SRST_C_DP_CTRL 250
653 #define SRST_P_MIPI_DSI0 251
654 #define SRST_P_MIPI_DSI1 252
655 #define SRST_DP_CORE 253
656 #define SRST_DP_I2S 254
658 /* cru_softrst_con16 */
659 #define SRST_GASKET 256
660 #define SRST_VIO_GRF 258
661 #define SRST_DPTX_SPDIF_REC 259
662 #define SRST_HDMI_CTRL 260
663 #define SRST_HDCP_CTRL 261
664 #define SRST_A_ISP0_NOC 262
665 #define SRST_A_ISP1_NOC 263
666 #define SRST_H_ISP0_NOC 266
667 #define SRST_H_ISP1_NOC 267
668 #define SRST_H_ISP0 268
669 #define SRST_H_ISP1 269
670 #define SRST_ISP0 270
671 #define SRST_ISP1 271
673 /* cru_softrst_con17 */
674 #define SRST_A_VOP0_NOC 272
675 #define SRST_A_VOP1_NOC 273
676 #define SRST_A_VOP0 274
677 #define SRST_A_VOP1 275
678 #define SRST_H_VOP0_NOC 276
679 #define SRST_H_VOP1_NOC 277
680 #define SRST_H_VOP0 278
681 #define SRST_H_VOP1 279
682 #define SRST_D_VOP0 280
683 #define SRST_D_VOP1 281
684 #define SRST_VOP0_PWM 282
685 #define SRST_VOP1_PWM 283
686 #define SRST_P_EDP_NOC 284
687 #define SRST_P_EDP_CTRL 285
689 /* cru_softrst_con18 */
690 #define SRST_A_GPU 288
691 #define SRST_A_GPU_NOC 289
692 #define SRST_A_GPU_GRF 290
693 #define SRST_PVTM_GPU 291
694 #define SRST_A_USB3_NOC 292
695 #define SRST_A_USB3_OTG0 293
696 #define SRST_A_USB3_OTG1 294
697 #define SRST_A_USB3_GRF 295
700 /* cru_softrst_con19 */
701 #define SRST_P_TIMER0_5 304
702 #define SRST_TIMER0 305
703 #define SRST_TIMER1 306
704 #define SRST_TIMER2 307
705 #define SRST_TIMER3 308
706 #define SRST_TIMER4 309
707 #define SRST_TIMER5 310
708 #define SRST_P_TIMER6_11 311
709 #define SRST_TIMER6 312
710 #define SRST_TIMER7 313
711 #define SRST_TIMER8 314
712 #define SRST_TIMER9 315
713 #define SRST_TIMER10 316
714 #define SRST_TIMER11 317
715 #define SRST_P_INTR_ARB_PMU 318
716 #define SRST_P_ALIVE_SGRF 319
718 /* cru_softrst_con20 */
719 #define SRST_P_GPIO2 320
720 #define SRST_P_GPIO3 321
721 #define SRST_P_GPIO4 322
722 #define SRST_P_GRF 323
723 #define SRST_P_ALIVE_NOC 324
724 #define SRST_P_WDT0 325
725 #define SRST_P_WDT1 326
726 #define SRST_P_INTR_ARB 327
727 #define SRST_P_UPHY0_DPTX 328
728 #define SRST_P_UPHY0_APB 330
729 #define SRST_P_UPHY0_TCPHY 332
730 #define SRST_P_UPHY1_TCPHY 333
731 #define SRST_P_UPHY0_TCPDCTRL 334
732 #define SRST_P_UPHY1_TCPDCTRL 335
734 /* pmu soft-reset indices */
736 /* pmu_cru_softrst_con0 */
738 #define SRST_P_INTMEM 1
739 #define SRST_H_CM0S 2
740 #define SRST_H_CM0S_NOC 3
741 #define SRST_DBG_CM0S 4
742 #define SRST_PO_CM0S 5
743 #define SRST_P_SPI3 6
745 #define SRST_P_TIMER_0_1 8
746 #define SRST_P_TIMER_0 9
747 #define SRST_P_TIMER_1 10
748 #define SRST_P_UART4 11
749 #define SRST_UART4 12
750 #define SRST_P_WDT 13
752 /* pmu_cru_softrst_con1 */
753 #define SRST_P_I2C6 16
754 #define SRST_P_I2C7 17
755 #define SRST_P_I2C8 18
756 #define SRST_P_MAILBOX 19
757 #define SRST_P_RKPWM 20
758 #define SRST_P_PMUGRF 21
759 #define SRST_P_SGRF 22
760 #define SRST_P_GPIO0 23
761 #define SRST_P_GPIO1 24
762 #define SRST_P_CRU 25
763 #define SRST_P_INTR 26