2 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
3 * Author: Xing Zheng <zhengxing@rock-chips.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
17 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
31 /* sclk gates (special clocks) */
47 #define SCLK_SARADC 80
52 #define SCLK_SPDIF_8CH 85
53 #define SCLK_I2S0_8CH 86
54 #define SCLK_I2S1_8CH 87
55 #define SCLK_I2S2_8CH 88
56 #define SCLK_I2S_8CH_OUT 89
57 #define SCLK_TIMER00 90
58 #define SCLK_TIMER01 91
59 #define SCLK_TIMER02 92
60 #define SCLK_TIMER03 93
61 #define SCLK_TIMER04 94
62 #define SCLK_TIMER05 95
63 #define SCLK_TIMER06 96
64 #define SCLK_TIMER07 97
65 #define SCLK_TIMER08 98
66 #define SCLK_TIMER09 99
67 #define SCLK_TIMER10 100
68 #define SCLK_TIMER11 101
69 #define SCLK_MACREF 102
70 #define SCLK_MAC_RX 103
71 #define SCLK_MAC_TX 104
73 #define SCLK_MACREF_OUT 106
74 #define SCLK_VOP0_PWM 107
75 #define SCLK_VOP1_PWM 108
79 #define SCLK_HDMI_CEC 112
80 #define SCLK_HDMI_SFR 113
81 #define SCLK_DP_CORE_SRC 114
82 #define SCLK_PVTM_CORE_L 115
83 #define SCLK_PVTM_CORE_B 116
84 #define SCLK_PVTM_GPU 117
85 #define SCLK_PVTM_DDR 118
86 #define SCLK_MIPIDPHY_REF 119
87 #define SCLK_MIPIDPHY_CFG 120
88 #define SCLK_HSICPHY 121
89 #define SCLK_USBPHY480M 122
90 #define SCLK_USB2PHY0_REF 123
91 #define SCLK_USB2PHY1_REF 124
92 #define SCLK_UPHY0_TCPDPHY_REF 125
93 #define SCLK_UPHY0_TCPDCORE 126
94 #define SCLK_UPHY1_TCPDPHY_REF 127
95 #define SCLK_UPHY1_TCPDCORE 128
96 #define SCLK_USB3OTG0_REF 129
97 #define SCLK_USB3OTG1_REF 130
98 #define SCLK_USB3OTG0_SUSPEND 131
99 #define SCLK_USB3OTG1_SUSPEND 132
100 #define SCLK_CRYPTO0 133
101 #define SCLK_CRYPTO1 134
102 #define SCLK_CCI_TRACE 135
104 #define SCLK_CIF_OUT 137
105 #define SCLK_PCIEPHY_REF 138
106 #define SCLK_PCIE_CORE 139
107 #define SCLK_MO_PERILP 140
108 #define SCLK_M0_PERILP_DEC 141
109 #define SCLK_CM0S 142
110 #define SCLK_DBG_NOC 143
111 #define SCLK_DBG_PD_CORE_B 144
112 #define SCLK_DBG_PD_CORE_L 145
113 #define SCLK_DFIMON0_TIMER 146
114 #define SCLK_DFIMON1_TIMER 147
115 #define SCLK_INTMEM0 148
116 #define SCLK_INTMEM1 149
117 #define SCLK_INTMEM2 150
118 #define SCLK_INTMEM3 151
119 #define SCLK_INTMEM4 152
120 #define SCLK_INTMEM5 153
122 #define DCLK_VOP0 170
123 #define DCLK_VOP1 171
126 #define ACLK_PERIHP 192
127 #define ACLK_PERIHP_NOC 193
128 #define ACLK_PERILP0 194
129 #define ACLK_PERILP0_NOC 195
130 #define ACLK_PERF_PCIE 196
131 #define ACLK_PCIE 197
132 #define ACLK_INTMEM 198
133 #define ACLK_TZMA 199
136 #define ACLK_CCI_NOC0 202
137 #define ACLK_CCI_NOC1 203
138 #define ACLK_CCI_GRF 204
139 #define ACLK_CENTER 205
140 #define ACLK_CENTER_MAIN_NOC 206
141 #define ACLK_CENTER_PERI_NOC 207
143 #define ACLK_PERF_GPU 209
144 #define ACLK_GPU_GRF 210
145 #define ACLK_DMAC0_PERILP 211
146 #define ACLK_DMAC1_PERILP 212
147 #define ACLK_GMAC 213
148 #define ACLK_GMAC_NOC 214
149 #define ACLK_PERF_GMAC 215
150 #define ACLK_VOP0_NOC 216
151 #define ACLK_VOP0 217
152 #define ACLK_VOP1_NOC 218
153 #define ACLK_VOP1 219
155 #define ACLK_RGA_NOC 221
156 #define ACLK_HDCP 222
157 #define ACLK_HDCP_NOC 223
158 #define ACLK_HDCP22 224
160 #define ACLK_IEP_NOC 226
162 #define ACLK_VIO_NOC 228
163 #define ACLK_ISP0 229
164 #define ACLK_ISP1 230
165 #define ACLK_ISP0_NOC 231
166 #define ACLK_ISP1_NOC 232
167 #define ACLK_ISP0_WRAPPER 233
168 #define ACLK_ISP1_WRAPPER 234
169 #define ACLK_VCODEC 235
170 #define ACLK_VCODEC_NOC 236
172 #define ACLK_VDU_NOC 238
173 #define ACLK_PERI 239
174 #define ACLK_EMMC 240
175 #define ACLK_EMMC_CORE 241
176 #define ACLK_EMMC_NOC 242
177 #define ACLK_EMMC_GRF 243
178 #define ACLK_USB3 244
179 #define ACLK_USB3_NOC 245
180 #define ACLK_USB3OTG0 246
181 #define ACLK_USB3OTG1 247
182 #define ACLK_USB3_RKSOC_AXI_PERF 248
183 #define ACLK_USB3_GRF 249
185 #define ACLK_GIC_NOC 251
186 #define ACLK_GIC_ADB400_CORE_L_2_GIC 252
187 #define ACLK_GIC_ADB400_CORE_B_2_GIC 253
188 #define ACLK_GIC_ADB400_GIC_2_CORE_L 254
189 #define ACLK_GIC_ADB400_GIC_2_CORE_B 255
192 #define PCLK_PERIHP 320
193 #define PCLK_PERIHP_NOC 321
194 #define PCLK_PERILP0 322
195 #define PCLK_PERILP1 323
196 #define PCLK_PERILP1_NOC 324
197 #define PCLK_PERILP_SGRF 325
198 #define PCLK_PERIHP_GRF 326
199 #define PCLK_PCIE 327
200 #define PCLK_SGRF 328
201 #define PCLK_INTR_ARB 329
202 #define PCLK_CENTER_MAIN_NOC 330
204 #define PCLK_COREDBG_B 332
205 #define PCLK_COREDBG_L 333
206 #define PCLK_DBG_CXCS_PD_CORE_B 334
208 #define PCLK_GPIO2 336
209 #define PCLK_GPIO3 337
210 #define PCLK_GPIO4 338
212 #define PCLK_HSICPHY 340
213 #define PCLK_I2C1 341
214 #define PCLK_I2C2 342
215 #define PCLK_I2C3 343
216 #define PCLK_I2C5 344
217 #define PCLK_I2C6 345
218 #define PCLK_I2C7 346
219 #define PCLK_SPI0 347
220 #define PCLK_SPI1 348
221 #define PCLK_SPI2 349
222 #define PCLK_SPI4 350
223 #define PCLK_SPI5 351
224 #define PCLK_UART0 352
225 #define PCLK_UART1 353
226 #define PCLK_UART2 354
227 #define PCLK_UART3 355
228 #define PCLK_TSADC 356
229 #define PCLK_SARADC 357
230 #define PCLK_GMAC 358
231 #define PCLK_GMAC_NOC 359
232 #define PCLK_TIMER0 360
233 #define PCLK_TIMER1 361
235 #define PCLK_EDP_NOC 363
236 #define PCLK_EDP_CTRL 364
238 #define PCLK_VIO_NOC 366
239 #define PCLK_VIO_GRF 367
240 #define PCLK_MIPI_DSI0 368
241 #define PCLK_MIPI_DSI1 369
242 #define PCLK_HDCP 370
243 #define PCLK_HDCP_NOC 371
244 #define PCLK_HDMI_CTRL 372
245 #define PCLK_DP_CTRL 373
246 #define PCLK_HDCP22 374
247 #define PCLK_GASKET 375
249 #define PCLK_DDR_MON 377
250 #define PCLK_DDR_SGRF 378
251 #define PCLK_ISP1_WRAPPER 379
253 #define PCLK_EFUSE1024NS 381
254 #define PCLK_EFUSE1024S 382
255 #define PCLK_PMU_INTR_ARB 383
256 #define PCLK_MAILBOX0 384
259 #define HCLK_PERIHP 448
260 #define HCLK_PERILP0 449
261 #define HCLK_PERILP1 450
262 #define HCLK_PERILP0_NOC 451
263 #define HCLK_PERILP1_NOC 452
264 #define HCLK_M0_PERILP 453
265 #define HCLK_M0_PERILP_NOC 454
266 #define HCLK_AHB1TOM 455
267 #define HCLK_HOST0 456
268 #define HCLK_HOST0_ARB 457
269 #define HCLK_HOST1 458
270 #define HCLK_HOST1_ARB 459
271 #define HCLK_HSIC 460
273 #define HCLK_SDMMC 462
274 #define HCLK_SDMMC_NOC 463
275 #define HCLK_M_CRYPTO0 464
276 #define HCLK_M_CRYPTO1 465
277 #define HCLK_S_CRYPTO0 466
278 #define HCLK_S_CRYPTO1 467
279 #define HCLK_I2S0_8CH 468
280 #define HCLK_I2S1_8CH 469
281 #define HCLK_I2S2_8CH 470
282 #define HCLK_SPDIF 471
283 #define HCLK_VOP0_NOC 472
284 #define HCLK_VOP0 473
285 #define HCLK_VOP1_NOC 474
286 #define HCLK_VOP1 475
289 #define HCLK_IEP_NOC 478
290 #define HCLK_ISP0 479
291 #define HCLK_ISP1 480
292 #define HCLK_ISP0_NOC 481
293 #define HCLK_ISP1_NOC 482
294 #define HCLK_ISP0_WRAPPER 483
295 #define HCLK_ISP1_WRAPPER 484
297 #define HCLK_RGA_NOC 486
298 #define HCLK_HDCP 487
299 #define HCLK_HDCP_NOC 488
300 #define HCLK_HDCP22 489
301 #define HCLK_VCODEC 490
302 #define HCLK_VCODEC_NOC 491
304 #define HCLK_VDU_NOC 493
305 #define HCLK_SDIO 494
306 #define HCLK_SDIO_NOC 495
307 #define HCLK_SDIOAUDIO_NOC 496
309 #define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1)
311 /* pmu-clocks indices */
312 #define SCLK_32K_SUSPEND_PMU 521
313 #define SCLK_SPI3_PMU 522
314 #define SCLK_TIMER12_PMU 523
315 #define SCLK_TIMER13_PMU 524
316 #define SCLK_UART4_PMU 525
317 #define SCLK_PVTM_PMU 526
318 #define SCLK_WIFI_PMU 527
319 #define SCLK_I2C0_PMU 528
320 #define SCLK_I2C4_PMU 529
321 #define SCLK_I2C8_PMU 530
324 #define PCLK_PMUGRF_PMU 541
325 #define PCLK_INTMEM1_PMU 542
326 #define PCLK_GPIO0_PMU 543
327 #define PCLK_GPIO1_PMU 544
328 #define PCLK_SGRF_PMU 545
329 #define PCLK_NOC_PMU 546
330 #define PCLK_I2C0_PMU 547
331 #define PCLK_I2C4_PMU 548
332 #define PCLK_I2C8_PMU 549
333 #define PCLK_RKPWM_PMU 550
334 #define PCLK_SPI3_PMU 551
335 #define PCLK_TIMER_PMU 552
336 #define PCLK_MAILBOX_PMU 553
337 #define PCLK_UART4_PMU 554
338 #define PCLK_WDT_M0_PMU 555
340 #define FCLK_CM0S_PMU 560
341 #define SCLK_CM0S_PMU 561
342 #define HCLK_CM0S_PMU 562
343 #define DCLK_CM0S_PMU 563
344 #define PCLK_INTR_ARB_PMU 564
345 #define HCLK_NOC_PMU 565
347 #define CLKPMU_NR_CLKS (HCLK_NOC_PMU - SCLK_32K_SUSPEND_PMU + 1)
349 /* soft-reset indices */
351 /* cru_softrst_con0 */
352 #define SRST_CORE_L0 0
353 #define SRST_CORE_B0 1
354 #define SRST_CORE_PO_L0 2
355 #define SRST_CORE_PO_B0 3
361 #define SRST_A_CCIM0_NOC 9
362 #define SRST_A_CCIM1_NOC 10
363 #define SRST_DBG_NOC 11
365 /* cru_softrst_con1 */
366 #define SRST_CORE_L0_T 16
367 #define SRST_CORE_L1 17
368 #define SRST_CORE_L2 18
369 #define SRST_CORE_L3 19
370 #define SRST_CORE_PO_L0_T 20
371 #define SRST_CORE_PO_L1 21
372 #define SRST_CORE_PO_L2 22
373 #define SRST_CORE_PO_L3 23
374 #define SRST_A_ADB400_GIC2COREL 24
375 #define SRST_A_ADB400_COREL2GIC 25
376 #define SRST_P_DBG_L 26
377 #define SRST_L2_L_T 28
378 #define SRST_ADB_L_T 29
379 #define SRST_A_RKPERF_L 30
380 #define SRST_PVTM_CORE_L 31
382 /* cru_softrst_con2 */
383 #define SRST_CORE_B0_T 32
384 #define SRST_CORE_B1 33
385 #define SRST_CORE_PO_B0_T 36
386 #define SRST_CORE_PO_B1 37
387 #define SRST_A_ADB400_GIC2COREB 40
388 #define SRST_A_ADB400_COREB2GIC 41
389 #define SRST_P_DBG_B 42
390 #define SRST_L2_B_T 43
391 #define SRST_ADB_B_T 45
392 #define SRST_A_RKPERF_B 46
393 #define SRST_PVTM_CORE_B 47
395 /* cru_softrst_con3 */
396 #define SRST_A_CCI_T 50
397 #define SRST_A_CCIM0_NOC_T 51
398 #define SRST_A_CCIM1_NOC_T 52
399 #define SRST_A_ADB400M_PD_CORE_B_T 53
400 #define SRST_A_ADB400M_PD_CORE_L_T 54
401 #define SRST_DBG_NOC_T 55
402 #define SRST_DBG_CXCS 56
403 #define SRST_CCI_TRACE 57
404 #define SRST_P_CCI_GRF 58
406 /* cru_softrst_con4 */
407 #define SRST_A_CENTER_MAIN_NOC 64
408 #define SRST_A_CENTER_PERI_NOC 65
409 #define SRST_P_CENTER_MAIN 66
410 #define SRST_P_DDRMON 67
411 #define SRST_P_CIC 68
412 #define SRST_P_CENTER_SGRF 69
413 #define SRST_DDR0_MSCH 70
414 #define SRST_DDRCFG0_MSCH 71
416 #define SRST_DDRPHY0 73
417 #define SRST_DDR1_MSCH 74
418 #define SRST_DDRCFG1_MSCH 75
420 #define SRST_DDRPHY1 77
421 #define SRST_DDR_CIC 78
422 #define SRST_PVTM_DDR 79
424 /* cru_softrst_con5 */
425 #define SRST_A_VCODEC_NOC 80
426 #define SRST_A_VCODEC 81
427 #define SRST_H_VCODEC_NOC 82
428 #define SRST_H_VCODEC 83
429 #define SRST_A_VDU_NOC 88
430 #define SRST_A_VDU 89
431 #define SRST_H_VDU_NOC 90
432 #define SRST_H_VDU 91
433 #define SRST_VDU_CORE 92
434 #define SRST_VDU_CA 93
436 /* cru_softrst_con6 */
437 #define SRST_A_IEP_NOC 96
438 #define SRST_A_VOP_IEP 97
439 #define SRST_A_IEP 98
440 #define SRST_H_IEP_NOC 99
441 #define SRST_H_IEP 100
442 #define SRST_A_RGA_NOC 102
443 #define SRST_A_RGA 103
444 #define SRST_H_RGA_NOC 104
445 #define SRST_H_RGA 105
446 #define SRST_RGA_CORE 106
447 #define SRST_EMMC_NOC 108
448 #define SRST_EMMC 109
449 #define SRST_EMMC_GRF 110
451 /* cru_softrst_con7 */
452 #define SRST_A_PERIHP_NOC 112
453 #define SRST_P_PERIHP_GRF 113
454 #define SRST_H_PERIHP_NOC 114
455 #define SRST_USBHOST0 115
456 #define SRST_HOSTC0_AUX 116
457 #define SRST_HOST0_ARB 117
458 #define SRST_USBHOST1 118
459 #define SRST_HOSTC1_AUX 119
460 #define SRST_HOST1_ARB 120
461 #define SRST_SDIO0 121
462 #define SRST_SDMMC 122
463 #define SRST_HSIC 123
464 #define SRST_HSIC_AUX 124
465 #define SRST_AHB1TOM 125
466 #define SRST_P_PERIHP_NOC 126
467 #define SRST_HSICPHY 127
469 /* cru_softrst_con8 */
470 #define SRST_A_PCIE 128
471 #define SRST_P_PCIE 129
472 #define SRST_PCIE_CORE 130
473 #define SRST_PCIE_MGMT 131
474 #define SRST_PCIE_MGMT_STICKY 132
475 #define SRST_PCIE_PIPE 133
476 #define SRST_PCIE_PM 134
477 #define SRST_PCIEPHY 135
478 #define SRST_A_GMAC_NOC 136
479 #define SRST_A_GMAC 137
480 #define SRST_P_GMAC_NOC 138
481 #define SRST_P_GMAC_GRF 140
482 #define SRST_HSICPHY_POR 142
483 #define SRST_HSICPHY_UTMI 143
485 /* cru_softrst_con9 */
486 #define SRST_USB2PHY0_POR 144
487 #define SRST_USB2PHY0_UTMI_PORT0 145
488 #define SRST_USB2PHY0_UTMI_PORT1 146
489 #define SRST_USB2PHY0_EHCIPHY 147
490 #define SRST_UPHY0_PIPE_L00 148
491 #define SRST_UPHY0 149
492 #define SRST_UPHY0_TCPDPWRUP 150
493 #define SRST_USB2PHY1_POR 152
494 #define SRST_USB2PHY1_UTMI_PORT0 153
495 #define SRST_USB2PHY1_UTMI_PORT1 154
496 #define SRST_USB2PHY1_EHCIPHY 155
497 #define SRST_UPHY1_PIPE_L00 156
498 #define SRST_UPHY1 157
499 #define SRST_UPHY1_TCPDPWRUP 158
501 /* cru_softrst_con10 */
502 #define SRST_A_PERILP0_NOC 160
503 #define SRST_A_DCF 161
504 #define SRST_GIC500 162
505 #define SRST_DMAC0_PERILP0 163
506 #define SRST_DMAC1_PERILP0 164
507 #define SRST_TZMA 165
508 #define SRST_INTMEM 166
509 #define SRST_ADB400_MST0 167
510 #define SRST_ADB400_MST1 168
511 #define SRST_ADB400_SLV0 169
512 #define SRST_ADB400_SLV1 170
513 #define SRST_H_PERILP0 171
514 #define SRST_H_PERILP0_NOC 172
516 #define SRST_CRYPTO_S 174
517 #define SRST_CRYPTO_M 175
519 /* cru_softrst_con11 */
520 #define SRST_P_DCF 176
521 #define SRST_CM0S_NOC 177
522 #define SRST_CM0S 178
523 #define SRST_CM0S_DBG 179
524 #define SRST_CM0S_PO 180
525 #define SRST_CRYPTO 181
526 #define SRST_P_PERILP1_SGRF 182
527 #define SRST_P_PERILP1_GRF 183
528 #define SRST_CRYPTO1_S 184
529 #define SRST_CRYPTO1_M 185
530 #define SRST_CRYPTO1 186
531 #define SRST_GIC_NOC 188
532 #define SRST_SD_NOC 189
533 #define SRST_SDIOAUDIO_BRG 190
535 /* cru_softrst_con12 */
536 #define SRST_H_PERILP1 192
537 #define SRST_H_PERILP1_NOC 193
538 #define SRST_H_I2S0_8CH 194
539 #define SRST_H_I2S1_8CH 195
540 #define SRST_H_I2S2_8CH 196
541 #define SRST_H_SPDIF_8CH 197
542 #define SRST_P_PERILP1_NOC 198
543 #define SRST_P_EFUSE_1024 199
544 #define SRST_P_EFUSE_1024S 200
545 #define SRST_P_I2C0 201
546 #define SRST_P_I2C1 202
547 #define SRST_P_I2C2 203
548 #define SRST_P_I2C3 204
549 #define SRST_P_I2C4 205
550 #define SRST_P_I2C5 206
551 #define SRST_P_MAILBOX0 207
553 /* cru_softrst_con13 */
554 #define SRST_P_UART0 208
555 #define SRST_P_UART1 209
556 #define SRST_P_UART2 210
557 #define SRST_P_UART3 211
558 #define SRST_P_SARADC 212
559 #define SRST_P_TSADC 213
560 #define SRST_P_SPI0 214
561 #define SRST_P_SPI1 215
562 #define SRST_P_SPI2 216
563 #define SRST_P_SPI3 217
564 #define SRST_P_SPI4 218
565 #define SRST_SPI0 219
566 #define SRST_SPI1 220
567 #define SRST_SPI2 221
568 #define SRST_SPI3 222
569 #define SRST_SPI4 223
571 /* cru_softrst_con14 */
572 #define SRST_I2S0_8CH 224
573 #define SRST_I2S1_8CH 225
574 #define SRST_I2S2_8CH 226
575 #define SRST_SPDIF_8CH 227
576 #define SRST_UART0 228
577 #define SRST_UART1 229
578 #define SRST_UART2 230
579 #define SRST_UART3 231
580 #define SRST_TSADC 232
581 #define SRST_I2C0 233
582 #define SRST_I2C1 234
583 #define SRST_I2C2 235
584 #define SRST_I2C3 236
585 #define SRST_I2C4 237
586 #define SRST_I2C5 238
587 #define SRST_SDIOAUDIO_NOC 239
589 /* cru_softrst_con15 */
590 #define SRST_A_VIO_NOC 240
591 #define SRST_A_HDCP_NOC 241
592 #define SRST_A_HDCP 242
593 #define SRST_H_HDCP_NOC 243
594 #define SRST_H_HDCP 244
595 #define SRST_P_HDCP_NOC 245
596 #define SRST_P_HDCP 246
597 #define SRST_P_HDMI_CTRL 247
598 #define SRST_P_DP_CTRL 248
599 #define SRST_S_DP_CTRL 249
600 #define SRST_C_DP_CTRL 250
601 #define SRST_P_MIPI_DSI0 251
602 #define SRST_P_MIPI_DSI1 252
603 #define SRST_DP_CORE 253
604 #define SRST_DP_I2S 254
606 /* cru_softrst_con16 */
607 #define SRST_GASKET 256
608 #define SRST_VIO_GRF 258
609 #define SRST_DPTX_SPDIF_REC 259
610 #define SRST_HDMI_CTRL 260
611 #define SRST_HDCP_CTRL 261
612 #define SRST_A_ISP0_NOC 262
613 #define SRST_A_ISP1_NOC 263
614 #define SRST_H_ISP0_NOC 266
615 #define SRST_H_ISP1_NOC 267
616 #define SRST_H_ISP0 268
617 #define SRST_H_ISP1 269
618 #define SRST_ISP0 270
619 #define SRST_ISP1 271
621 /* cru_softrst_con17 */
622 #define SRST_A_VOP0_NOC 272
623 #define SRST_A_VOP1_NOC 273
624 #define SRST_A_VOP0 274
625 #define SRST_A_VOP1 275
626 #define SRST_H_VOP0_NOC 276
627 #define SRST_H_VOP1_NOC 277
628 #define SRST_H_VOP0 278
629 #define SRST_H_VOP1 279
630 #define SRST_D_VOP0 280
631 #define SRST_D_VOP1 281
632 #define SRST_VOP0_PWM 282
633 #define SRST_VOP1_PWM 283
634 #define SRST_P_EDP_NOC 284
635 #define SRST_P_EDP_CTRL 285
637 /* cru_softrst_con18 */
638 #define SRST_A_GPU_NOC 289
639 #define SRST_A_GPU_GRF 290
640 #define SRST_PVTM_GPU 291
641 #define SRST_A_USB3_NOC 292
642 #define SRST_A_USB3_OTG0 293
643 #define SRST_A_USB3_OTG1 294
644 #define SRST_A_USB3_GRF 295
647 /* cru_softrst_con19 */
648 #define SRST_P_TIMER0_5 304
649 #define SRST_TIMER0 305
650 #define SRST_TIMER1 306
651 #define SRST_TIMER2 307
652 #define SRST_TIMER3 308
653 #define SRST_TIMER4 309
654 #define SRST_TIMER5 310
655 #define SRST_P_TIMER6_11 311
656 #define SRST_TIMER6 312
657 #define SRST_TIMER7 313
658 #define SRST_TIMER8 314
659 #define SRST_TIMER9 315
660 #define SRST_TIMER10 316
661 #define SRST_TIMER11 317
662 #define SRST_P_INTR_ARB_PMU 318
663 #define SRST_P_ALIVE_SGRF 319
665 /* cru_softrst_con20 */
666 #define SRST_P_GPIO2 320
667 #define SRST_P_GPIO3 321
668 #define SRST_P_GPIO4 322
669 #define SRST_P_GRF 323
670 #define SRST_P_ALIVE_NOC 324
671 #define SRST_P_WDT0 325
672 #define SRST_P_WDT1 326
673 #define SRST_P_INTR_ARB 327
674 #define SRST_P_UPHY0_DPTX 328
675 #define SRST_P_UPHY0_APB 330
676 #define SRST_P_UPHY0_TCPHY 332
677 #define SRST_P_UPHY1_TCPHY 333
678 #define SRST_P_UPHY0_TCPDCTRL 334
679 #define SRST_P_UPHY1_TCPDCTRL 335
681 /* pmu soft-reset indices */
683 /* pmu_cru_softrst_con0 */
685 #define SRST_P_INTMEM 1
686 #define SRST_H_CM0S 2
687 #define SRST_H_CM0S_NOC 3
688 #define SRST_DBG_CM0S 4
689 #define SRST_PO_CM0S 5
690 #define SRST_P_SPI6 6
692 #define SRST_P_TIMER_0_1 8
693 #define SRST_P_TIMER_0 9
694 #define SRST_P_TIMER_1 10
695 #define SRST_P_UART4 11
696 #define SRST_UART4 12
697 #define SRST_P_WDT 13
699 /* pmu_cru_softrst_con1 */
700 #define SRST_P_I2C6 16
701 #define SRST_P_I2C7 17
702 #define SRST_P_I2C8 18
703 #define SRST_P_MAILBOX 19
704 #define SRST_P_RKPWM 20
705 #define SRST_P_PMUGRF 21
706 #define SRST_P_SGRF 22
707 #define SRST_P_GPIO0 23
708 #define SRST_P_GPIO1 24
709 #define SRST_P_CRU 25
710 #define SRST_P_INTR 26