2 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
3 * Author: Xing Zheng <zhengxing@rock-chips.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
17 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
30 /* sclk gates (special clocks) */
46 #define SCLK_SARADC 80
51 #define SCLK_SPDIF_8CH 85
52 #define SCLK_I2S0_8CH 86
53 #define SCLK_I2S1_8CH 87
54 #define SCLK_I2S2_8CH 88
55 #define SCLK_I2S_8CH_OUT 89
56 #define SCLK_TIMER00 90
57 #define SCLK_TIMER01 91
58 #define SCLK_TIMER02 92
59 #define SCLK_TIMER03 93
60 #define SCLK_TIMER04 94
61 #define SCLK_TIMER05 95
62 #define SCLK_TIMER06 96
63 #define SCLK_TIMER07 97
64 #define SCLK_TIMER08 98
65 #define SCLK_TIMER09 99
66 #define SCLK_TIMER10 100
67 #define SCLK_TIMER11 101
68 #define SCLK_MACREF 102
69 #define SCLK_MAC_RX 103
70 #define SCLK_MAC_TX 104
72 #define SCLK_MACREF_OUT 106
73 #define SCLK_VOP0_PWM 107
74 #define SCLK_VOP1_PWM 108
75 #define SCLK_RGA_CORE 109
78 #define SCLK_HDMI_CEC 112
79 #define SCLK_HDMI_SFR 113
80 #define SCLK_DP_CORE 114
81 #define SCLK_PVTM_CORE_L 115
82 #define SCLK_PVTM_CORE_B 116
83 #define SCLK_PVTM_GPU 117
84 #define SCLK_PVTM_DDR 118
85 #define SCLK_MIPIDPHY_REF 119
86 #define SCLK_MIPIDPHY_CFG 120
87 #define SCLK_HSICPHY 121
88 #define SCLK_USBPHY480M 122
89 #define SCLK_USB2PHY0_REF 123
90 #define SCLK_USB2PHY1_REF 124
91 #define SCLK_UPHY0_TCPDPHY_REF 125
92 #define SCLK_UPHY0_TCPDCORE 126
93 #define SCLK_UPHY1_TCPDPHY_REF 127
94 #define SCLK_UPHY1_TCPDCORE 128
95 #define SCLK_USB3OTG0_REF 129
96 #define SCLK_USB3OTG1_REF 130
97 #define SCLK_USB3OTG0_SUSPEND 131
98 #define SCLK_USB3OTG1_SUSPEND 132
99 #define SCLK_CRYPTO0 133
100 #define SCLK_CRYPTO1 134
101 #define SCLK_CCI_TRACE 135
103 #define SCLK_CIF_OUT 137
104 #define SCLK_PCIEPHY_REF 138
105 #define SCLK_PCIE_CORE 139
106 #define SCLK_M0_PERILP 140
107 #define SCLK_M0_PERILP_DEC 141
108 #define SCLK_CM0S 142
109 #define SCLK_DBG_NOC 143
110 #define SCLK_DBG_PD_CORE_B 144
111 #define SCLK_DBG_PD_CORE_L 145
112 #define SCLK_DFIMON0_TIMER 146
113 #define SCLK_DFIMON1_TIMER 147
114 #define SCLK_INTMEM0 148
115 #define SCLK_INTMEM1 149
116 #define SCLK_INTMEM2 150
117 #define SCLK_INTMEM3 151
118 #define SCLK_INTMEM4 152
119 #define SCLK_INTMEM5 153
120 #define SCLK_SDMMC_DRV 154
121 #define SCLK_SDMMC_SAMPLE 155
122 #define SCLK_SDIO_DRV 156
123 #define SCLK_SDIO_SAMPLE 157
124 #define SCLK_VDU_CORE 158
125 #define SCLK_VDU_CA 159
126 #define SCLK_PCIE_PM 160
127 #define SCLK_SPDIF_REC_DPTX 161
128 #define SCLK_DPHY_PLL 162
129 #define SCLK_DPHY_TX0_CFG 163
130 #define SCLK_DPHY_TX1RX1_CFG 164
131 #define SCLK_DPHY_RX0_CFG 165
132 #define SCLK_RMII_SRC 166
133 #define SCLK_PCIEPHY_REF100M 167
134 #define SCLK_USBPHY0_480M_SRC 168
135 #define SCLK_USBPHY1_480M_SRC 169
137 #define DCLK_VOP0 180
138 #define DCLK_VOP1 181
139 #define DCLK_VOP0_DIV 182
140 #define DCLK_VOP1_DIV 183
141 #define DCLK_M0_PERILP 184
143 #define FCLK_CM0S 190
146 #define ACLK_PERIHP 192
147 #define ACLK_PERIHP_NOC 193
148 #define ACLK_PERILP0 194
149 #define ACLK_PERILP0_NOC 195
150 #define ACLK_PERF_PCIE 196
151 #define ACLK_PCIE 197
152 #define ACLK_INTMEM 198
153 #define ACLK_TZMA 199
156 #define ACLK_CCI_NOC0 202
157 #define ACLK_CCI_NOC1 203
158 #define ACLK_CCI_GRF 204
159 #define ACLK_CENTER 205
160 #define ACLK_CENTER_MAIN_NOC 206
161 #define ACLK_CENTER_PERI_NOC 207
163 #define ACLK_PERF_GPU 209
164 #define ACLK_GPU_GRF 210
165 #define ACLK_DMAC0_PERILP 211
166 #define ACLK_DMAC1_PERILP 212
167 #define ACLK_GMAC 213
168 #define ACLK_GMAC_NOC 214
169 #define ACLK_PERF_GMAC 215
170 #define ACLK_VOP0_NOC 216
171 #define ACLK_VOP0 217
172 #define ACLK_VOP1_NOC 218
173 #define ACLK_VOP1 219
175 #define ACLK_RGA_NOC 221
176 #define ACLK_HDCP 222
177 #define ACLK_HDCP_NOC 223
178 #define ACLK_HDCP22 224
180 #define ACLK_IEP_NOC 226
182 #define ACLK_VIO_NOC 228
183 #define ACLK_ISP0 229
184 #define ACLK_ISP1 230
185 #define ACLK_ISP0_NOC 231
186 #define ACLK_ISP1_NOC 232
187 #define ACLK_ISP0_WRAPPER 233
188 #define ACLK_ISP1_WRAPPER 234
189 #define ACLK_VCODEC 235
190 #define ACLK_VCODEC_NOC 236
192 #define ACLK_VDU_NOC 238
193 #define ACLK_PERI 239
194 #define ACLK_EMMC 240
195 #define ACLK_EMMC_CORE 241
196 #define ACLK_EMMC_NOC 242
197 #define ACLK_EMMC_GRF 243
198 #define ACLK_USB3 244
199 #define ACLK_USB3_NOC 245
200 #define ACLK_USB3OTG0 246
201 #define ACLK_USB3OTG1 247
202 #define ACLK_USB3_RKSOC_AXI_PERF 248
203 #define ACLK_USB3_GRF 249
205 #define ACLK_GIC_NOC 251
206 #define ACLK_GIC_ADB400_CORE_L_2_GIC 252
207 #define ACLK_GIC_ADB400_CORE_B_2_GIC 253
208 #define ACLK_GIC_ADB400_GIC_2_CORE_L 254
209 #define ACLK_GIC_ADB400_GIC_2_CORE_B 255
210 #define ACLK_CORE_ADB400_CORE_L_2_CCI500 256
211 #define ACLK_CORE_ADB400_CORE_B_2_CCI500 257
212 #define ACLK_ADB400M_PD_CORE_L 258
213 #define ACLK_ADB400M_PD_CORE_B 259
214 #define ACLK_PERF_CORE_L 260
215 #define ACLK_PERF_CORE_B 261
216 #define ACLK_GIC_PRE 262
217 #define ACLK_VOP0_PRE 263
218 #define ACLK_VOP1_PRE 264
221 #define PCLK_PERIHP 320
222 #define PCLK_PERIHP_NOC 321
223 #define PCLK_PERILP0 322
224 #define PCLK_PERILP1 323
225 #define PCLK_PERILP1_NOC 324
226 #define PCLK_PERILP_SGRF 325
227 #define PCLK_PERIHP_GRF 326
228 #define PCLK_PCIE 327
229 #define PCLK_SGRF 328
230 #define PCLK_INTR_ARB 329
231 #define PCLK_CENTER_MAIN_NOC 330
233 #define PCLK_COREDBG_B 332
234 #define PCLK_COREDBG_L 333
235 #define PCLK_DBG_CXCS_PD_CORE_B 334
237 #define PCLK_GPIO2 336
238 #define PCLK_GPIO3 337
239 #define PCLK_GPIO4 338
241 #define PCLK_HSICPHY 340
242 #define PCLK_I2C1 341
243 #define PCLK_I2C2 342
244 #define PCLK_I2C3 343
245 #define PCLK_I2C5 344
246 #define PCLK_I2C6 345
247 #define PCLK_I2C7 346
248 #define PCLK_SPI0 347
249 #define PCLK_SPI1 348
250 #define PCLK_SPI2 349
251 #define PCLK_SPI4 350
252 #define PCLK_SPI5 351
253 #define PCLK_UART0 352
254 #define PCLK_UART1 353
255 #define PCLK_UART2 354
256 #define PCLK_UART3 355
257 #define PCLK_TSADC 356
258 #define PCLK_SARADC 357
259 #define PCLK_GMAC 358
260 #define PCLK_GMAC_NOC 359
261 #define PCLK_TIMER0 360
262 #define PCLK_TIMER1 361
264 #define PCLK_EDP_NOC 363
265 #define PCLK_EDP_CTRL 364
267 #define PCLK_VIO_NOC 366
268 #define PCLK_VIO_GRF 367
269 #define PCLK_MIPI_DSI0 368
270 #define PCLK_MIPI_DSI1 369
271 #define PCLK_HDCP 370
272 #define PCLK_HDCP_NOC 371
273 #define PCLK_HDMI_CTRL 372
274 #define PCLK_DP_CTRL 373
275 #define PCLK_HDCP22 374
276 #define PCLK_GASKET 375
278 #define PCLK_DDR_MON 377
279 #define PCLK_DDR_SGRF 378
280 #define PCLK_ISP1_WRAPPER 379
282 #define PCLK_EFUSE1024NS 381
283 #define PCLK_EFUSE1024S 382
284 #define PCLK_PMU_INTR_ARB 383
285 #define PCLK_MAILBOX0 384
286 #define PCLK_USBPHY_MUX_G 385
287 #define PCLK_UPHY0_TCPHY_G 386
288 #define PCLK_UPHY0_TCPD_G 387
289 #define PCLK_UPHY1_TCPHY_G 388
290 #define PCLK_UPHY1_TCPD_G 389
291 #define PCLK_ALIVE 390
294 #define HCLK_PERIHP 448
295 #define HCLK_PERILP0 449
296 #define HCLK_PERILP1 450
297 #define HCLK_PERILP0_NOC 451
298 #define HCLK_PERILP1_NOC 452
299 #define HCLK_M0_PERILP 453
300 #define HCLK_M0_PERILP_NOC 454
301 #define HCLK_AHB1TOM 455
302 #define HCLK_HOST0 456
303 #define HCLK_HOST0_ARB 457
304 #define HCLK_HOST1 458
305 #define HCLK_HOST1_ARB 459
306 #define HCLK_HSIC 460
308 #define HCLK_SDMMC 462
309 #define HCLK_SDMMC_NOC 463
310 #define HCLK_M_CRYPTO0 464
311 #define HCLK_M_CRYPTO1 465
312 #define HCLK_S_CRYPTO0 466
313 #define HCLK_S_CRYPTO1 467
314 #define HCLK_I2S0_8CH 468
315 #define HCLK_I2S1_8CH 469
316 #define HCLK_I2S2_8CH 470
317 #define HCLK_SPDIF 471
318 #define HCLK_VOP0_NOC 472
319 #define HCLK_VOP0 473
320 #define HCLK_VOP1_NOC 474
321 #define HCLK_VOP1 475
324 #define HCLK_IEP_NOC 478
325 #define HCLK_ISP0 479
326 #define HCLK_ISP1 480
327 #define HCLK_ISP0_NOC 481
328 #define HCLK_ISP1_NOC 482
329 #define HCLK_ISP0_WRAPPER 483
330 #define HCLK_ISP1_WRAPPER 484
332 #define HCLK_RGA_NOC 486
333 #define HCLK_HDCP 487
334 #define HCLK_HDCP_NOC 488
335 #define HCLK_HDCP22 489
336 #define HCLK_VCODEC 490
337 #define HCLK_VCODEC_NOC 491
339 #define HCLK_VDU_NOC 493
340 #define HCLK_SDIO 494
341 #define HCLK_SDIO_NOC 495
342 #define HCLK_SDIOAUDIO_NOC 496
344 #define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1)
346 /* pmu-clocks indices */
350 #define SCLK_32K_SUSPEND_PMU 2
351 #define SCLK_SPI3_PMU 3
352 #define SCLK_TIMER12_PMU 4
353 #define SCLK_TIMER13_PMU 5
354 #define SCLK_UART4_PMU 6
355 #define SCLK_PVTM_PMU 7
356 #define SCLK_WIFI_PMU 8
357 #define SCLK_I2C0_PMU 9
358 #define SCLK_I2C4_PMU 10
359 #define SCLK_I2C8_PMU 11
361 #define PCLK_SRC_PMU 19
363 #define PCLK_PMUGRF_PMU 21
364 #define PCLK_INTMEM1_PMU 22
365 #define PCLK_GPIO0_PMU 23
366 #define PCLK_GPIO1_PMU 24
367 #define PCLK_SGRF_PMU 25
368 #define PCLK_NOC_PMU 26
369 #define PCLK_I2C0_PMU 27
370 #define PCLK_I2C4_PMU 28
371 #define PCLK_I2C8_PMU 29
372 #define PCLK_RKPWM_PMU 30
373 #define PCLK_SPI3_PMU 31
374 #define PCLK_TIMER_PMU 32
375 #define PCLK_MAILBOX_PMU 33
376 #define PCLK_UART4_PMU 34
377 #define PCLK_WDT_M0_PMU 35
379 #define FCLK_CM0S_SRC_PMU 44
380 #define FCLK_CM0S_PMU 45
381 #define SCLK_CM0S_PMU 46
382 #define HCLK_CM0S_PMU 47
383 #define DCLK_CM0S_PMU 48
384 #define PCLK_INTR_ARB_PMU 49
385 #define HCLK_NOC_PMU 50
387 #define CLKPMU_NR_CLKS (HCLK_NOC_PMU + 1)
389 /* soft-reset indices */
391 /* cru_softrst_con0 */
392 #define SRST_CORE_L0 0
393 #define SRST_CORE_B0 1
394 #define SRST_CORE_PO_L0 2
395 #define SRST_CORE_PO_B0 3
401 #define SRST_A_CCIM0_NOC 9
402 #define SRST_A_CCIM1_NOC 10
403 #define SRST_DBG_NOC 11
405 /* cru_softrst_con1 */
406 #define SRST_CORE_L0_T 16
407 #define SRST_CORE_L1 17
408 #define SRST_CORE_L2 18
409 #define SRST_CORE_L3 19
410 #define SRST_CORE_PO_L0_T 20
411 #define SRST_CORE_PO_L1 21
412 #define SRST_CORE_PO_L2 22
413 #define SRST_CORE_PO_L3 23
414 #define SRST_A_ADB400_GIC2COREL 24
415 #define SRST_A_ADB400_COREL2GIC 25
416 #define SRST_P_DBG_L 26
417 #define SRST_L2_L_T 28
418 #define SRST_ADB_L_T 29
419 #define SRST_A_RKPERF_L 30
420 #define SRST_PVTM_CORE_L 31
422 /* cru_softrst_con2 */
423 #define SRST_CORE_B0_T 32
424 #define SRST_CORE_B1 33
425 #define SRST_CORE_PO_B0_T 36
426 #define SRST_CORE_PO_B1 37
427 #define SRST_A_ADB400_GIC2COREB 40
428 #define SRST_A_ADB400_COREB2GIC 41
429 #define SRST_P_DBG_B 42
430 #define SRST_L2_B_T 43
431 #define SRST_ADB_B_T 45
432 #define SRST_A_RKPERF_B 46
433 #define SRST_PVTM_CORE_B 47
435 /* cru_softrst_con3 */
436 #define SRST_A_CCI_T 50
437 #define SRST_A_CCIM0_NOC_T 51
438 #define SRST_A_CCIM1_NOC_T 52
439 #define SRST_A_ADB400M_PD_CORE_B_T 53
440 #define SRST_A_ADB400M_PD_CORE_L_T 54
441 #define SRST_DBG_NOC_T 55
442 #define SRST_DBG_CXCS 56
443 #define SRST_CCI_TRACE 57
444 #define SRST_P_CCI_GRF 58
446 /* cru_softrst_con4 */
447 #define SRST_A_CENTER_MAIN_NOC 64
448 #define SRST_A_CENTER_PERI_NOC 65
449 #define SRST_P_CENTER_MAIN 66
450 #define SRST_P_DDRMON 67
451 #define SRST_P_CIC 68
452 #define SRST_P_CENTER_SGRF 69
453 #define SRST_DDR0_MSCH 70
454 #define SRST_DDRCFG0_MSCH 71
456 #define SRST_DDRPHY0 73
457 #define SRST_DDR1_MSCH 74
458 #define SRST_DDRCFG1_MSCH 75
460 #define SRST_DDRPHY1 77
461 #define SRST_DDR_CIC 78
462 #define SRST_PVTM_DDR 79
464 /* cru_softrst_con5 */
465 #define SRST_A_VCODEC_NOC 80
466 #define SRST_A_VCODEC 81
467 #define SRST_H_VCODEC_NOC 82
468 #define SRST_H_VCODEC 83
469 #define SRST_A_VDU_NOC 88
470 #define SRST_A_VDU 89
471 #define SRST_H_VDU_NOC 90
472 #define SRST_H_VDU 91
473 #define SRST_VDU_CORE 92
474 #define SRST_VDU_CA 93
476 /* cru_softrst_con6 */
477 #define SRST_A_IEP_NOC 96
478 #define SRST_A_VOP_IEP 97
479 #define SRST_A_IEP 98
480 #define SRST_H_IEP_NOC 99
481 #define SRST_H_IEP 100
482 #define SRST_A_RGA_NOC 102
483 #define SRST_A_RGA 103
484 #define SRST_H_RGA_NOC 104
485 #define SRST_H_RGA 105
486 #define SRST_RGA_CORE 106
487 #define SRST_EMMC_NOC 108
488 #define SRST_EMMC 109
489 #define SRST_EMMC_GRF 110
491 /* cru_softrst_con7 */
492 #define SRST_A_PERIHP_NOC 112
493 #define SRST_P_PERIHP_GRF 113
494 #define SRST_H_PERIHP_NOC 114
495 #define SRST_USBHOST0 115
496 #define SRST_HOSTC0_AUX 116
497 #define SRST_HOST0_ARB 117
498 #define SRST_USBHOST1 118
499 #define SRST_HOSTC1_AUX 119
500 #define SRST_HOST1_ARB 120
501 #define SRST_SDIO0 121
502 #define SRST_SDMMC 122
503 #define SRST_HSIC 123
504 #define SRST_HSIC_AUX 124
505 #define SRST_AHB1TOM 125
506 #define SRST_P_PERIHP_NOC 126
507 #define SRST_HSICPHY 127
509 /* cru_softrst_con8 */
510 #define SRST_A_PCIE 128
511 #define SRST_P_PCIE 129
512 #define SRST_PCIE_CORE 130
513 #define SRST_PCIE_MGMT 131
514 #define SRST_PCIE_MGMT_STICKY 132
515 #define SRST_PCIE_PIPE 133
516 #define SRST_PCIE_PM 134
517 #define SRST_PCIEPHY 135
518 #define SRST_A_GMAC_NOC 136
519 #define SRST_A_GMAC 137
520 #define SRST_P_GMAC_NOC 138
521 #define SRST_P_GMAC_GRF 140
522 #define SRST_HSICPHY_POR 142
523 #define SRST_HSICPHY_UTMI 143
525 /* cru_softrst_con9 */
526 #define SRST_USB2PHY0_POR 144
527 #define SRST_USB2PHY0_UTMI_PORT0 145
528 #define SRST_USB2PHY0_UTMI_PORT1 146
529 #define SRST_USB2PHY0_EHCIPHY 147
530 #define SRST_UPHY0_PIPE_L00 148
531 #define SRST_UPHY0 149
532 #define SRST_UPHY0_TCPDPWRUP 150
533 #define SRST_USB2PHY1_POR 152
534 #define SRST_USB2PHY1_UTMI_PORT0 153
535 #define SRST_USB2PHY1_UTMI_PORT1 154
536 #define SRST_USB2PHY1_EHCIPHY 155
537 #define SRST_UPHY1_PIPE_L00 156
538 #define SRST_UPHY1 157
539 #define SRST_UPHY1_TCPDPWRUP 158
541 /* cru_softrst_con10 */
542 #define SRST_A_PERILP0_NOC 160
543 #define SRST_A_DCF 161
544 #define SRST_GIC500 162
545 #define SRST_DMAC0_PERILP0 163
546 #define SRST_DMAC1_PERILP0 164
547 #define SRST_TZMA 165
548 #define SRST_INTMEM 166
549 #define SRST_ADB400_MST0 167
550 #define SRST_ADB400_MST1 168
551 #define SRST_ADB400_SLV0 169
552 #define SRST_ADB400_SLV1 170
553 #define SRST_H_PERILP0 171
554 #define SRST_H_PERILP0_NOC 172
556 #define SRST_CRYPTO_S 174
557 #define SRST_CRYPTO_M 175
559 /* cru_softrst_con11 */
560 #define SRST_P_DCF 176
561 #define SRST_CM0S_NOC 177
562 #define SRST_CM0S 178
563 #define SRST_CM0S_DBG 179
564 #define SRST_CM0S_PO 180
565 #define SRST_CRYPTO 181
566 #define SRST_P_PERILP1_SGRF 182
567 #define SRST_P_PERILP1_GRF 183
568 #define SRST_CRYPTO1_S 184
569 #define SRST_CRYPTO1_M 185
570 #define SRST_CRYPTO1 186
571 #define SRST_GIC_NOC 188
572 #define SRST_SD_NOC 189
573 #define SRST_SDIOAUDIO_BRG 190
575 /* cru_softrst_con12 */
576 #define SRST_H_PERILP1 192
577 #define SRST_H_PERILP1_NOC 193
578 #define SRST_H_I2S0_8CH 194
579 #define SRST_H_I2S1_8CH 195
580 #define SRST_H_I2S2_8CH 196
581 #define SRST_H_SPDIF_8CH 197
582 #define SRST_P_PERILP1_NOC 198
583 #define SRST_P_EFUSE_1024 199
584 #define SRST_P_EFUSE_1024S 200
585 #define SRST_P_I2C0 201
586 #define SRST_P_I2C1 202
587 #define SRST_P_I2C2 203
588 #define SRST_P_I2C3 204
589 #define SRST_P_I2C4 205
590 #define SRST_P_I2C5 206
591 #define SRST_P_MAILBOX0 207
593 /* cru_softrst_con13 */
594 #define SRST_P_UART0 208
595 #define SRST_P_UART1 209
596 #define SRST_P_UART2 210
597 #define SRST_P_UART3 211
598 #define SRST_P_SARADC 212
599 #define SRST_P_TSADC 213
600 #define SRST_P_SPI0 214
601 #define SRST_P_SPI1 215
602 #define SRST_P_SPI2 216
603 #define SRST_P_SPI3 217
604 #define SRST_P_SPI4 218
605 #define SRST_SPI0 219
606 #define SRST_SPI1 220
607 #define SRST_SPI2 221
608 #define SRST_SPI3 222
609 #define SRST_SPI4 223
611 /* cru_softrst_con14 */
612 #define SRST_I2S0_8CH 224
613 #define SRST_I2S1_8CH 225
614 #define SRST_I2S2_8CH 226
615 #define SRST_SPDIF_8CH 227
616 #define SRST_UART0 228
617 #define SRST_UART1 229
618 #define SRST_UART2 230
619 #define SRST_UART3 231
620 #define SRST_TSADC 232
621 #define SRST_I2C0 233
622 #define SRST_I2C1 234
623 #define SRST_I2C2 235
624 #define SRST_I2C3 236
625 #define SRST_I2C4 237
626 #define SRST_I2C5 238
627 #define SRST_SDIOAUDIO_NOC 239
629 /* cru_softrst_con15 */
630 #define SRST_A_VIO_NOC 240
631 #define SRST_A_HDCP_NOC 241
632 #define SRST_A_HDCP 242
633 #define SRST_H_HDCP_NOC 243
634 #define SRST_H_HDCP 244
635 #define SRST_P_HDCP_NOC 245
636 #define SRST_P_HDCP 246
637 #define SRST_P_HDMI_CTRL 247
638 #define SRST_P_DP_CTRL 248
639 #define SRST_S_DP_CTRL 249
640 #define SRST_C_DP_CTRL 250
641 #define SRST_P_MIPI_DSI0 251
642 #define SRST_P_MIPI_DSI1 252
643 #define SRST_DP_CORE 253
644 #define SRST_DP_I2S 254
646 /* cru_softrst_con16 */
647 #define SRST_GASKET 256
648 #define SRST_VIO_GRF 258
649 #define SRST_DPTX_SPDIF_REC 259
650 #define SRST_HDMI_CTRL 260
651 #define SRST_HDCP_CTRL 261
652 #define SRST_A_ISP0_NOC 262
653 #define SRST_A_ISP1_NOC 263
654 #define SRST_H_ISP0_NOC 266
655 #define SRST_H_ISP1_NOC 267
656 #define SRST_H_ISP0 268
657 #define SRST_H_ISP1 269
658 #define SRST_ISP0 270
659 #define SRST_ISP1 271
661 /* cru_softrst_con17 */
662 #define SRST_A_VOP0_NOC 272
663 #define SRST_A_VOP1_NOC 273
664 #define SRST_A_VOP0 274
665 #define SRST_A_VOP1 275
666 #define SRST_H_VOP0_NOC 276
667 #define SRST_H_VOP1_NOC 277
668 #define SRST_H_VOP0 278
669 #define SRST_H_VOP1 279
670 #define SRST_D_VOP0 280
671 #define SRST_D_VOP1 281
672 #define SRST_VOP0_PWM 282
673 #define SRST_VOP1_PWM 283
674 #define SRST_P_EDP_NOC 284
675 #define SRST_P_EDP_CTRL 285
677 /* cru_softrst_con18 */
678 #define SRST_A_GPU 288
679 #define SRST_A_GPU_NOC 289
680 #define SRST_A_GPU_GRF 290
681 #define SRST_PVTM_GPU 291
682 #define SRST_A_USB3_NOC 292
683 #define SRST_A_USB3_OTG0 293
684 #define SRST_A_USB3_OTG1 294
685 #define SRST_A_USB3_GRF 295
688 /* cru_softrst_con19 */
689 #define SRST_P_TIMER0_5 304
690 #define SRST_TIMER0 305
691 #define SRST_TIMER1 306
692 #define SRST_TIMER2 307
693 #define SRST_TIMER3 308
694 #define SRST_TIMER4 309
695 #define SRST_TIMER5 310
696 #define SRST_P_TIMER6_11 311
697 #define SRST_TIMER6 312
698 #define SRST_TIMER7 313
699 #define SRST_TIMER8 314
700 #define SRST_TIMER9 315
701 #define SRST_TIMER10 316
702 #define SRST_TIMER11 317
703 #define SRST_P_INTR_ARB_PMU 318
704 #define SRST_P_ALIVE_SGRF 319
706 /* cru_softrst_con20 */
707 #define SRST_P_GPIO2 320
708 #define SRST_P_GPIO3 321
709 #define SRST_P_GPIO4 322
710 #define SRST_P_GRF 323
711 #define SRST_P_ALIVE_NOC 324
712 #define SRST_P_WDT0 325
713 #define SRST_P_WDT1 326
714 #define SRST_P_INTR_ARB 327
715 #define SRST_P_UPHY0_DPTX 328
716 #define SRST_P_UPHY0_APB 330
717 #define SRST_P_UPHY0_TCPHY 332
718 #define SRST_P_UPHY1_TCPHY 333
719 #define SRST_P_UPHY0_TCPDCTRL 334
720 #define SRST_P_UPHY1_TCPDCTRL 335
722 /* pmu soft-reset indices */
724 /* pmu_cru_softrst_con0 */
726 #define SRST_P_INTMEM 1
727 #define SRST_H_CM0S 2
728 #define SRST_H_CM0S_NOC 3
729 #define SRST_DBG_CM0S 4
730 #define SRST_PO_CM0S 5
731 #define SRST_P_SPI6 6
733 #define SRST_P_TIMER_0_1 8
734 #define SRST_P_TIMER_0 9
735 #define SRST_P_TIMER_1 10
736 #define SRST_P_UART4 11
737 #define SRST_UART4 12
738 #define SRST_P_WDT 13
740 /* pmu_cru_softrst_con1 */
741 #define SRST_P_I2C6 16
742 #define SRST_P_I2C7 17
743 #define SRST_P_I2C8 18
744 #define SRST_P_MAILBOX 19
745 #define SRST_P_RKPWM 20
746 #define SRST_P_PMUGRF 21
747 #define SRST_P_SGRF 22
748 #define SRST_P_GPIO0 23
749 #define SRST_P_GPIO1 24
750 #define SRST_P_CRU 25
751 #define SRST_P_INTR 26