2 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
3 * Author: Xing Zheng <zhengxing@rock-chips.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
17 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
31 /* sclk gates (special clocks) */
47 #define SCLK_SARADC 80
52 #define SCLK_SPDIF_8CH 85
53 #define SCLK_I2S0_8CH 86
54 #define SCLK_I2S1_8CH 87
55 #define SCLK_I2S2_8CH 88
56 #define SCLK_I2S_8CH_OUT 89
57 #define SCLK_TIMER00 90
58 #define SCLK_TIMER01 91
59 #define SCLK_TIMER02 92
60 #define SCLK_TIMER03 93
61 #define SCLK_TIMER04 94
62 #define SCLK_TIMER05 95
63 #define SCLK_TIMER06 96
64 #define SCLK_TIMER07 97
65 #define SCLK_TIMER08 98
66 #define SCLK_TIMER09 99
67 #define SCLK_TIMER10 100
68 #define SCLK_TIMER11 101
69 #define SCLK_MACREF 102
70 #define SCLK_MAC_RX 103
71 #define SCLK_MAC_TX 104
73 #define SCLK_MACREF_OUT 106
74 #define SCLK_VOP0_PWM 107
75 #define SCLK_VOP1_PWM 108
79 #define SCLK_HDMI_CEC 112
80 #define SCLK_HDMI_SFR 113
81 #define SCLK_DP_CORE_SRC 114
82 #define SCLK_PVTM_CORE_L 115
83 #define SCLK_PVTM_CORE_B 116
84 #define SCLK_PVTM_GPU 117
85 #define SCLK_PVTM_DDR 118
86 #define SCLK_MIPIDPHY_REF 119
87 #define SCLK_MIPIDPHY_CFG 120
88 #define SCLK_HSICPHY 121
89 #define SCLK_USBPHY480M 122
90 #define SCLK_USB2PHY0_REF 123
91 #define SCLK_USB2PHY1_REF 124
92 #define SCLK_UPHY0_TCPDPHY_REF 125
93 #define SCLK_UPHY0_TCPDCORE 126
94 #define SCLK_UPHY1_TCPDPHY_REF 127
95 #define SCLK_UPHY1_TCPDCORE 128
96 #define SCLK_USB3OTG0_REF 129
97 #define SCLK_USB3OTG1_REF 130
98 #define SCLK_USB3OTG0_SUSPEND 131
99 #define SCLK_USB3OTG1_SUSPEND 132
100 #define SCLK_CRYPTO0 133
101 #define SCLK_CRYPTO1 134
102 #define SCLK_CCI_TRACE 135
104 #define SCLK_CIF_OUT 137
105 #define SCLK_PCIEPHY_REF 138
106 #define SCLK_PCIE_CORE 139
107 #define SCLK_MO_PERILP 140
108 #define SCLK_M0_PERILP_DEC 141
109 #define SCLK_CM0S 142
110 #define SCLK_DBG_NOC 143
111 #define SCLK_DBG_PD_CORE_B 144
112 #define SCLK_DBG_PD_CORE_L 145
113 #define SCLK_DFIMON0_TIMER 146
114 #define SCLK_DFIMON1_TIMER 147
115 #define SCLK_INTMEM0 148
116 #define SCLK_INTMEM1 149
117 #define SCLK_INTMEM2 150
118 #define SCLK_INTMEM3 151
119 #define SCLK_INTMEM4 152
120 #define SCLK_INTMEM5 153
121 #define SCLK_SDMMC_DRV 154
122 #define SCLK_SDMMC_SAMPLE 155
123 #define SCLK_SDIO_DRV 156
124 #define SCLK_SDIO_SAMPLE 157
126 #define DCLK_VOP0 170
127 #define DCLK_VOP1 171
130 #define ACLK_PERIHP 192
131 #define ACLK_PERIHP_NOC 193
132 #define ACLK_PERILP0 194
133 #define ACLK_PERILP0_NOC 195
134 #define ACLK_PERF_PCIE 196
135 #define ACLK_PCIE 197
136 #define ACLK_INTMEM 198
137 #define ACLK_TZMA 199
140 #define ACLK_CCI_NOC0 202
141 #define ACLK_CCI_NOC1 203
142 #define ACLK_CCI_GRF 204
143 #define ACLK_CENTER 205
144 #define ACLK_CENTER_MAIN_NOC 206
145 #define ACLK_CENTER_PERI_NOC 207
147 #define ACLK_PERF_GPU 209
148 #define ACLK_GPU_GRF 210
149 #define ACLK_DMAC0_PERILP 211
150 #define ACLK_DMAC1_PERILP 212
151 #define ACLK_GMAC 213
152 #define ACLK_GMAC_NOC 214
153 #define ACLK_PERF_GMAC 215
154 #define ACLK_VOP0_NOC 216
155 #define ACLK_VOP0 217
156 #define ACLK_VOP1_NOC 218
157 #define ACLK_VOP1 219
159 #define ACLK_RGA_NOC 221
160 #define ACLK_HDCP 222
161 #define ACLK_HDCP_NOC 223
162 #define ACLK_HDCP22 224
164 #define ACLK_IEP_NOC 226
166 #define ACLK_VIO_NOC 228
167 #define ACLK_ISP0 229
168 #define ACLK_ISP1 230
169 #define ACLK_ISP0_NOC 231
170 #define ACLK_ISP1_NOC 232
171 #define ACLK_ISP0_WRAPPER 233
172 #define ACLK_ISP1_WRAPPER 234
173 #define ACLK_VCODEC 235
174 #define ACLK_VCODEC_NOC 236
176 #define ACLK_VDU_NOC 238
177 #define ACLK_PERI 239
178 #define ACLK_EMMC 240
179 #define ACLK_EMMC_CORE 241
180 #define ACLK_EMMC_NOC 242
181 #define ACLK_EMMC_GRF 243
182 #define ACLK_USB3 244
183 #define ACLK_USB3_NOC 245
184 #define ACLK_USB3OTG0 246
185 #define ACLK_USB3OTG1 247
186 #define ACLK_USB3_RKSOC_AXI_PERF 248
187 #define ACLK_USB3_GRF 249
189 #define ACLK_GIC_NOC 251
190 #define ACLK_GIC_ADB400_CORE_L_2_GIC 252
191 #define ACLK_GIC_ADB400_CORE_B_2_GIC 253
192 #define ACLK_GIC_ADB400_GIC_2_CORE_L 254
193 #define ACLK_GIC_ADB400_GIC_2_CORE_B 255
196 #define PCLK_PERIHP 320
197 #define PCLK_PERIHP_NOC 321
198 #define PCLK_PERILP0 322
199 #define PCLK_PERILP1 323
200 #define PCLK_PERILP1_NOC 324
201 #define PCLK_PERILP_SGRF 325
202 #define PCLK_PERIHP_GRF 326
203 #define PCLK_PCIE 327
204 #define PCLK_SGRF 328
205 #define PCLK_INTR_ARB 329
206 #define PCLK_CENTER_MAIN_NOC 330
208 #define PCLK_COREDBG_B 332
209 #define PCLK_COREDBG_L 333
210 #define PCLK_DBG_CXCS_PD_CORE_B 334
212 #define PCLK_GPIO2 336
213 #define PCLK_GPIO3 337
214 #define PCLK_GPIO4 338
216 #define PCLK_HSICPHY 340
217 #define PCLK_I2C1 341
218 #define PCLK_I2C2 342
219 #define PCLK_I2C3 343
220 #define PCLK_I2C5 344
221 #define PCLK_I2C6 345
222 #define PCLK_I2C7 346
223 #define PCLK_SPI0 347
224 #define PCLK_SPI1 348
225 #define PCLK_SPI2 349
226 #define PCLK_SPI4 350
227 #define PCLK_SPI5 351
228 #define PCLK_UART0 352
229 #define PCLK_UART1 353
230 #define PCLK_UART2 354
231 #define PCLK_UART3 355
232 #define PCLK_TSADC 356
233 #define PCLK_SARADC 357
234 #define PCLK_GMAC 358
235 #define PCLK_GMAC_NOC 359
236 #define PCLK_TIMER0 360
237 #define PCLK_TIMER1 361
239 #define PCLK_EDP_NOC 363
240 #define PCLK_EDP_CTRL 364
242 #define PCLK_VIO_NOC 366
243 #define PCLK_VIO_GRF 367
244 #define PCLK_MIPI_DSI0 368
245 #define PCLK_MIPI_DSI1 369
246 #define PCLK_HDCP 370
247 #define PCLK_HDCP_NOC 371
248 #define PCLK_HDMI_CTRL 372
249 #define PCLK_DP_CTRL 373
250 #define PCLK_HDCP22 374
251 #define PCLK_GASKET 375
253 #define PCLK_DDR_MON 377
254 #define PCLK_DDR_SGRF 378
255 #define PCLK_ISP1_WRAPPER 379
257 #define PCLK_EFUSE1024NS 381
258 #define PCLK_EFUSE1024S 382
259 #define PCLK_PMU_INTR_ARB 383
260 #define PCLK_MAILBOX0 384
263 #define HCLK_PERIHP 448
264 #define HCLK_PERILP0 449
265 #define HCLK_PERILP1 450
266 #define HCLK_PERILP0_NOC 451
267 #define HCLK_PERILP1_NOC 452
268 #define HCLK_M0_PERILP 453
269 #define HCLK_M0_PERILP_NOC 454
270 #define HCLK_AHB1TOM 455
271 #define HCLK_HOST0 456
272 #define HCLK_HOST0_ARB 457
273 #define HCLK_HOST1 458
274 #define HCLK_HOST1_ARB 459
275 #define HCLK_HSIC 460
277 #define HCLK_SDMMC 462
278 #define HCLK_SDMMC_NOC 463
279 #define HCLK_M_CRYPTO0 464
280 #define HCLK_M_CRYPTO1 465
281 #define HCLK_S_CRYPTO0 466
282 #define HCLK_S_CRYPTO1 467
283 #define HCLK_I2S0_8CH 468
284 #define HCLK_I2S1_8CH 469
285 #define HCLK_I2S2_8CH 470
286 #define HCLK_SPDIF 471
287 #define HCLK_VOP0_NOC 472
288 #define HCLK_VOP0 473
289 #define HCLK_VOP1_NOC 474
290 #define HCLK_VOP1 475
293 #define HCLK_IEP_NOC 478
294 #define HCLK_ISP0 479
295 #define HCLK_ISP1 480
296 #define HCLK_ISP0_NOC 481
297 #define HCLK_ISP1_NOC 482
298 #define HCLK_ISP0_WRAPPER 483
299 #define HCLK_ISP1_WRAPPER 484
301 #define HCLK_RGA_NOC 486
302 #define HCLK_HDCP 487
303 #define HCLK_HDCP_NOC 488
304 #define HCLK_HDCP22 489
305 #define HCLK_VCODEC 490
306 #define HCLK_VCODEC_NOC 491
308 #define HCLK_VDU_NOC 493
309 #define HCLK_SDIO 494
310 #define HCLK_SDIO_NOC 495
311 #define HCLK_SDIOAUDIO_NOC 496
313 #define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1)
315 /* pmu-clocks indices */
316 #define SCLK_32K_SUSPEND_PMU 521
317 #define SCLK_SPI3_PMU 522
318 #define SCLK_TIMER12_PMU 523
319 #define SCLK_TIMER13_PMU 524
320 #define SCLK_UART4_PMU 525
321 #define SCLK_PVTM_PMU 526
322 #define SCLK_WIFI_PMU 527
323 #define SCLK_I2C0_PMU 528
324 #define SCLK_I2C4_PMU 529
325 #define SCLK_I2C8_PMU 530
328 #define PCLK_PMUGRF_PMU 541
329 #define PCLK_INTMEM1_PMU 542
330 #define PCLK_GPIO0_PMU 543
331 #define PCLK_GPIO1_PMU 544
332 #define PCLK_SGRF_PMU 545
333 #define PCLK_NOC_PMU 546
334 #define PCLK_I2C0_PMU 547
335 #define PCLK_I2C4_PMU 548
336 #define PCLK_I2C8_PMU 549
337 #define PCLK_RKPWM_PMU 550
338 #define PCLK_SPI3_PMU 551
339 #define PCLK_TIMER_PMU 552
340 #define PCLK_MAILBOX_PMU 553
341 #define PCLK_UART4_PMU 554
342 #define PCLK_WDT_M0_PMU 555
344 #define FCLK_CM0S_PMU 560
345 #define SCLK_CM0S_PMU 561
346 #define HCLK_CM0S_PMU 562
347 #define DCLK_CM0S_PMU 563
348 #define PCLK_INTR_ARB_PMU 564
349 #define HCLK_NOC_PMU 565
351 #define CLKPMU_NR_CLKS (HCLK_NOC_PMU - SCLK_32K_SUSPEND_PMU + 1)
353 /* soft-reset indices */
355 /* cru_softrst_con0 */
356 #define SRST_CORE_L0 0
357 #define SRST_CORE_B0 1
358 #define SRST_CORE_PO_L0 2
359 #define SRST_CORE_PO_B0 3
365 #define SRST_A_CCIM0_NOC 9
366 #define SRST_A_CCIM1_NOC 10
367 #define SRST_DBG_NOC 11
369 /* cru_softrst_con1 */
370 #define SRST_CORE_L0_T 16
371 #define SRST_CORE_L1 17
372 #define SRST_CORE_L2 18
373 #define SRST_CORE_L3 19
374 #define SRST_CORE_PO_L0_T 20
375 #define SRST_CORE_PO_L1 21
376 #define SRST_CORE_PO_L2 22
377 #define SRST_CORE_PO_L3 23
378 #define SRST_A_ADB400_GIC2COREL 24
379 #define SRST_A_ADB400_COREL2GIC 25
380 #define SRST_P_DBG_L 26
381 #define SRST_L2_L_T 28
382 #define SRST_ADB_L_T 29
383 #define SRST_A_RKPERF_L 30
384 #define SRST_PVTM_CORE_L 31
386 /* cru_softrst_con2 */
387 #define SRST_CORE_B0_T 32
388 #define SRST_CORE_B1 33
389 #define SRST_CORE_PO_B0_T 36
390 #define SRST_CORE_PO_B1 37
391 #define SRST_A_ADB400_GIC2COREB 40
392 #define SRST_A_ADB400_COREB2GIC 41
393 #define SRST_P_DBG_B 42
394 #define SRST_L2_B_T 43
395 #define SRST_ADB_B_T 45
396 #define SRST_A_RKPERF_B 46
397 #define SRST_PVTM_CORE_B 47
399 /* cru_softrst_con3 */
400 #define SRST_A_CCI_T 50
401 #define SRST_A_CCIM0_NOC_T 51
402 #define SRST_A_CCIM1_NOC_T 52
403 #define SRST_A_ADB400M_PD_CORE_B_T 53
404 #define SRST_A_ADB400M_PD_CORE_L_T 54
405 #define SRST_DBG_NOC_T 55
406 #define SRST_DBG_CXCS 56
407 #define SRST_CCI_TRACE 57
408 #define SRST_P_CCI_GRF 58
410 /* cru_softrst_con4 */
411 #define SRST_A_CENTER_MAIN_NOC 64
412 #define SRST_A_CENTER_PERI_NOC 65
413 #define SRST_P_CENTER_MAIN 66
414 #define SRST_P_DDRMON 67
415 #define SRST_P_CIC 68
416 #define SRST_P_CENTER_SGRF 69
417 #define SRST_DDR0_MSCH 70
418 #define SRST_DDRCFG0_MSCH 71
420 #define SRST_DDRPHY0 73
421 #define SRST_DDR1_MSCH 74
422 #define SRST_DDRCFG1_MSCH 75
424 #define SRST_DDRPHY1 77
425 #define SRST_DDR_CIC 78
426 #define SRST_PVTM_DDR 79
428 /* cru_softrst_con5 */
429 #define SRST_A_VCODEC_NOC 80
430 #define SRST_A_VCODEC 81
431 #define SRST_H_VCODEC_NOC 82
432 #define SRST_H_VCODEC 83
433 #define SRST_A_VDU_NOC 88
434 #define SRST_A_VDU 89
435 #define SRST_H_VDU_NOC 90
436 #define SRST_H_VDU 91
437 #define SRST_VDU_CORE 92
438 #define SRST_VDU_CA 93
440 /* cru_softrst_con6 */
441 #define SRST_A_IEP_NOC 96
442 #define SRST_A_VOP_IEP 97
443 #define SRST_A_IEP 98
444 #define SRST_H_IEP_NOC 99
445 #define SRST_H_IEP 100
446 #define SRST_A_RGA_NOC 102
447 #define SRST_A_RGA 103
448 #define SRST_H_RGA_NOC 104
449 #define SRST_H_RGA 105
450 #define SRST_RGA_CORE 106
451 #define SRST_EMMC_NOC 108
452 #define SRST_EMMC 109
453 #define SRST_EMMC_GRF 110
455 /* cru_softrst_con7 */
456 #define SRST_A_PERIHP_NOC 112
457 #define SRST_P_PERIHP_GRF 113
458 #define SRST_H_PERIHP_NOC 114
459 #define SRST_USBHOST0 115
460 #define SRST_HOSTC0_AUX 116
461 #define SRST_HOST0_ARB 117
462 #define SRST_USBHOST1 118
463 #define SRST_HOSTC1_AUX 119
464 #define SRST_HOST1_ARB 120
465 #define SRST_SDIO0 121
466 #define SRST_SDMMC 122
467 #define SRST_HSIC 123
468 #define SRST_HSIC_AUX 124
469 #define SRST_AHB1TOM 125
470 #define SRST_P_PERIHP_NOC 126
471 #define SRST_HSICPHY 127
473 /* cru_softrst_con8 */
474 #define SRST_A_PCIE 128
475 #define SRST_P_PCIE 129
476 #define SRST_PCIE_CORE 130
477 #define SRST_PCIE_MGMT 131
478 #define SRST_PCIE_MGMT_STICKY 132
479 #define SRST_PCIE_PIPE 133
480 #define SRST_PCIE_PM 134
481 #define SRST_PCIEPHY 135
482 #define SRST_A_GMAC_NOC 136
483 #define SRST_A_GMAC 137
484 #define SRST_P_GMAC_NOC 138
485 #define SRST_P_GMAC_GRF 140
486 #define SRST_HSICPHY_POR 142
487 #define SRST_HSICPHY_UTMI 143
489 /* cru_softrst_con9 */
490 #define SRST_USB2PHY0_POR 144
491 #define SRST_USB2PHY0_UTMI_PORT0 145
492 #define SRST_USB2PHY0_UTMI_PORT1 146
493 #define SRST_USB2PHY0_EHCIPHY 147
494 #define SRST_UPHY0_PIPE_L00 148
495 #define SRST_UPHY0 149
496 #define SRST_UPHY0_TCPDPWRUP 150
497 #define SRST_USB2PHY1_POR 152
498 #define SRST_USB2PHY1_UTMI_PORT0 153
499 #define SRST_USB2PHY1_UTMI_PORT1 154
500 #define SRST_USB2PHY1_EHCIPHY 155
501 #define SRST_UPHY1_PIPE_L00 156
502 #define SRST_UPHY1 157
503 #define SRST_UPHY1_TCPDPWRUP 158
505 /* cru_softrst_con10 */
506 #define SRST_A_PERILP0_NOC 160
507 #define SRST_A_DCF 161
508 #define SRST_GIC500 162
509 #define SRST_DMAC0_PERILP0 163
510 #define SRST_DMAC1_PERILP0 164
511 #define SRST_TZMA 165
512 #define SRST_INTMEM 166
513 #define SRST_ADB400_MST0 167
514 #define SRST_ADB400_MST1 168
515 #define SRST_ADB400_SLV0 169
516 #define SRST_ADB400_SLV1 170
517 #define SRST_H_PERILP0 171
518 #define SRST_H_PERILP0_NOC 172
520 #define SRST_CRYPTO_S 174
521 #define SRST_CRYPTO_M 175
523 /* cru_softrst_con11 */
524 #define SRST_P_DCF 176
525 #define SRST_CM0S_NOC 177
526 #define SRST_CM0S 178
527 #define SRST_CM0S_DBG 179
528 #define SRST_CM0S_PO 180
529 #define SRST_CRYPTO 181
530 #define SRST_P_PERILP1_SGRF 182
531 #define SRST_P_PERILP1_GRF 183
532 #define SRST_CRYPTO1_S 184
533 #define SRST_CRYPTO1_M 185
534 #define SRST_CRYPTO1 186
535 #define SRST_GIC_NOC 188
536 #define SRST_SD_NOC 189
537 #define SRST_SDIOAUDIO_BRG 190
539 /* cru_softrst_con12 */
540 #define SRST_H_PERILP1 192
541 #define SRST_H_PERILP1_NOC 193
542 #define SRST_H_I2S0_8CH 194
543 #define SRST_H_I2S1_8CH 195
544 #define SRST_H_I2S2_8CH 196
545 #define SRST_H_SPDIF_8CH 197
546 #define SRST_P_PERILP1_NOC 198
547 #define SRST_P_EFUSE_1024 199
548 #define SRST_P_EFUSE_1024S 200
549 #define SRST_P_I2C0 201
550 #define SRST_P_I2C1 202
551 #define SRST_P_I2C2 203
552 #define SRST_P_I2C3 204
553 #define SRST_P_I2C4 205
554 #define SRST_P_I2C5 206
555 #define SRST_P_MAILBOX0 207
557 /* cru_softrst_con13 */
558 #define SRST_P_UART0 208
559 #define SRST_P_UART1 209
560 #define SRST_P_UART2 210
561 #define SRST_P_UART3 211
562 #define SRST_P_SARADC 212
563 #define SRST_P_TSADC 213
564 #define SRST_P_SPI0 214
565 #define SRST_P_SPI1 215
566 #define SRST_P_SPI2 216
567 #define SRST_P_SPI3 217
568 #define SRST_P_SPI4 218
569 #define SRST_SPI0 219
570 #define SRST_SPI1 220
571 #define SRST_SPI2 221
572 #define SRST_SPI3 222
573 #define SRST_SPI4 223
575 /* cru_softrst_con14 */
576 #define SRST_I2S0_8CH 224
577 #define SRST_I2S1_8CH 225
578 #define SRST_I2S2_8CH 226
579 #define SRST_SPDIF_8CH 227
580 #define SRST_UART0 228
581 #define SRST_UART1 229
582 #define SRST_UART2 230
583 #define SRST_UART3 231
584 #define SRST_TSADC 232
585 #define SRST_I2C0 233
586 #define SRST_I2C1 234
587 #define SRST_I2C2 235
588 #define SRST_I2C3 236
589 #define SRST_I2C4 237
590 #define SRST_I2C5 238
591 #define SRST_SDIOAUDIO_NOC 239
593 /* cru_softrst_con15 */
594 #define SRST_A_VIO_NOC 240
595 #define SRST_A_HDCP_NOC 241
596 #define SRST_A_HDCP 242
597 #define SRST_H_HDCP_NOC 243
598 #define SRST_H_HDCP 244
599 #define SRST_P_HDCP_NOC 245
600 #define SRST_P_HDCP 246
601 #define SRST_P_HDMI_CTRL 247
602 #define SRST_P_DP_CTRL 248
603 #define SRST_S_DP_CTRL 249
604 #define SRST_C_DP_CTRL 250
605 #define SRST_P_MIPI_DSI0 251
606 #define SRST_P_MIPI_DSI1 252
607 #define SRST_DP_CORE 253
608 #define SRST_DP_I2S 254
610 /* cru_softrst_con16 */
611 #define SRST_GASKET 256
612 #define SRST_VIO_GRF 258
613 #define SRST_DPTX_SPDIF_REC 259
614 #define SRST_HDMI_CTRL 260
615 #define SRST_HDCP_CTRL 261
616 #define SRST_A_ISP0_NOC 262
617 #define SRST_A_ISP1_NOC 263
618 #define SRST_H_ISP0_NOC 266
619 #define SRST_H_ISP1_NOC 267
620 #define SRST_H_ISP0 268
621 #define SRST_H_ISP1 269
622 #define SRST_ISP0 270
623 #define SRST_ISP1 271
625 /* cru_softrst_con17 */
626 #define SRST_A_VOP0_NOC 272
627 #define SRST_A_VOP1_NOC 273
628 #define SRST_A_VOP0 274
629 #define SRST_A_VOP1 275
630 #define SRST_H_VOP0_NOC 276
631 #define SRST_H_VOP1_NOC 277
632 #define SRST_H_VOP0 278
633 #define SRST_H_VOP1 279
634 #define SRST_D_VOP0 280
635 #define SRST_D_VOP1 281
636 #define SRST_VOP0_PWM 282
637 #define SRST_VOP1_PWM 283
638 #define SRST_P_EDP_NOC 284
639 #define SRST_P_EDP_CTRL 285
641 /* cru_softrst_con18 */
642 #define SRST_A_GPU_NOC 289
643 #define SRST_A_GPU_GRF 290
644 #define SRST_PVTM_GPU 291
645 #define SRST_A_USB3_NOC 292
646 #define SRST_A_USB3_OTG0 293
647 #define SRST_A_USB3_OTG1 294
648 #define SRST_A_USB3_GRF 295
651 /* cru_softrst_con19 */
652 #define SRST_P_TIMER0_5 304
653 #define SRST_TIMER0 305
654 #define SRST_TIMER1 306
655 #define SRST_TIMER2 307
656 #define SRST_TIMER3 308
657 #define SRST_TIMER4 309
658 #define SRST_TIMER5 310
659 #define SRST_P_TIMER6_11 311
660 #define SRST_TIMER6 312
661 #define SRST_TIMER7 313
662 #define SRST_TIMER8 314
663 #define SRST_TIMER9 315
664 #define SRST_TIMER10 316
665 #define SRST_TIMER11 317
666 #define SRST_P_INTR_ARB_PMU 318
667 #define SRST_P_ALIVE_SGRF 319
669 /* cru_softrst_con20 */
670 #define SRST_P_GPIO2 320
671 #define SRST_P_GPIO3 321
672 #define SRST_P_GPIO4 322
673 #define SRST_P_GRF 323
674 #define SRST_P_ALIVE_NOC 324
675 #define SRST_P_WDT0 325
676 #define SRST_P_WDT1 326
677 #define SRST_P_INTR_ARB 327
678 #define SRST_P_UPHY0_DPTX 328
679 #define SRST_P_UPHY0_APB 330
680 #define SRST_P_UPHY0_TCPHY 332
681 #define SRST_P_UPHY1_TCPHY 333
682 #define SRST_P_UPHY0_TCPDCTRL 334
683 #define SRST_P_UPHY1_TCPDCTRL 335
685 /* pmu soft-reset indices */
687 /* pmu_cru_softrst_con0 */
689 #define SRST_P_INTMEM 1
690 #define SRST_H_CM0S 2
691 #define SRST_H_CM0S_NOC 3
692 #define SRST_DBG_CM0S 4
693 #define SRST_PO_CM0S 5
694 #define SRST_P_SPI6 6
696 #define SRST_P_TIMER_0_1 8
697 #define SRST_P_TIMER_0 9
698 #define SRST_P_TIMER_1 10
699 #define SRST_P_UART4 11
700 #define SRST_UART4 12
701 #define SRST_P_WDT 13
703 /* pmu_cru_softrst_con1 */
704 #define SRST_P_I2C6 16
705 #define SRST_P_I2C7 17
706 #define SRST_P_I2C8 18
707 #define SRST_P_MAILBOX 19
708 #define SRST_P_RKPWM 20
709 #define SRST_P_PMUGRF 21
710 #define SRST_P_SGRF 22
711 #define SRST_P_GPIO0 23
712 #define SRST_P_GPIO1 24
713 #define SRST_P_CRU 25
714 #define SRST_P_INTR 26