2 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
3 * Author: Xing Zheng <zhengxing@rock-chips.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
17 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
31 /* sclk gates (special clocks) */
47 #define SCLK_SARADC 80
52 #define SCLK_SPDIF_8CH 85
53 #define SCLK_I2S0_8CH 86
54 #define SCLK_I2S1_8CH 87
55 #define SCLK_I2S2_8CH 88
56 #define SCLK_I2S_8CH_OUT 89
57 #define SCLK_TIMER00 90
58 #define SCLK_TIMER01 91
59 #define SCLK_TIMER02 92
60 #define SCLK_TIMER03 93
61 #define SCLK_TIMER04 94
62 #define SCLK_TIMER05 95
63 #define SCLK_TIMER06 96
64 #define SCLK_TIMER07 97
65 #define SCLK_TIMER08 98
66 #define SCLK_TIMER09 99
67 #define SCLK_TIMER10 100
68 #define SCLK_TIMER11 101
69 #define SCLK_MACREF 102
70 #define SCLK_MAC_RX 103
71 #define SCLK_MAC_TX 104
73 #define SCLK_MACREF_OUT 106
74 #define SCLK_VOP0_PWM 107
75 #define SCLK_VOP1_PWM 108
79 #define SCLK_HDMI_CEC 112
80 #define SCLK_HDMI_SFR 113
81 #define SCLK_DP_CORE 114
82 #define SCLK_PVTM_CORE_L 115
83 #define SCLK_PVTM_CORE_B 116
84 #define SCLK_PVTM_GPU 117
85 #define SCLK_PVTM_DDR 118
86 #define SCLK_MIPIDPHY_REF 119
87 #define SCLK_MIPIDPHY_CFG 120
88 #define SCLK_HSICPHY 121
89 #define SCLK_USBPHY480M 122
90 #define SCLK_USB2PHY0_REF 123
91 #define SCLK_USB2PHY1_REF 124
92 #define SCLK_UPHY0_TCPDPHY_REF 125
93 #define SCLK_UPHY0_TCPDCORE 126
94 #define SCLK_UPHY1_TCPDPHY_REF 127
95 #define SCLK_UPHY1_TCPDCORE 128
96 #define SCLK_USB3OTG0_REF 129
97 #define SCLK_USB3OTG1_REF 130
98 #define SCLK_USB3OTG0_SUSPEND 131
99 #define SCLK_USB3OTG1_SUSPEND 132
100 #define SCLK_CRYPTO0 133
101 #define SCLK_CRYPTO1 134
102 #define SCLK_CCI_TRACE 135
104 #define SCLK_CIF_OUT 137
105 #define SCLK_PCIEPHY_REF 138
106 #define SCLK_PCIE_CORE 139
107 #define SCLK_M0_PERILP 140
108 #define SCLK_M0_PERILP_DEC 141
109 #define SCLK_CM0S 142
110 #define SCLK_DBG_NOC 143
111 #define SCLK_DBG_PD_CORE_B 144
112 #define SCLK_DBG_PD_CORE_L 145
113 #define SCLK_DFIMON0_TIMER 146
114 #define SCLK_DFIMON1_TIMER 147
115 #define SCLK_INTMEM0 148
116 #define SCLK_INTMEM1 149
117 #define SCLK_INTMEM2 150
118 #define SCLK_INTMEM3 151
119 #define SCLK_INTMEM4 152
120 #define SCLK_INTMEM5 153
121 #define SCLK_SDMMC_DRV 154
122 #define SCLK_SDMMC_SAMPLE 155
123 #define SCLK_SDIO_DRV 156
124 #define SCLK_SDIO_SAMPLE 157
125 #define SCLK_VDU_CORE 158
126 #define SCLK_VDU_CA 159
127 #define SCLK_PCIE_PM 160
128 #define SCLK_SPDIF_REC_DPTX 161
129 #define SCLK_DPHY_PLL 162
130 #define SCLK_DPHY_TX0_CFG 163
131 #define SCLK_DPHY_TX1RX1_CFG 164
132 #define SCLK_DPHY_RX0_CFG 165
134 #define DCLK_VOP0 180
135 #define DCLK_VOP1 181
136 #define DCLK_M0_PERILP 182
139 #define ACLK_PERIHP 192
140 #define ACLK_PERIHP_NOC 193
141 #define ACLK_PERILP0 194
142 #define ACLK_PERILP0_NOC 195
143 #define ACLK_PERF_PCIE 196
144 #define ACLK_PCIE 197
145 #define ACLK_INTMEM 198
146 #define ACLK_TZMA 199
149 #define ACLK_CCI_NOC0 202
150 #define ACLK_CCI_NOC1 203
151 #define ACLK_CCI_GRF 204
152 #define ACLK_CENTER 205
153 #define ACLK_CENTER_MAIN_NOC 206
154 #define ACLK_CENTER_PERI_NOC 207
156 #define ACLK_PERF_GPU 209
157 #define ACLK_GPU_GRF 210
158 #define ACLK_DMAC0_PERILP 211
159 #define ACLK_DMAC1_PERILP 212
160 #define ACLK_GMAC 213
161 #define ACLK_GMAC_NOC 214
162 #define ACLK_PERF_GMAC 215
163 #define ACLK_VOP0_NOC 216
164 #define ACLK_VOP0 217
165 #define ACLK_VOP1_NOC 218
166 #define ACLK_VOP1 219
168 #define ACLK_RGA_NOC 221
169 #define ACLK_HDCP 222
170 #define ACLK_HDCP_NOC 223
171 #define ACLK_HDCP22 224
173 #define ACLK_IEP_NOC 226
175 #define ACLK_VIO_NOC 228
176 #define ACLK_ISP0 229
177 #define ACLK_ISP1 230
178 #define ACLK_ISP0_NOC 231
179 #define ACLK_ISP1_NOC 232
180 #define ACLK_ISP0_WRAPPER 233
181 #define ACLK_ISP1_WRAPPER 234
182 #define ACLK_VCODEC 235
183 #define ACLK_VCODEC_NOC 236
185 #define ACLK_VDU_NOC 238
186 #define ACLK_PERI 239
187 #define ACLK_EMMC 240
188 #define ACLK_EMMC_CORE 241
189 #define ACLK_EMMC_NOC 242
190 #define ACLK_EMMC_GRF 243
191 #define ACLK_USB3 244
192 #define ACLK_USB3_NOC 245
193 #define ACLK_USB3OTG0 246
194 #define ACLK_USB3OTG1 247
195 #define ACLK_USB3_RKSOC_AXI_PERF 248
196 #define ACLK_USB3_GRF 249
198 #define ACLK_GIC_NOC 251
199 #define ACLK_GIC_ADB400_CORE_L_2_GIC 252
200 #define ACLK_GIC_ADB400_CORE_B_2_GIC 253
201 #define ACLK_GIC_ADB400_GIC_2_CORE_L 254
202 #define ACLK_GIC_ADB400_GIC_2_CORE_B 255
203 #define ACLK_CORE_ADB400_CORE_L_2_CCI500 256
204 #define ACLK_CORE_ADB400_CORE_B_2_CCI500 257
205 #define ACLK_ADB400M_PD_CORE_L 258
206 #define ACLK_ADB400M_PD_CORE_B 259
207 #define ACLK_PERF_CORE_L 260
208 #define ACLK_PERF_CORE_B 261
211 #define PCLK_PERIHP 320
212 #define PCLK_PERIHP_NOC 321
213 #define PCLK_PERILP0 322
214 #define PCLK_PERILP1 323
215 #define PCLK_PERILP1_NOC 324
216 #define PCLK_PERILP_SGRF 325
217 #define PCLK_PERIHP_GRF 326
218 #define PCLK_PCIE 327
219 #define PCLK_SGRF 328
220 #define PCLK_INTR_ARB 329
221 #define PCLK_CENTER_MAIN_NOC 330
223 #define PCLK_COREDBG_B 332
224 #define PCLK_COREDBG_L 333
225 #define PCLK_DBG_CXCS_PD_CORE_B 334
227 #define PCLK_GPIO2 336
228 #define PCLK_GPIO3 337
229 #define PCLK_GPIO4 338
231 #define PCLK_HSICPHY 340
232 #define PCLK_I2C1 341
233 #define PCLK_I2C2 342
234 #define PCLK_I2C3 343
235 #define PCLK_I2C5 344
236 #define PCLK_I2C6 345
237 #define PCLK_I2C7 346
238 #define PCLK_SPI0 347
239 #define PCLK_SPI1 348
240 #define PCLK_SPI2 349
241 #define PCLK_SPI4 350
242 #define PCLK_SPI5 351
243 #define PCLK_UART0 352
244 #define PCLK_UART1 353
245 #define PCLK_UART2 354
246 #define PCLK_UART3 355
247 #define PCLK_TSADC 356
248 #define PCLK_SARADC 357
249 #define PCLK_GMAC 358
250 #define PCLK_GMAC_NOC 359
251 #define PCLK_TIMER0 360
252 #define PCLK_TIMER1 361
254 #define PCLK_EDP_NOC 363
255 #define PCLK_EDP_CTRL 364
257 #define PCLK_VIO_NOC 366
258 #define PCLK_VIO_GRF 367
259 #define PCLK_MIPI_DSI0 368
260 #define PCLK_MIPI_DSI1 369
261 #define PCLK_HDCP 370
262 #define PCLK_HDCP_NOC 371
263 #define PCLK_HDMI_CTRL 372
264 #define PCLK_DP_CTRL 373
265 #define PCLK_HDCP22 374
266 #define PCLK_GASKET 375
268 #define PCLK_DDR_MON 377
269 #define PCLK_DDR_SGRF 378
270 #define PCLK_ISP1_WRAPPER 379
272 #define PCLK_EFUSE1024NS 381
273 #define PCLK_EFUSE1024S 382
274 #define PCLK_PMU_INTR_ARB 383
275 #define PCLK_MAILBOX0 384
276 #define PCLK_USBPHY_MUX_G 385
277 #define PCLK_UPHY0_TCPHY_G 386
278 #define PCLK_UPHY0_TCPD_G 387
279 #define PCLK_UPHY1_TCPHY_G 388
280 #define PCLK_UPHY1_TCPD_G 389
283 #define HCLK_PERIHP 448
284 #define HCLK_PERILP0 449
285 #define HCLK_PERILP1 450
286 #define HCLK_PERILP0_NOC 451
287 #define HCLK_PERILP1_NOC 452
288 #define HCLK_M0_PERILP 453
289 #define HCLK_M0_PERILP_NOC 454
290 #define HCLK_AHB1TOM 455
291 #define HCLK_HOST0 456
292 #define HCLK_HOST0_ARB 457
293 #define HCLK_HOST1 458
294 #define HCLK_HOST1_ARB 459
295 #define HCLK_HSIC 460
297 #define HCLK_SDMMC 462
298 #define HCLK_SDMMC_NOC 463
299 #define HCLK_M_CRYPTO0 464
300 #define HCLK_M_CRYPTO1 465
301 #define HCLK_S_CRYPTO0 466
302 #define HCLK_S_CRYPTO1 467
303 #define HCLK_I2S0_8CH 468
304 #define HCLK_I2S1_8CH 469
305 #define HCLK_I2S2_8CH 470
306 #define HCLK_SPDIF 471
307 #define HCLK_VOP0_NOC 472
308 #define HCLK_VOP0 473
309 #define HCLK_VOP1_NOC 474
310 #define HCLK_VOP1 475
313 #define HCLK_IEP_NOC 478
314 #define HCLK_ISP0 479
315 #define HCLK_ISP1 480
316 #define HCLK_ISP0_NOC 481
317 #define HCLK_ISP1_NOC 482
318 #define HCLK_ISP0_WRAPPER 483
319 #define HCLK_ISP1_WRAPPER 484
321 #define HCLK_RGA_NOC 486
322 #define HCLK_HDCP 487
323 #define HCLK_HDCP_NOC 488
324 #define HCLK_HDCP22 489
325 #define HCLK_VCODEC 490
326 #define HCLK_VCODEC_NOC 491
328 #define HCLK_VDU_NOC 493
329 #define HCLK_SDIO 494
330 #define HCLK_SDIO_NOC 495
331 #define HCLK_SDIOAUDIO_NOC 496
333 #define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1)
335 /* pmu-clocks indices */
336 #define SCLK_32K_SUSPEND_PMU 521
337 #define SCLK_SPI3_PMU 522
338 #define SCLK_TIMER12_PMU 523
339 #define SCLK_TIMER13_PMU 524
340 #define SCLK_UART4_PMU 525
341 #define SCLK_PVTM_PMU 526
342 #define SCLK_WIFI_PMU 527
343 #define SCLK_I2C0_PMU 528
344 #define SCLK_I2C4_PMU 529
345 #define SCLK_I2C8_PMU 530
348 #define PCLK_PMUGRF_PMU 541
349 #define PCLK_INTMEM1_PMU 542
350 #define PCLK_GPIO0_PMU 543
351 #define PCLK_GPIO1_PMU 544
352 #define PCLK_SGRF_PMU 545
353 #define PCLK_NOC_PMU 546
354 #define PCLK_I2C0_PMU 547
355 #define PCLK_I2C4_PMU 548
356 #define PCLK_I2C8_PMU 549
357 #define PCLK_RKPWM_PMU 550
358 #define PCLK_SPI3_PMU 551
359 #define PCLK_TIMER_PMU 552
360 #define PCLK_MAILBOX_PMU 553
361 #define PCLK_UART4_PMU 554
362 #define PCLK_WDT_M0_PMU 555
364 #define FCLK_CM0S_PMU 560
365 #define SCLK_CM0S_PMU 561
366 #define HCLK_CM0S_PMU 562
367 #define DCLK_CM0S_PMU 563
368 #define PCLK_INTR_ARB_PMU 564
369 #define HCLK_NOC_PMU 565
371 #define CLKPMU_NR_CLKS (HCLK_NOC_PMU - SCLK_32K_SUSPEND_PMU + 1)
373 /* soft-reset indices */
375 /* cru_softrst_con0 */
376 #define SRST_CORE_L0 0
377 #define SRST_CORE_B0 1
378 #define SRST_CORE_PO_L0 2
379 #define SRST_CORE_PO_B0 3
385 #define SRST_A_CCIM0_NOC 9
386 #define SRST_A_CCIM1_NOC 10
387 #define SRST_DBG_NOC 11
389 /* cru_softrst_con1 */
390 #define SRST_CORE_L0_T 16
391 #define SRST_CORE_L1 17
392 #define SRST_CORE_L2 18
393 #define SRST_CORE_L3 19
394 #define SRST_CORE_PO_L0_T 20
395 #define SRST_CORE_PO_L1 21
396 #define SRST_CORE_PO_L2 22
397 #define SRST_CORE_PO_L3 23
398 #define SRST_A_ADB400_GIC2COREL 24
399 #define SRST_A_ADB400_COREL2GIC 25
400 #define SRST_P_DBG_L 26
401 #define SRST_L2_L_T 28
402 #define SRST_ADB_L_T 29
403 #define SRST_A_RKPERF_L 30
404 #define SRST_PVTM_CORE_L 31
406 /* cru_softrst_con2 */
407 #define SRST_CORE_B0_T 32
408 #define SRST_CORE_B1 33
409 #define SRST_CORE_PO_B0_T 36
410 #define SRST_CORE_PO_B1 37
411 #define SRST_A_ADB400_GIC2COREB 40
412 #define SRST_A_ADB400_COREB2GIC 41
413 #define SRST_P_DBG_B 42
414 #define SRST_L2_B_T 43
415 #define SRST_ADB_B_T 45
416 #define SRST_A_RKPERF_B 46
417 #define SRST_PVTM_CORE_B 47
419 /* cru_softrst_con3 */
420 #define SRST_A_CCI_T 50
421 #define SRST_A_CCIM0_NOC_T 51
422 #define SRST_A_CCIM1_NOC_T 52
423 #define SRST_A_ADB400M_PD_CORE_B_T 53
424 #define SRST_A_ADB400M_PD_CORE_L_T 54
425 #define SRST_DBG_NOC_T 55
426 #define SRST_DBG_CXCS 56
427 #define SRST_CCI_TRACE 57
428 #define SRST_P_CCI_GRF 58
430 /* cru_softrst_con4 */
431 #define SRST_A_CENTER_MAIN_NOC 64
432 #define SRST_A_CENTER_PERI_NOC 65
433 #define SRST_P_CENTER_MAIN 66
434 #define SRST_P_DDRMON 67
435 #define SRST_P_CIC 68
436 #define SRST_P_CENTER_SGRF 69
437 #define SRST_DDR0_MSCH 70
438 #define SRST_DDRCFG0_MSCH 71
440 #define SRST_DDRPHY0 73
441 #define SRST_DDR1_MSCH 74
442 #define SRST_DDRCFG1_MSCH 75
444 #define SRST_DDRPHY1 77
445 #define SRST_DDR_CIC 78
446 #define SRST_PVTM_DDR 79
448 /* cru_softrst_con5 */
449 #define SRST_A_VCODEC_NOC 80
450 #define SRST_A_VCODEC 81
451 #define SRST_H_VCODEC_NOC 82
452 #define SRST_H_VCODEC 83
453 #define SRST_A_VDU_NOC 88
454 #define SRST_A_VDU 89
455 #define SRST_H_VDU_NOC 90
456 #define SRST_H_VDU 91
457 #define SRST_VDU_CORE 92
458 #define SRST_VDU_CA 93
460 /* cru_softrst_con6 */
461 #define SRST_A_IEP_NOC 96
462 #define SRST_A_VOP_IEP 97
463 #define SRST_A_IEP 98
464 #define SRST_H_IEP_NOC 99
465 #define SRST_H_IEP 100
466 #define SRST_A_RGA_NOC 102
467 #define SRST_A_RGA 103
468 #define SRST_H_RGA_NOC 104
469 #define SRST_H_RGA 105
470 #define SRST_RGA_CORE 106
471 #define SRST_EMMC_NOC 108
472 #define SRST_EMMC 109
473 #define SRST_EMMC_GRF 110
475 /* cru_softrst_con7 */
476 #define SRST_A_PERIHP_NOC 112
477 #define SRST_P_PERIHP_GRF 113
478 #define SRST_H_PERIHP_NOC 114
479 #define SRST_USBHOST0 115
480 #define SRST_HOSTC0_AUX 116
481 #define SRST_HOST0_ARB 117
482 #define SRST_USBHOST1 118
483 #define SRST_HOSTC1_AUX 119
484 #define SRST_HOST1_ARB 120
485 #define SRST_SDIO0 121
486 #define SRST_SDMMC 122
487 #define SRST_HSIC 123
488 #define SRST_HSIC_AUX 124
489 #define SRST_AHB1TOM 125
490 #define SRST_P_PERIHP_NOC 126
491 #define SRST_HSICPHY 127
493 /* cru_softrst_con8 */
494 #define SRST_A_PCIE 128
495 #define SRST_P_PCIE 129
496 #define SRST_PCIE_CORE 130
497 #define SRST_PCIE_MGMT 131
498 #define SRST_PCIE_MGMT_STICKY 132
499 #define SRST_PCIE_PIPE 133
500 #define SRST_PCIE_PM 134
501 #define SRST_PCIEPHY 135
502 #define SRST_A_GMAC_NOC 136
503 #define SRST_A_GMAC 137
504 #define SRST_P_GMAC_NOC 138
505 #define SRST_P_GMAC_GRF 140
506 #define SRST_HSICPHY_POR 142
507 #define SRST_HSICPHY_UTMI 143
509 /* cru_softrst_con9 */
510 #define SRST_USB2PHY0_POR 144
511 #define SRST_USB2PHY0_UTMI_PORT0 145
512 #define SRST_USB2PHY0_UTMI_PORT1 146
513 #define SRST_USB2PHY0_EHCIPHY 147
514 #define SRST_UPHY0_PIPE_L00 148
515 #define SRST_UPHY0 149
516 #define SRST_UPHY0_TCPDPWRUP 150
517 #define SRST_USB2PHY1_POR 152
518 #define SRST_USB2PHY1_UTMI_PORT0 153
519 #define SRST_USB2PHY1_UTMI_PORT1 154
520 #define SRST_USB2PHY1_EHCIPHY 155
521 #define SRST_UPHY1_PIPE_L00 156
522 #define SRST_UPHY1 157
523 #define SRST_UPHY1_TCPDPWRUP 158
525 /* cru_softrst_con10 */
526 #define SRST_A_PERILP0_NOC 160
527 #define SRST_A_DCF 161
528 #define SRST_GIC500 162
529 #define SRST_DMAC0_PERILP0 163
530 #define SRST_DMAC1_PERILP0 164
531 #define SRST_TZMA 165
532 #define SRST_INTMEM 166
533 #define SRST_ADB400_MST0 167
534 #define SRST_ADB400_MST1 168
535 #define SRST_ADB400_SLV0 169
536 #define SRST_ADB400_SLV1 170
537 #define SRST_H_PERILP0 171
538 #define SRST_H_PERILP0_NOC 172
540 #define SRST_CRYPTO_S 174
541 #define SRST_CRYPTO_M 175
543 /* cru_softrst_con11 */
544 #define SRST_P_DCF 176
545 #define SRST_CM0S_NOC 177
546 #define SRST_CM0S 178
547 #define SRST_CM0S_DBG 179
548 #define SRST_CM0S_PO 180
549 #define SRST_CRYPTO 181
550 #define SRST_P_PERILP1_SGRF 182
551 #define SRST_P_PERILP1_GRF 183
552 #define SRST_CRYPTO1_S 184
553 #define SRST_CRYPTO1_M 185
554 #define SRST_CRYPTO1 186
555 #define SRST_GIC_NOC 188
556 #define SRST_SD_NOC 189
557 #define SRST_SDIOAUDIO_BRG 190
559 /* cru_softrst_con12 */
560 #define SRST_H_PERILP1 192
561 #define SRST_H_PERILP1_NOC 193
562 #define SRST_H_I2S0_8CH 194
563 #define SRST_H_I2S1_8CH 195
564 #define SRST_H_I2S2_8CH 196
565 #define SRST_H_SPDIF_8CH 197
566 #define SRST_P_PERILP1_NOC 198
567 #define SRST_P_EFUSE_1024 199
568 #define SRST_P_EFUSE_1024S 200
569 #define SRST_P_I2C0 201
570 #define SRST_P_I2C1 202
571 #define SRST_P_I2C2 203
572 #define SRST_P_I2C3 204
573 #define SRST_P_I2C4 205
574 #define SRST_P_I2C5 206
575 #define SRST_P_MAILBOX0 207
577 /* cru_softrst_con13 */
578 #define SRST_P_UART0 208
579 #define SRST_P_UART1 209
580 #define SRST_P_UART2 210
581 #define SRST_P_UART3 211
582 #define SRST_P_SARADC 212
583 #define SRST_P_TSADC 213
584 #define SRST_P_SPI0 214
585 #define SRST_P_SPI1 215
586 #define SRST_P_SPI2 216
587 #define SRST_P_SPI3 217
588 #define SRST_P_SPI4 218
589 #define SRST_SPI0 219
590 #define SRST_SPI1 220
591 #define SRST_SPI2 221
592 #define SRST_SPI3 222
593 #define SRST_SPI4 223
595 /* cru_softrst_con14 */
596 #define SRST_I2S0_8CH 224
597 #define SRST_I2S1_8CH 225
598 #define SRST_I2S2_8CH 226
599 #define SRST_SPDIF_8CH 227
600 #define SRST_UART0 228
601 #define SRST_UART1 229
602 #define SRST_UART2 230
603 #define SRST_UART3 231
604 #define SRST_TSADC 232
605 #define SRST_I2C0 233
606 #define SRST_I2C1 234
607 #define SRST_I2C2 235
608 #define SRST_I2C3 236
609 #define SRST_I2C4 237
610 #define SRST_I2C5 238
611 #define SRST_SDIOAUDIO_NOC 239
613 /* cru_softrst_con15 */
614 #define SRST_A_VIO_NOC 240
615 #define SRST_A_HDCP_NOC 241
616 #define SRST_A_HDCP 242
617 #define SRST_H_HDCP_NOC 243
618 #define SRST_H_HDCP 244
619 #define SRST_P_HDCP_NOC 245
620 #define SRST_P_HDCP 246
621 #define SRST_P_HDMI_CTRL 247
622 #define SRST_P_DP_CTRL 248
623 #define SRST_S_DP_CTRL 249
624 #define SRST_C_DP_CTRL 250
625 #define SRST_P_MIPI_DSI0 251
626 #define SRST_P_MIPI_DSI1 252
627 #define SRST_DP_CORE 253
628 #define SRST_DP_I2S 254
630 /* cru_softrst_con16 */
631 #define SRST_GASKET 256
632 #define SRST_VIO_GRF 258
633 #define SRST_DPTX_SPDIF_REC 259
634 #define SRST_HDMI_CTRL 260
635 #define SRST_HDCP_CTRL 261
636 #define SRST_A_ISP0_NOC 262
637 #define SRST_A_ISP1_NOC 263
638 #define SRST_H_ISP0_NOC 266
639 #define SRST_H_ISP1_NOC 267
640 #define SRST_H_ISP0 268
641 #define SRST_H_ISP1 269
642 #define SRST_ISP0 270
643 #define SRST_ISP1 271
645 /* cru_softrst_con17 */
646 #define SRST_A_VOP0_NOC 272
647 #define SRST_A_VOP1_NOC 273
648 #define SRST_A_VOP0 274
649 #define SRST_A_VOP1 275
650 #define SRST_H_VOP0_NOC 276
651 #define SRST_H_VOP1_NOC 277
652 #define SRST_H_VOP0 278
653 #define SRST_H_VOP1 279
654 #define SRST_D_VOP0 280
655 #define SRST_D_VOP1 281
656 #define SRST_VOP0_PWM 282
657 #define SRST_VOP1_PWM 283
658 #define SRST_P_EDP_NOC 284
659 #define SRST_P_EDP_CTRL 285
661 /* cru_softrst_con18 */
662 #define SRST_A_GPU_NOC 289
663 #define SRST_A_GPU_GRF 290
664 #define SRST_PVTM_GPU 291
665 #define SRST_A_USB3_NOC 292
666 #define SRST_A_USB3_OTG0 293
667 #define SRST_A_USB3_OTG1 294
668 #define SRST_A_USB3_GRF 295
671 /* cru_softrst_con19 */
672 #define SRST_P_TIMER0_5 304
673 #define SRST_TIMER0 305
674 #define SRST_TIMER1 306
675 #define SRST_TIMER2 307
676 #define SRST_TIMER3 308
677 #define SRST_TIMER4 309
678 #define SRST_TIMER5 310
679 #define SRST_P_TIMER6_11 311
680 #define SRST_TIMER6 312
681 #define SRST_TIMER7 313
682 #define SRST_TIMER8 314
683 #define SRST_TIMER9 315
684 #define SRST_TIMER10 316
685 #define SRST_TIMER11 317
686 #define SRST_P_INTR_ARB_PMU 318
687 #define SRST_P_ALIVE_SGRF 319
689 /* cru_softrst_con20 */
690 #define SRST_P_GPIO2 320
691 #define SRST_P_GPIO3 321
692 #define SRST_P_GPIO4 322
693 #define SRST_P_GRF 323
694 #define SRST_P_ALIVE_NOC 324
695 #define SRST_P_WDT0 325
696 #define SRST_P_WDT1 326
697 #define SRST_P_INTR_ARB 327
698 #define SRST_P_UPHY0_DPTX 328
699 #define SRST_P_UPHY0_APB 330
700 #define SRST_P_UPHY0_TCPHY 332
701 #define SRST_P_UPHY1_TCPHY 333
702 #define SRST_P_UPHY0_TCPDCTRL 334
703 #define SRST_P_UPHY1_TCPDCTRL 335
705 /* pmu soft-reset indices */
707 /* pmu_cru_softrst_con0 */
709 #define SRST_P_INTMEM 1
710 #define SRST_H_CM0S 2
711 #define SRST_H_CM0S_NOC 3
712 #define SRST_DBG_CM0S 4
713 #define SRST_PO_CM0S 5
714 #define SRST_P_SPI6 6
716 #define SRST_P_TIMER_0_1 8
717 #define SRST_P_TIMER_0 9
718 #define SRST_P_TIMER_1 10
719 #define SRST_P_UART4 11
720 #define SRST_UART4 12
721 #define SRST_P_WDT 13
723 /* pmu_cru_softrst_con1 */
724 #define SRST_P_I2C6 16
725 #define SRST_P_I2C7 17
726 #define SRST_P_I2C8 18
727 #define SRST_P_MAILBOX 19
728 #define SRST_P_RKPWM 20
729 #define SRST_P_PMUGRF 21
730 #define SRST_P_SGRF 22
731 #define SRST_P_GPIO0 23
732 #define SRST_P_GPIO1 24
733 #define SRST_P_CRU 25
734 #define SRST_P_INTR 26