2 * Header providing constants for Rockchip pinctrl bindings.
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_RK3188_H__
19 #define __DT_BINDINGS_ROCKCHIP_PINCTRL_RK3188_H__
25 #define GPIO0_C0 0x0c00
26 #define NAND_D8 0x0c01
28 #define GPIO0_C1 0x0c10
29 #define NAND_D9 0x0c11
31 #define GPIO0_C2 0x0c20
32 #define NAND_D10 0x0c21
34 #define GPIO0_C3 0x0c30
35 #define NAND_D11 0x0c31
37 #define GPIO0_C4 0x0c40
38 #define NAND_D12 0x0c41
40 #define GPIO0_C5 0x0c50
41 #define NAND_D13 0x0c51
43 #define GPIO0_C6 0x0c60
44 #define NAND_D14 0x0c61
46 #define GPIO0_C7 0x0c70
47 #define NAND_D15 0x0c71
51 #define GPIO0_D0 0x0d00
52 #define NAND_DQS 0x0d01
53 #define EMMC_CLKOUT 0x0d02
55 #define GPIO0_D1 0x0d10
56 #define NAND_CS1 0x0d11
58 #define GPIO0_D2 0x0d20
59 #define NAND_CS2 0x0d21
60 #define EMMC_CMD 0x0d22
62 #define GPIO0_D3 0x0d30
63 #define NAND_CS3 0x0d31
64 #define EMMC_RSTNOUT 0x0d32
66 #define GPIO0_D4 0x0d40
67 #define SPI1_RXD 0x0d41
69 #define GPIO0_D5 0x0d50
70 #define SPI1_TXD 0x0d51
72 #define GPIO0_D6 0x0d60
73 #define SPI1_CLK 0x0d61
75 #define GPIO0_D7 0x0d70
76 #define SPI1_CS0 0x0d71
80 #define GPIO1_A0 0x1a00
81 #define UART0_SIN 0x1a01
83 #define GPIO1_A1 0x1a10
84 #define UART0_SOUT 0x1a11
86 #define GPIO1_A2 0x1a20
87 #define UART0_CTSN 0x1a21
89 #define GPIO1_A3 0x1a30
90 #define UART0_RTSN 0x1a31
92 #define GPIO1_A4 0x1a40
93 #define UART1_SIN 0x1a41
94 #define SPI0_RXD 0x1a42
96 #define GPIO1_A5 0x1a50
97 #define UART1_SOUT 0x1a51
98 #define SPI0_TXD 0x1a52
100 #define GPIO1_A6 0x1a60
101 #define UART1_CTSN 0x1a61
102 #define SPI0_CLK 0x1a62
104 #define GPIO1_A7 0x1a70
105 #define UART1_RTSN 0x1a71
106 #define SPI0_CS0 0x1a72
109 #define GPIO1_B0 0x1b00
110 #define UART2_SIN 0x1b01
111 #define JTAG_TDI 0x1b02
113 #define GPIO1_B1 0x1b10
114 #define UART2_SOUT 0x1b11
115 #define JTAG_TDO 0x1b12
117 #define GPIO1_B2 0x1b20
118 #define UART3_SIN 0x1b21
119 #define GPS_MAG 0x1b22
121 #define GPIO1_B3 0x1b30
122 #define UART3_SOUT 0x1b31
123 #define GPS_SIG 0x1b32
125 #define GPIO1_B4 0x1b40
126 #define UART3_CTSN 0x1b41
127 #define GPS_RFCLK 0x1b42
129 #define GPIO1_B5 0x1b50
130 #define UART3_RTSN 0x1b51
132 #define GPIO1_B6 0x1b60
133 #define SPDIF_TX 0x1b61
134 #define SPI1_CS1 0x1b62
136 #define GPIO1_B7 0x1b70
137 #define SPI0_CS1 0x1b71
141 #define GPIO1_C0 0x1c00
142 #define I2S0_MCLK 0x1c01
144 #define GPIO1_C1 0x1c10
145 #define I2S0_SCLK 0x1c11
147 #define GPIO1_C2 0x1c20
148 #define I2S0_LRCKRX 0x1c21
150 #define GPIO1_C3 0x1c30
151 #define I2S0_LRCKTX 0x1c31
153 #define GPIO1_C4 0x1c40
154 #define I2S0_SDI 0x1c41
156 #define GPIO1_C5 0x1c50
157 #define I2S0_SDO 0x1c51
161 #define GPIO1_D0 0x1d00
162 #define I2C0_SDA 0x1d01
164 #define GPIO1_D1 0x1d10
165 #define I2C0_SCL 0x1d11
167 #define GPIO1_D2 0x1d20
168 #define I2C1_SDA 0x1d21
170 #define GPIO1_D3 0x1d30
171 #define I2C1_SCL 0x1d31
173 #define GPIO1_D4 0x1d40
174 #define I2C2_SDA 0x1d41
176 #define GPIO1_D5 0x1d50
177 #define I2C2_SCL 0x1d51
179 #define GPIO1_D6 0x1d60
180 #define I2C4_SDA 0x1d61
182 #define GPIO1_D7 0x1d70
183 #define I2C4_SCL 0x1d71
187 #define GPIO2_A0 0x2a00
188 #define LCDC1_D0 0x2a01
189 #define SMC_D0 0x2a02
190 #define TRACE_D0 0x2a03
192 #define GPIO2_A1 0x2a10
193 #define LCDC1_D1 0x2a11
194 #define SMC_D1 0x2a12
195 #define TRACE_D1 0x2a13
197 #define GPIO2_A2 0x2a20
198 #define LCDC1_D2 0x2a21
199 #define SMC_D2 0x2a22
200 #define TRACE_D2 0x2a23
202 #define GPIO2_A3 0x2a30
203 #define LCDC1_D3 0x2a31
204 #define SMC_D3 0x2a32
205 #define TRACE_D3 0x2a33
207 #define GPIO2_A4 0x2a40
208 #define LCDC1_D4 0x2a41
209 #define SMC_D4 0x2a42
210 #define TRACE_D4 0x2a43
212 #define GPIO2_A5 0x2a50
213 #define LCDC1_D5 0x2a51
214 #define SMC_D5 0x2a52
215 #define TRACE_D5 0x2a53
217 #define GPIO2_A6 0x2a60
218 #define LCDC1_D6 0x2a61
219 #define SMC_D6 0x2a62
220 #define TRACE_D6 0x2a63
222 #define GPIO2_A7 0x2a70
223 #define LCDC1_D7 0x2a71
224 #define SMC_D7 0x2a72
225 #define TRACE_D7 0x2a73
229 #define GPIO2_B0 0x2b00
230 #define LCDC1_D8 0x2b01
231 #define SMC_D8 0x2b02
232 #define TRACE_D8 0x2b03
234 #define GPIO2_B1 0x2b10
235 #define LCDC1_D9 0x2b11
236 #define SMC_D9 0x2b11
237 #define TRACE_D9 0x2b12
239 #define GPIO2_B2 0x2b20
240 #define LCDC1_D10 0x2b21
241 #define SMC_D10 0x2b22
242 #define TRACE_D10 0x2b23
244 #define GPIO2_B3 0x2b30
245 #define LCDC1_D11 0x2b31
246 #define SMC_D11 0x2b32
247 #define TRACE_D11 0x2b33
249 #define GPIO2_B4 0x2b40
250 #define LCDC1_D12 0x2b41
251 #define SMC_D12 0x2b42
252 #define TRACE_D12 0x2b43
254 #define GPIO2_B5 0x2b50
255 #define LCDC1_D13 0x2b51
256 #define SMC_D13 0x2b52
257 #define TRACE_D13 0x2b53
259 #define GPIO2_B6 0x2b60
260 #define LCDC1_D14 0x2b61
261 #define SMC_D14 0x2b62
262 #define TRACE_D14 0x2b63
265 #define GPIO2_B7 0x2b70
266 #define LCDC1_D15 0x2b71
267 #define SMC_D15 0x2b72
268 #define TRACE_D15 0x2b73
272 #define GPIO2_C0 0x2c00
273 #define LCDC1_D16 0x2c01
274 #define SMC_R0 0x2c02
275 #define TRACE_CLK 0x2c03
277 #define GPIO2_C1 0x2c10
278 #define LCDC1_D17 0x2c11
279 #define SMC_R1 0x2c12
280 #define TRACE_CTL 0x2c13
282 #define GPIO2_C2 0x2c20
283 #define LCDC1_D18 0x2c21
284 #define SMC_R2 0x2c22
286 #define GPIO2_C3 0x2c30
287 #define LCDC1_D19 0x2c31
288 #define SMC_R3 0x2c32
290 #define GPIO2_C4 0x2c40
291 #define LCDC1_D20 0x2c41
292 #define SMC_R4 0x2c42
294 #define GPIO2_C5 0x2c50
295 #define LCDC1_D21 0x2c51
296 #define SMC_R5 0x2c52
298 #define GPIO2_C6 0x2c60
299 #define LCDC1_D22 0x2c61
300 #define SMC_R6 0x2c62
302 #define GPIO2_C7 0x2c70
303 #define LCDC1_D23 0x2c71
304 #define SMC_R7 0x2c72
308 #define GPIO2_D0 0x2d00
309 #define LCDC1_DCLK 0x2d01
310 #define SMC_CS0 0x2d02
312 #define GPIO2_D1 0x2d10
313 #define LCDC1_DEN 0x2d11
314 #define SMC_WEN 0x2d12
316 #define GPIO2_D2 0x2d20
317 #define LCDC1_HSYNC 0x2d21
318 #define SMC_OEN 0x2d22
320 #define GPIO2_D3 0x2d30
321 #define LCDC1_VSYNC 0x2d31
322 #define SMC_ADVN 0x2d32
324 #define GPIO2_D4 0x2d40
325 #define SMC_BLSN0 0x2d41
327 #define GPIO2_D5 0x2d50
328 #define SMC_BLSN1 0x2d51
330 #define GPIO2_D6 0x2d60
331 #define SMC_CS1 0x2d61
333 #define GPIO2_D7 0x2d70
334 #define TEST_CLK_OUT 0x2d71
338 #define GPIO3_A0 0x3a00
339 #define MMC0_RSTNOUT 0x3a01
341 #define GPIO3_A1 0x3a10
342 #define MMC0_PWREN 0x3a11
344 #define GPIO3_A2 0x3a20
345 #define MMC0_CLKOUT 0x3a21
347 #define GPIO3_A3 0x3a30
348 #define MMC0_CMD 0x3a31
350 #define GPIO3_A4 0x3a40
351 #define MMC0_D0 0x3a41
353 #define GPIO3_A5 0x3a50
354 #define MMC0_D1 0x3a51
356 #define GPIO3_A6 0x3a60
357 #define MMC0_D2 0x3a61
359 #define GPIO3_A7 0x3a70
360 #define MMC0_D3 0x3a71
364 #define GPIO3_B0 0x3b00
365 #define MMC0_DETN 0x3b01
367 #define GPIO3_B1 0x3b10
368 #define MMC0_WRPRT 0x3b11
370 #define GPIO3_B3 0x3b30
371 #define CIF0_CLKOUT 0x3b31
373 #define GPIO3_B4 0x3b40
374 #define CIF0_D0 0x3b41
375 #define HSADC_D8 0x3b42
377 #define GPIO3_B5 0x3b50
378 #define CIF0_D1 0x3b51
379 #define HSADC_D9 0x3b52
381 #define GPIO3_B6 0x3b60
382 #define CIF0_D10 0x3b61
383 #define I2C3_SDA 0x3b62
385 #define GPIO3_B7 0x3b70
386 #define CIF0_D11 0x3b71
387 #define I2C3_SCL 0x3b72
391 #define GPIO3_C0 0x3c00
392 #define MMC1_CMD 0x3c01
393 #define RMII_TXEN 0x3c02
395 #define GPIO3_C1 0x3c10
396 #define MMC1_D0 0x3c11
397 #define RMII_TXD1 0x3c12
399 #define GPIO3_C2 0x3c20
400 #define MMC1_D1 0x3c21
401 #define RMII_TXD0 0x3c22
403 #define GPIO3_C3 0x3c30
404 #define MMC1_D2 0x3c31
405 #define RMII_RXD0 0x3c32
407 #define GPIO3_C4 0x3c40
408 #define MMC1_D3 0x3c41
409 #define RMII_RXD1 0x3c42
411 #define GPIO3_C5 0x3c50
412 #define MMC1_CLKOUT 0x3c51
413 #define RMII_CLKOUT 0x3c52
414 #define RMII_CLKIN 0x3c52
416 #define GPIO3_C6 0x3c60
417 #define MMC1_DETN 0x3c61
418 #define RMII_RXERR 0x3c62
420 #define GPIO3_C7 0x3c70
421 #define MMC1_WRPRT 0x3c71
422 #define RMII_CRS 0x3c72
426 #define GPIO3_D0 0x3d00
427 #define MMC1_PWREN 0x3d01
428 #define RMII_MD 0x3d02
430 #define GPIO3_D1 0x3d10
431 #define MMC1_BKEPWR 0x3d11
432 #define RMII_MDCLK 0x3d12
434 #define GPIO3_D2 0x3d20
435 #define MMC1_INTN 0x3d21
437 #define GPIO3_D3 0x3d30
440 #define GPIO3_D4 0x3d40
442 #define JTAG_TRSTN 0x3d42
444 #define GPIO3_D5 0x3d50
446 #define JTAG_TCK 0x3d52
447 #define OTG_DRV_VBUS 0x3d53
449 #define GPIO3_D6 0x3d60
451 #define JTAG_TMS 0x3d62
452 #define HOST_DRV_VBUS 0x3d63
455 #define RK2928_PULL_OFFSET 0x118
456 #define RK2928_PULL_PINS_PER_REG 16
457 #define RK2928_PULL_BANK_STRIDE 8
459 #define RK3188_PULL_BITS_PER_PIN 2
460 #define RK3188_PULL_PINS_PER_REG 8
461 #define RK3188_PULL_BANK_STRIDE 16
464 /*warning:don not chang the following value*/
465 #define VALUE_PULL_DISABLE 0
466 #define VALUE_PULL_UP 1
467 #define VALUE_PULL_DOWN 2
468 #define VALUE_PULL_DEFAULT 3
470 #define VALUE_VOL_DEFAULT 0
471 #define VALUE_VOL_33V 0
472 #define VALUE_VOL_18V 1
474 #define VALUE_DRV_DEFAULT 0
475 #define VALUE_DRV_2MA 0
476 #define VALUE_DRV_4MA 1
477 #define VALUE_DRV_8MA 2
478 #define VALUE_DRV_12MA 3
480 #define VALUE_TRI_DEFAULT 0
481 #define VALUE_TRI_FALSE 0
482 #define VALUE_TRI_TRUE 1
486 * pin config bit field definitions
493 * MSB of each field is presence bit for the config.
496 #define PULL_PRESENT (1 << 2)
498 #define VOL_PRESENT (1 << 5)
500 #define DRV_PRESENT (1 << 8)
502 #define TRI_PRESENT (1 << 11)
504 #define CONFIG_TO_PULL(c) ((c) >> PULL_SHIFT & 0x3)
505 #define CONFIG_TO_VOL(c) ((c) >> VOL_SHIFT & 0x3)
506 #define CONFIG_TO_DRV(c) ((c) >> DRV_SHIFT & 0x3)
507 #define CONFIG_TO_TRI(c) ((c) >> TRI_SHIFT & 0x3)
510 #define MAX_NUM_CONFIGS 4
517 //#define rk29_mux_api_set(name, mode) iomux_set(mode)
518 //#define rk30_mux_api_set(name, mode) iomux_set(mode)
519 //#define rk30_iomux_init() iomux_init()
524 #define RK30_PIN0_PA0 (0*NUM_GROUP + PIN_BASE + 0)
525 #define RK30_PIN0_PA1 (0*NUM_GROUP + PIN_BASE + 1)
526 #define RK30_PIN0_PA2 (0*NUM_GROUP + PIN_BASE + 2)
527 #define RK30_PIN0_PA3 (0*NUM_GROUP + PIN_BASE + 3)
528 #define RK30_PIN0_PA4 (0*NUM_GROUP + PIN_BASE + 4)
529 #define RK30_PIN0_PA5 (0*NUM_GROUP + PIN_BASE + 5)
530 #define RK30_PIN0_PA6 (0*NUM_GROUP + PIN_BASE + 6)
531 #define RK30_PIN0_PA7 (0*NUM_GROUP + PIN_BASE + 7)
532 #define RK30_PIN0_PB0 (0*NUM_GROUP + PIN_BASE + 8)
533 #define RK30_PIN0_PB1 (0*NUM_GROUP + PIN_BASE + 9)
534 #define RK30_PIN0_PB2 (0*NUM_GROUP + PIN_BASE + 10)
535 #define RK30_PIN0_PB3 (0*NUM_GROUP + PIN_BASE + 11)
536 #define RK30_PIN0_PB4 (0*NUM_GROUP + PIN_BASE + 12)
537 #define RK30_PIN0_PB5 (0*NUM_GROUP + PIN_BASE + 13)
538 #define RK30_PIN0_PB6 (0*NUM_GROUP + PIN_BASE + 14)
539 #define RK30_PIN0_PB7 (0*NUM_GROUP + PIN_BASE + 15)
540 #define RK30_PIN0_PC0 (0*NUM_GROUP + PIN_BASE + 16)
541 #define RK30_PIN0_PC1 (0*NUM_GROUP + PIN_BASE + 17)
542 #define RK30_PIN0_PC2 (0*NUM_GROUP + PIN_BASE + 18)
543 #define RK30_PIN0_PC3 (0*NUM_GROUP + PIN_BASE + 19)
544 #define RK30_PIN0_PC4 (0*NUM_GROUP + PIN_BASE + 20)
545 #define RK30_PIN0_PC5 (0*NUM_GROUP + PIN_BASE + 21)
546 #define RK30_PIN0_PC6 (0*NUM_GROUP + PIN_BASE + 22)
547 #define RK30_PIN0_PC7 (0*NUM_GROUP + PIN_BASE + 23)
548 #define RK30_PIN0_PD0 (0*NUM_GROUP + PIN_BASE + 24)
549 #define RK30_PIN0_PD1 (0*NUM_GROUP + PIN_BASE + 25)
550 #define RK30_PIN0_PD2 (0*NUM_GROUP + PIN_BASE + 26)
551 #define RK30_PIN0_PD3 (0*NUM_GROUP + PIN_BASE + 27)
552 #define RK30_PIN0_PD4 (0*NUM_GROUP + PIN_BASE + 28)
553 #define RK30_PIN0_PD5 (0*NUM_GROUP + PIN_BASE + 29)
554 #define RK30_PIN0_PD6 (0*NUM_GROUP + PIN_BASE + 30)
555 #define RK30_PIN0_PD7 (0*NUM_GROUP + PIN_BASE + 31)
557 #define RK30_PIN1_PA0 (1*NUM_GROUP + PIN_BASE + 0)
558 #define RK30_PIN1_PA1 (1*NUM_GROUP + PIN_BASE + 1)
559 #define RK30_PIN1_PA2 (1*NUM_GROUP + PIN_BASE + 2)
560 #define RK30_PIN1_PA3 (1*NUM_GROUP + PIN_BASE + 3)
561 #define RK30_PIN1_PA4 (1*NUM_GROUP + PIN_BASE + 4)
562 #define RK30_PIN1_PA5 (1*NUM_GROUP + PIN_BASE + 5)
563 #define RK30_PIN1_PA6 (1*NUM_GROUP + PIN_BASE + 6)
564 #define RK30_PIN1_PA7 (1*NUM_GROUP + PIN_BASE + 7)
565 #define RK30_PIN1_PB0 (1*NUM_GROUP + PIN_BASE + 8)
566 #define RK30_PIN1_PB1 (1*NUM_GROUP + PIN_BASE + 9)
567 #define RK30_PIN1_PB2 (1*NUM_GROUP + PIN_BASE + 10)
568 #define RK30_PIN1_PB3 (1*NUM_GROUP + PIN_BASE + 11)
569 #define RK30_PIN1_PB4 (1*NUM_GROUP + PIN_BASE + 12)
570 #define RK30_PIN1_PB5 (1*NUM_GROUP + PIN_BASE + 13)
571 #define RK30_PIN1_PB6 (1*NUM_GROUP + PIN_BASE + 14)
572 #define RK30_PIN1_PB7 (1*NUM_GROUP + PIN_BASE + 15)
573 #define RK30_PIN1_PC0 (1*NUM_GROUP + PIN_BASE + 16)
574 #define RK30_PIN1_PC1 (1*NUM_GROUP + PIN_BASE + 17)
575 #define RK30_PIN1_PC2 (1*NUM_GROUP + PIN_BASE + 18)
576 #define RK30_PIN1_PC3 (1*NUM_GROUP + PIN_BASE + 19)
577 #define RK30_PIN1_PC4 (1*NUM_GROUP + PIN_BASE + 20)
578 #define RK30_PIN1_PC5 (1*NUM_GROUP + PIN_BASE + 21)
579 #define RK30_PIN1_PC6 (1*NUM_GROUP + PIN_BASE + 22)
580 #define RK30_PIN1_PC7 (1*NUM_GROUP + PIN_BASE + 23)
581 #define RK30_PIN1_PD0 (1*NUM_GROUP + PIN_BASE + 24)
582 #define RK30_PIN1_PD1 (1*NUM_GROUP + PIN_BASE + 25)
583 #define RK30_PIN1_PD2 (1*NUM_GROUP + PIN_BASE + 26)
584 #define RK30_PIN1_PD3 (1*NUM_GROUP + PIN_BASE + 27)
585 #define RK30_PIN1_PD4 (1*NUM_GROUP + PIN_BASE + 28)
586 #define RK30_PIN1_PD5 (1*NUM_GROUP + PIN_BASE + 29)
587 #define RK30_PIN1_PD6 (1*NUM_GROUP + PIN_BASE + 30)
588 #define RK30_PIN1_PD7 (1*NUM_GROUP + PIN_BASE + 31)
590 #define RK30_PIN2_PA0 (2*NUM_GROUP + PIN_BASE + 0)
591 #define RK30_PIN2_PA1 (2*NUM_GROUP + PIN_BASE + 1)
592 #define RK30_PIN2_PA2 (2*NUM_GROUP + PIN_BASE + 2)
593 #define RK30_PIN2_PA3 (2*NUM_GROUP + PIN_BASE + 3)
594 #define RK30_PIN2_PA4 (2*NUM_GROUP + PIN_BASE + 4)
595 #define RK30_PIN2_PA5 (2*NUM_GROUP + PIN_BASE + 5)
596 #define RK30_PIN2_PA6 (2*NUM_GROUP + PIN_BASE + 6)
597 #define RK30_PIN2_PA7 (2*NUM_GROUP + PIN_BASE + 7)
598 #define RK30_PIN2_PB0 (2*NUM_GROUP + PIN_BASE + 8)
599 #define RK30_PIN2_PB1 (2*NUM_GROUP + PIN_BASE + 9)
600 #define RK30_PIN2_PB2 (2*NUM_GROUP + PIN_BASE + 10)
601 #define RK30_PIN2_PB3 (2*NUM_GROUP + PIN_BASE + 11)
602 #define RK30_PIN2_PB4 (2*NUM_GROUP + PIN_BASE + 12)
603 #define RK30_PIN2_PB5 (2*NUM_GROUP + PIN_BASE + 13)
604 #define RK30_PIN2_PB6 (2*NUM_GROUP + PIN_BASE + 14)
605 #define RK30_PIN2_PB7 (2*NUM_GROUP + PIN_BASE + 15)
606 #define RK30_PIN2_PC0 (2*NUM_GROUP + PIN_BASE + 16)
607 #define RK30_PIN2_PC1 (2*NUM_GROUP + PIN_BASE + 17)
608 #define RK30_PIN2_PC2 (2*NUM_GROUP + PIN_BASE + 18)
609 #define RK30_PIN2_PC3 (2*NUM_GROUP + PIN_BASE + 19)
610 #define RK30_PIN2_PC4 (2*NUM_GROUP + PIN_BASE + 20)
611 #define RK30_PIN2_PC5 (2*NUM_GROUP + PIN_BASE + 21)
612 #define RK30_PIN2_PC6 (2*NUM_GROUP + PIN_BASE + 22)
613 #define RK30_PIN2_PC7 (2*NUM_GROUP + PIN_BASE + 23)
614 #define RK30_PIN2_PD0 (2*NUM_GROUP + PIN_BASE + 24)
615 #define RK30_PIN2_PD1 (2*NUM_GROUP + PIN_BASE + 25)
616 #define RK30_PIN2_PD2 (2*NUM_GROUP + PIN_BASE + 26)
617 #define RK30_PIN2_PD3 (2*NUM_GROUP + PIN_BASE + 27)
618 #define RK30_PIN2_PD4 (2*NUM_GROUP + PIN_BASE + 28)
619 #define RK30_PIN2_PD5 (2*NUM_GROUP + PIN_BASE + 29)
620 #define RK30_PIN2_PD6 (2*NUM_GROUP + PIN_BASE + 30)
621 #define RK30_PIN2_PD7 (2*NUM_GROUP + PIN_BASE + 31)
623 #define RK30_PIN3_PA0 (3*NUM_GROUP + PIN_BASE + 0)
624 #define RK30_PIN3_PA1 (3*NUM_GROUP + PIN_BASE + 1)
625 #define RK30_PIN3_PA2 (3*NUM_GROUP + PIN_BASE + 2)
626 #define RK30_PIN3_PA3 (3*NUM_GROUP + PIN_BASE + 3)
627 #define RK30_PIN3_PA4 (3*NUM_GROUP + PIN_BASE + 4)
628 #define RK30_PIN3_PA5 (3*NUM_GROUP + PIN_BASE + 5)
629 #define RK30_PIN3_PA6 (3*NUM_GROUP + PIN_BASE + 6)
630 #define RK30_PIN3_PA7 (3*NUM_GROUP + PIN_BASE + 7)
631 #define RK30_PIN3_PB0 (3*NUM_GROUP + PIN_BASE + 8)
632 #define RK30_PIN3_PB1 (3*NUM_GROUP + PIN_BASE + 9)
633 #define RK30_PIN3_PB2 (3*NUM_GROUP + PIN_BASE + 10)
634 #define RK30_PIN3_PB3 (3*NUM_GROUP + PIN_BASE + 11)
635 #define RK30_PIN3_PB4 (3*NUM_GROUP + PIN_BASE + 12)
636 #define RK30_PIN3_PB5 (3*NUM_GROUP + PIN_BASE + 13)
637 #define RK30_PIN3_PB6 (3*NUM_GROUP + PIN_BASE + 14)
638 #define RK30_PIN3_PB7 (3*NUM_GROUP + PIN_BASE + 15)
639 #define RK30_PIN3_PC0 (3*NUM_GROUP + PIN_BASE + 16)
640 #define RK30_PIN3_PC1 (3*NUM_GROUP + PIN_BASE + 17)
641 #define RK30_PIN3_PC2 (3*NUM_GROUP + PIN_BASE + 18)
642 #define RK30_PIN3_PC3 (3*NUM_GROUP + PIN_BASE + 19)
643 #define RK30_PIN3_PC4 (3*NUM_GROUP + PIN_BASE + 20)
644 #define RK30_PIN3_PC5 (3*NUM_GROUP + PIN_BASE + 21)
645 #define RK30_PIN3_PC6 (3*NUM_GROUP + PIN_BASE + 22)
646 #define RK30_PIN3_PC7 (3*NUM_GROUP + PIN_BASE + 23)
647 #define RK30_PIN3_PD0 (3*NUM_GROUP + PIN_BASE + 24)
648 #define RK30_PIN3_PD1 (3*NUM_GROUP + PIN_BASE + 25)
649 #define RK30_PIN3_PD2 (3*NUM_GROUP + PIN_BASE + 26)
650 #define RK30_PIN3_PD3 (3*NUM_GROUP + PIN_BASE + 27)
651 #define RK30_PIN3_PD4 (3*NUM_GROUP + PIN_BASE + 28)
652 #define RK30_PIN3_PD5 (3*NUM_GROUP + PIN_BASE + 29)
653 #define RK30_PIN3_PD6 (3*NUM_GROUP + PIN_BASE + 30)
654 #define RK30_PIN3_PD7 (3*NUM_GROUP + PIN_BASE + 31)
656 #define RK30_PIN4_PA0 (4*NUM_GROUP + PIN_BASE + 0)
657 #define RK30_PIN4_PA1 (4*NUM_GROUP + PIN_BASE + 1)
658 #define RK30_PIN4_PA2 (4*NUM_GROUP + PIN_BASE + 2)
659 #define RK30_PIN4_PA3 (4*NUM_GROUP + PIN_BASE + 3)
660 #define RK30_PIN4_PA4 (4*NUM_GROUP + PIN_BASE + 4)
661 #define RK30_PIN4_PA5 (4*NUM_GROUP + PIN_BASE + 5)
662 #define RK30_PIN4_PA6 (4*NUM_GROUP + PIN_BASE + 6)
663 #define RK30_PIN4_PA7 (4*NUM_GROUP + PIN_BASE + 7)
664 #define RK30_PIN4_PB0 (4*NUM_GROUP + PIN_BASE + 8)
665 #define RK30_PIN4_PB1 (4*NUM_GROUP + PIN_BASE + 9)
666 #define RK30_PIN4_PB2 (4*NUM_GROUP + PIN_BASE + 10)
667 #define RK30_PIN4_PB3 (4*NUM_GROUP + PIN_BASE + 11)
668 #define RK30_PIN4_PB4 (4*NUM_GROUP + PIN_BASE + 12)
669 #define RK30_PIN4_PB5 (4*NUM_GROUP + PIN_BASE + 13)
670 #define RK30_PIN4_PB6 (4*NUM_GROUP + PIN_BASE + 14)
671 #define RK30_PIN4_PB7 (4*NUM_GROUP + PIN_BASE + 15)
672 #define RK30_PIN4_PC0 (4*NUM_GROUP + PIN_BASE + 16)
673 #define RK30_PIN4_PC1 (4*NUM_GROUP + PIN_BASE + 17)
674 #define RK30_PIN4_PC2 (4*NUM_GROUP + PIN_BASE + 18)
675 #define RK30_PIN4_PC3 (4*NUM_GROUP + PIN_BASE + 19)
676 #define RK30_PIN4_PC4 (4*NUM_GROUP + PIN_BASE + 20)
677 #define RK30_PIN4_PC5 (4*NUM_GROUP + PIN_BASE + 21)
678 #define RK30_PIN4_PC6 (4*NUM_GROUP + PIN_BASE + 22)
679 #define RK30_PIN4_PC7 (4*NUM_GROUP + PIN_BASE + 23)
680 #define RK30_PIN4_PD0 (4*NUM_GROUP + PIN_BASE + 24)
681 #define RK30_PIN4_PD1 (4*NUM_GROUP + PIN_BASE + 25)
682 #define RK30_PIN4_PD2 (4*NUM_GROUP + PIN_BASE + 26)
683 #define RK30_PIN4_PD3 (4*NUM_GROUP + PIN_BASE + 27)
684 #define RK30_PIN4_PD4 (4*NUM_GROUP + PIN_BASE + 28)
685 #define RK30_PIN4_PD5 (4*NUM_GROUP + PIN_BASE + 29)
686 #define RK30_PIN4_PD6 (4*NUM_GROUP + PIN_BASE + 30)
687 #define RK30_PIN4_PD7 (4*NUM_GROUP + PIN_BASE + 31)
689 #define RK30_PIN6_PA0 (6*NUM_GROUP + PIN_BASE + 0)
690 #define RK30_PIN6_PA1 (6*NUM_GROUP + PIN_BASE + 1)
691 #define RK30_PIN6_PA2 (6*NUM_GROUP + PIN_BASE + 2)
692 #define RK30_PIN6_PA3 (6*NUM_GROUP + PIN_BASE + 3)
693 #define RK30_PIN6_PA4 (6*NUM_GROUP + PIN_BASE + 4)
694 #define RK30_PIN6_PA5 (6*NUM_GROUP + PIN_BASE + 5)
695 #define RK30_PIN6_PA6 (6*NUM_GROUP + PIN_BASE + 6)
696 #define RK30_PIN6_PA7 (6*NUM_GROUP + PIN_BASE + 7)
697 #define RK30_PIN6_PB0 (6*NUM_GROUP + PIN_BASE + 8)
698 #define RK30_PIN6_PB1 (6*NUM_GROUP + PIN_BASE + 9)
699 #define RK30_PIN6_PB2 (6*NUM_GROUP + PIN_BASE + 10)
700 #define RK30_PIN6_PB3 (6*NUM_GROUP + PIN_BASE + 11)
701 #define RK30_PIN6_PB4 (6*NUM_GROUP + PIN_BASE + 12)
702 #define RK30_PIN6_PB5 (6*NUM_GROUP + PIN_BASE + 13)
703 #define RK30_PIN6_PB6 (6*NUM_GROUP + PIN_BASE + 14)
704 #define RK30_PIN6_PB7 (6*NUM_GROUP + PIN_BASE + 15)