2 * linux/include/linux/clk-provider.h
4 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
5 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #ifndef __LINUX_CLK_PROVIDER_H
12 #define __LINUX_CLK_PROVIDER_H
14 #include <linux/clk.h>
16 #ifdef CONFIG_COMMON_CLK
19 * flags used across common struct clk. these flags should only affect the
20 * top-level framework. custom flags for dealing with hardware specifics
21 * belong in struct clk_foo
23 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
24 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
25 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
26 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
27 #define CLK_IS_ROOT BIT(4) /* root clk, has no parent */
28 #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
29 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
34 * struct clk_ops - Callback operations for hardware clocks; these are to
35 * be provided by the clock implementation, and will be called by drivers
36 * through the clk_* api.
38 * @prepare: Prepare the clock for enabling. This must not return until
39 * the clock is fully prepared, and it's safe to call clk_enable.
40 * This callback is intended to allow clock implementations to
41 * do any initialisation that may sleep. Called with
44 * @unprepare: Release the clock from its prepared state. This will typically
45 * undo any work done in the @prepare callback. Called with
48 * @is_prepared: Queries the hardware to determine if the clock is prepared.
49 * This function is allowed to sleep. Optional, if this op is not
50 * set then the prepare count will be used.
52 * @unprepare_unused: Unprepare the clock atomically. Only called from
53 * clk_disable_unused for prepare clocks with special needs.
54 * Called with prepare mutex held. This function may sleep.
56 * @enable: Enable the clock atomically. This must not return until the
57 * clock is generating a valid clock signal, usable by consumer
58 * devices. Called with enable_lock held. This function must not
61 * @disable: Disable the clock atomically. Called with enable_lock held.
62 * This function must not sleep.
64 * @is_enabled: Queries the hardware to determine if the clock is enabled.
65 * This function must not sleep. Optional, if this op is not
66 * set then the enable count will be used.
68 * @disable_unused: Disable the clock atomically. Only called from
69 * clk_disable_unused for gate clocks with special needs.
70 * Called with enable_lock held. This function must not
73 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The
74 * parent rate is an input parameter. It is up to the caller to
75 * ensure that the prepare_mutex is held across this call.
76 * Returns the calculated rate. Optional, but recommended - if
77 * this op is not set then clock rate will be initialized to 0.
79 * @round_rate: Given a target rate as input, returns the closest rate actually
80 * supported by the clock.
82 * @determine_rate: Given a target rate as input, returns the closest rate
83 * actually supported by the clock, and optionally the parent clock
84 * that should be used to provide the clock rate.
86 * @get_parent: Queries the hardware to determine the parent of a clock. The
87 * return value is a u8 which specifies the index corresponding to
88 * the parent clock. This index can be applied to either the
89 * .parent_names or .parents arrays. In short, this function
90 * translates the parent value read from hardware into an array
91 * index. Currently only called when the clock is initialized by
92 * __clk_init. This callback is mandatory for clocks with
93 * multiple parents. It is optional (and unnecessary) for clocks
94 * with 0 or 1 parents.
96 * @set_parent: Change the input source of this clock; for clocks with multiple
97 * possible parents specify a new parent by passing in the index
98 * as a u8 corresponding to the parent in either the .parent_names
99 * or .parents arrays. This function in affect translates an
100 * array index into the value programmed into the hardware.
101 * Returns 0 on success, -EERROR otherwise.
103 * @set_rate: Change the rate of this clock. The requested rate is specified
104 * by the second argument, which should typically be the return
105 * of .round_rate call. The third argument gives the parent rate
106 * which is likely helpful for most .set_rate implementation.
107 * Returns 0 on success, -EERROR otherwise.
109 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
110 * implementations to split any work between atomic (enable) and sleepable
111 * (prepare) contexts. If enabling a clock requires code that might sleep,
112 * this must be done in clk_prepare. Clock enable code that will never be
113 * called in a sleepable context may be implemented in clk_enable.
115 * Typically, drivers will call clk_prepare when a clock may be needed later
116 * (eg. when a device is opened), and clk_enable when the clock is actually
117 * required (eg. from an interrupt). Note that clk_prepare MUST have been
118 * called before clk_enable.
121 int (*prepare)(struct clk_hw *hw);
122 void (*unprepare)(struct clk_hw *hw);
123 int (*is_prepared)(struct clk_hw *hw);
124 void (*unprepare_unused)(struct clk_hw *hw);
125 int (*enable)(struct clk_hw *hw);
126 void (*disable)(struct clk_hw *hw);
127 int (*is_enabled)(struct clk_hw *hw);
128 void (*disable_unused)(struct clk_hw *hw);
129 unsigned long (*recalc_rate)(struct clk_hw *hw,
130 unsigned long parent_rate);
131 long (*round_rate)(struct clk_hw *hw, unsigned long,
133 long (*determine_rate)(struct clk_hw *hw, unsigned long rate,
134 unsigned long *best_parent_rate,
135 struct clk **best_parent_clk);
136 int (*set_parent)(struct clk_hw *hw, u8 index);
137 u8 (*get_parent)(struct clk_hw *hw);
138 int (*set_rate)(struct clk_hw *hw, unsigned long,
140 void (*init)(struct clk_hw *hw);
144 * struct clk_init_data - holds init data that's common to all clocks and is
145 * shared between the clock provider and the common clock framework.
148 * @ops: operations this clock supports
149 * @parent_names: array of string names for all possible parents
150 * @num_parents: number of possible parents
151 * @flags: framework-level hints and quirks
153 struct clk_init_data {
155 const struct clk_ops *ops;
156 const char **parent_names;
162 * struct clk_hw - handle for traversing from a struct clk to its corresponding
163 * hardware-specific structure. struct clk_hw should be declared within struct
164 * clk_foo and then referenced by the struct clk instance that uses struct
167 * @clk: pointer to the struct clk instance that points back to this struct
170 * @init: pointer to struct clk_init_data that contains the init data shared
171 * with the common clock framework.
175 const struct clk_init_data *init;
179 * DOC: Basic clock implementations common to many platforms
181 * Each basic clock hardware type is comprised of a structure describing the
182 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
183 * unique flags for that hardware type, a registration function and an
184 * alternative macro for static initialization
188 * struct clk_fixed_rate - fixed-rate clock
189 * @hw: handle between common and hardware-specific interfaces
190 * @fixed_rate: constant frequency of clock
192 struct clk_fixed_rate {
194 unsigned long fixed_rate;
198 extern const struct clk_ops clk_fixed_rate_ops;
199 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
200 const char *parent_name, unsigned long flags,
201 unsigned long fixed_rate);
203 void of_fixed_clk_setup(struct device_node *np);
206 * struct clk_gate - gating clock
208 * @hw: handle between common and hardware-specific interfaces
209 * @reg: register controlling gate
210 * @bit_idx: single bit controlling gate
211 * @flags: hardware-specific flags
212 * @lock: register lock
214 * Clock which can gate its output. Implements .enable & .disable
217 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
218 * enable the clock. Setting this flag does the opposite: setting the bit
219 * disable the clock and clearing it enables the clock
220 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
221 * of this register, and mask of gate bits are in higher 16-bit of this
222 * register. While setting the gate bits, higher 16-bit should also be
223 * updated to indicate changing gate bits.
233 #define CLK_GATE_SET_TO_DISABLE BIT(0)
234 #define CLK_GATE_HIWORD_MASK BIT(1)
236 extern const struct clk_ops clk_gate_ops;
237 struct clk *clk_register_gate(struct device *dev, const char *name,
238 const char *parent_name, unsigned long flags,
239 void __iomem *reg, u8 bit_idx,
240 u8 clk_gate_flags, spinlock_t *lock);
242 struct clk_div_table {
248 * struct clk_divider - adjustable divider clock
250 * @hw: handle between common and hardware-specific interfaces
251 * @reg: register containing the divider
252 * @shift: shift to the divider bit field
253 * @width: width of the divider bit field
254 * @table: array of value/divider pairs, last entry should have div = 0
255 * @lock: register lock
257 * Clock with an adjustable divider affecting its output frequency. Implements
258 * .recalc_rate, .set_rate and .round_rate
261 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
262 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
263 * the raw value read from the register, with the value of zero considered
264 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
265 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
266 * the hardware register
267 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
268 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
269 * Some hardware implementations gracefully handle this case and allow a
270 * zero divisor by not modifying their input clock
271 * (divide by one / bypass).
272 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
273 * of this register, and mask of divider bits are in higher 16-bit of this
274 * register. While setting the divider bits, higher 16-bit should also be
275 * updated to indicate changing divider bits.
283 const struct clk_div_table *table;
287 #define CLK_DIVIDER_ONE_BASED BIT(0)
288 #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
289 #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
290 #define CLK_DIVIDER_HIWORD_MASK BIT(3)
292 extern const struct clk_ops clk_divider_ops;
293 struct clk *clk_register_divider(struct device *dev, const char *name,
294 const char *parent_name, unsigned long flags,
295 void __iomem *reg, u8 shift, u8 width,
296 u8 clk_divider_flags, spinlock_t *lock);
297 struct clk *clk_register_divider_table(struct device *dev, const char *name,
298 const char *parent_name, unsigned long flags,
299 void __iomem *reg, u8 shift, u8 width,
300 u8 clk_divider_flags, const struct clk_div_table *table,
304 * struct clk_mux - multiplexer clock
306 * @hw: handle between common and hardware-specific interfaces
307 * @reg: register controlling multiplexer
308 * @shift: shift to multiplexer bit field
309 * @width: width of mutliplexer bit field
310 * @flags: hardware-specific flags
311 * @lock: register lock
313 * Clock with multiple selectable parents. Implements .get_parent, .set_parent
317 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
318 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
319 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
320 * register, and mask of mux bits are in higher 16-bit of this register.
321 * While setting the mux bits, higher 16-bit should also be updated to
322 * indicate changing mux bits.
334 #define CLK_MUX_INDEX_ONE BIT(0)
335 #define CLK_MUX_INDEX_BIT BIT(1)
336 #define CLK_MUX_HIWORD_MASK BIT(2)
338 extern const struct clk_ops clk_mux_ops;
340 struct clk *clk_register_mux(struct device *dev, const char *name,
341 const char **parent_names, u8 num_parents, unsigned long flags,
342 void __iomem *reg, u8 shift, u8 width,
343 u8 clk_mux_flags, spinlock_t *lock);
345 struct clk *clk_register_mux_table(struct device *dev, const char *name,
346 const char **parent_names, u8 num_parents, unsigned long flags,
347 void __iomem *reg, u8 shift, u32 mask,
348 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
350 void of_fixed_factor_clk_setup(struct device_node *node);
353 * struct clk_fixed_factor - fixed multiplier and divider clock
355 * @hw: handle between common and hardware-specific interfaces
359 * Clock with a fixed multiplier and divider. The output frequency is the
360 * parent clock rate divided by div and multiplied by mult.
361 * Implements .recalc_rate, .set_rate and .round_rate
364 struct clk_fixed_factor {
370 extern struct clk_ops clk_fixed_factor_ops;
371 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
372 const char *parent_name, unsigned long flags,
373 unsigned int mult, unsigned int div);
376 * struct clk_composite - aggregate clock of mux, divider and gate clocks
378 * @hw: handle between common and hardware-specific interfaces
379 * @mux_hw: handle between composite and hardware-specific mux clock
380 * @rate_hw: handle between composite and hardware-specific rate clock
381 * @gate_hw: handle between composite and hardware-specific gate clock
382 * @mux_ops: clock ops for mux
383 * @rate_ops: clock ops for rate
384 * @gate_ops: clock ops for gate
386 struct clk_composite {
390 struct clk_hw *mux_hw;
391 struct clk_hw *rate_hw;
392 struct clk_hw *gate_hw;
394 const struct clk_ops *mux_ops;
395 const struct clk_ops *rate_ops;
396 const struct clk_ops *gate_ops;
399 struct clk *clk_register_composite(struct device *dev, const char *name,
400 const char **parent_names, int num_parents,
401 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
402 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
403 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
404 unsigned long flags);
407 * clk_register - allocate a new clock, register it and return an opaque cookie
408 * @dev: device that is registering this clock
409 * @hw: link to hardware-specific clock data
411 * clk_register is the primary interface for populating the clock tree with new
412 * clock nodes. It returns a pointer to the newly allocated struct clk which
413 * cannot be dereferenced by driver code but may be used in conjuction with the
414 * rest of the clock API. In the event of an error clk_register will return an
415 * error code; drivers must test for an error code after calling clk_register.
417 struct clk *clk_register(struct device *dev, struct clk_hw *hw);
418 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
420 void clk_unregister(struct clk *clk);
421 void devm_clk_unregister(struct device *dev, struct clk *clk);
423 /* helper functions */
424 const char *__clk_get_name(struct clk *clk);
425 struct clk_hw *__clk_get_hw(struct clk *clk);
426 u8 __clk_get_num_parents(struct clk *clk);
427 struct clk *__clk_get_parent(struct clk *clk);
428 struct clk *clk_get_parent_by_index(struct clk *clk, u8 index);
429 unsigned int __clk_get_enable_count(struct clk *clk);
430 unsigned int __clk_get_prepare_count(struct clk *clk);
431 unsigned long __clk_get_rate(struct clk *clk);
432 unsigned long __clk_get_flags(struct clk *clk);
433 bool __clk_is_prepared(struct clk *clk);
434 bool __clk_is_enabled(struct clk *clk);
435 struct clk *__clk_lookup(const char *name);
436 long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
437 unsigned long *best_parent_rate,
438 struct clk **best_parent_p);
441 * FIXME clock api without lock protection
443 int __clk_prepare(struct clk *clk);
444 void __clk_unprepare(struct clk *clk);
445 void __clk_reparent(struct clk *clk, struct clk *new_parent);
446 unsigned long __clk_round_rate(struct clk *clk, unsigned long rate);
450 typedef void (*of_clk_init_cb_t)(struct device_node *);
452 int of_clk_add_provider(struct device_node *np,
453 struct clk *(*clk_src_get)(struct of_phandle_args *args,
456 void of_clk_del_provider(struct device_node *np);
457 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
459 struct clk_onecell_data {
461 unsigned int clk_num;
463 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
464 int of_clk_get_parent_count(struct device_node *np);
465 const char *of_clk_get_parent_name(struct device_node *np, int index);
467 void of_clk_init(const struct of_device_id *matches);
469 #define CLK_OF_DECLARE(name, compat, fn) \
470 static const struct of_device_id __clk_of_table_##name \
471 __used __section(__clk_of_table) \
472 = { .compatible = compat, .data = fn };
474 #endif /* CONFIG_COMMON_CLK */
475 #endif /* CLK_PROVIDER_H */