2 * Driver for the Synopsys DesignWare DMA Controller (aka DMACA on
5 * Copyright (C) 2007 Atmel Corporation
6 * Copyright (C) 2010-2011 ST Microelectronics
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
15 #include <linux/dmaengine.h>
18 * struct dw_dma_slave - Controller-specific information about a slave
20 * @dma_dev: required DMA master device. Depricated.
21 * @bus_id: name of this device channel, not just a device name since
22 * devices may have more than one channel e.g. "foo_tx"
23 * @cfg_hi: Platform-specific initializer for the CFG_HI register
24 * @cfg_lo: Platform-specific initializer for the CFG_LO register
25 * @src_master: src master for transfers on allocated channel.
26 * @dst_master: dest master for transfers on allocated channel.
29 struct device *dma_dev;
38 * struct dw_dma_platform_data - Controller configuration parameters
39 * @nr_channels: Number of channels supported by hardware (max 8)
40 * @is_private: The device channels should be marked as private and not for
41 * by the general purpose DMA channel allocator.
42 * @chan_allocation_order: Allocate channels starting from 0 or 7
43 * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.
44 * @block_size: Maximum block size supported by the controller
45 * @nr_masters: Number of AHB masters supported by the controller
46 * @data_width: Maximum data width supported by hardware per AHB master
47 * (0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
48 * @sd: slave specific data. Used for configuring channels
49 * @sd_count: count of slave data structures passed.
51 struct dw_dma_platform_data {
52 unsigned int nr_channels;
54 #define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */
55 #define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */
56 unsigned char chan_allocation_order;
57 #define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */
58 #define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */
59 unsigned char chan_priority;
60 unsigned short block_size;
61 unsigned char nr_masters;
62 unsigned char data_width[4];
64 struct dw_dma_slave *sd;
65 unsigned int sd_count;
80 /* Platform-configurable bits in CFG_HI */
81 #define DWC_CFGH_FCMODE (1 << 0)
82 #define DWC_CFGH_FIFO_MODE (1 << 1)
83 #define DWC_CFGH_PROTCTL(x) ((x) << 2)
84 #define DWC_CFGH_SRC_PER(x) ((x) << 7)
85 #define DWC_CFGH_DST_PER(x) ((x) << 11)
87 /* Platform-configurable bits in CFG_LO */
88 #define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */
89 #define DWC_CFGL_LOCK_CH_BLOCK (1 << 12)
90 #define DWC_CFGL_LOCK_CH_XACT (2 << 12)
91 #define DWC_CFGL_LOCK_BUS_XFER (0 << 14) /* scope of LOCK_BUS */
92 #define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14)
93 #define DWC_CFGL_LOCK_BUS_XACT (2 << 14)
94 #define DWC_CFGL_LOCK_CH (1 << 15) /* channel lockout */
95 #define DWC_CFGL_LOCK_BUS (1 << 16) /* busmaster lockout */
96 #define DWC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */
97 #define DWC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */
99 /* DMA API extensions */
100 struct dw_cyclic_desc {
101 struct dw_desc **desc;
102 unsigned long periods;
103 void (*period_callback)(void *param);
104 void *period_callback_param;
107 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
108 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
109 enum dma_transfer_direction direction);
110 void dw_dma_cyclic_free(struct dma_chan *chan);
111 int dw_dma_cyclic_start(struct dma_chan *chan);
112 void dw_dma_cyclic_stop(struct dma_chan *chan);
114 dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan);
116 dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan);
117 bool dw_dma_generic_filter(struct dma_chan *chan, void *param);
119 #endif /* DW_DMAC_H */