4 * Author: Dave Jiang <djiang@mvista.com>
6 * 2006-2008 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
12 #ifndef _LINUX_EDAC_H_
13 #define _LINUX_EDAC_H_
15 #include <linux/atomic.h>
16 #include <linux/device.h>
17 #include <linux/completion.h>
18 #include <linux/workqueue.h>
19 #include <linux/debugfs.h>
23 #define EDAC_OPSTATE_INVAL -1
24 #define EDAC_OPSTATE_POLL 0
25 #define EDAC_OPSTATE_NMI 1
26 #define EDAC_OPSTATE_INT 2
28 extern int edac_op_state;
29 extern int edac_err_assert;
30 extern atomic_t edac_handlers;
31 extern struct bus_type edac_subsys;
33 extern int edac_handler_set(void);
34 extern void edac_atomic_assert_error(void);
35 extern struct bus_type *edac_get_sysfs_subsys(void);
36 extern void edac_put_sysfs_subsys(void);
38 static inline void opstate_init(void)
40 switch (edac_op_state) {
41 case EDAC_OPSTATE_POLL:
42 case EDAC_OPSTATE_NMI:
45 edac_op_state = EDAC_OPSTATE_POLL;
50 #define EDAC_MC_LABEL_LEN 31
51 #define MC_PROC_NAME_MAX_LEN 7
54 * enum dev_type - describe the type of memory DRAM chips used at the stick
55 * @DEV_UNKNOWN: Can't be determined, or MC doesn't support detect it
56 * @DEV_X1: 1 bit for data
57 * @DEV_X2: 2 bits for data
58 * @DEV_X4: 4 bits for data
59 * @DEV_X8: 8 bits for data
60 * @DEV_X16: 16 bits for data
61 * @DEV_X32: 32 bits for data
62 * @DEV_X64: 64 bits for data
64 * Typical values are x4 and x8.
73 DEV_X32, /* Do these parts exist? */
74 DEV_X64 /* Do these parts exist? */
77 #define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN)
78 #define DEV_FLAG_X1 BIT(DEV_X1)
79 #define DEV_FLAG_X2 BIT(DEV_X2)
80 #define DEV_FLAG_X4 BIT(DEV_X4)
81 #define DEV_FLAG_X8 BIT(DEV_X8)
82 #define DEV_FLAG_X16 BIT(DEV_X16)
83 #define DEV_FLAG_X32 BIT(DEV_X32)
84 #define DEV_FLAG_X64 BIT(DEV_X64)
87 * enum hw_event_mc_err_type - type of the detected error
89 * @HW_EVENT_ERR_CORRECTED: Corrected Error - Indicates that an ECC
90 * corrected error was detected
91 * @HW_EVENT_ERR_UNCORRECTED: Uncorrected Error - Indicates an error that
92 * can't be corrected by ECC, but it is not
93 * fatal (maybe it is on an unused memory area,
94 * or the memory controller could recover from
95 * it for example, by re-trying the operation).
96 * @HW_EVENT_ERR_FATAL: Fatal Error - Uncorrected error that could not
99 enum hw_event_mc_err_type {
100 HW_EVENT_ERR_CORRECTED,
101 HW_EVENT_ERR_UNCORRECTED,
106 * enum mem_type - memory types. For a more detailed reference, please see
107 * http://en.wikipedia.org/wiki/DRAM
109 * @MEM_EMPTY Empty csrow
110 * @MEM_RESERVED: Reserved csrow type
111 * @MEM_UNKNOWN: Unknown csrow type
112 * @MEM_FPM: FPM - Fast Page Mode, used on systems up to 1995.
113 * @MEM_EDO: EDO - Extended data out, used on systems up to 1998.
114 * @MEM_BEDO: BEDO - Burst Extended data out, an EDO variant.
115 * @MEM_SDR: SDR - Single data rate SDRAM
116 * http://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory
117 * They use 3 pins for chip select: Pins 0 and 2 are
118 * for rank 0; pins 1 and 3 are for rank 1, if the memory
120 * @MEM_RDR: Registered SDR SDRAM
121 * @MEM_DDR: Double data rate SDRAM
122 * http://en.wikipedia.org/wiki/DDR_SDRAM
123 * @MEM_RDDR: Registered Double data rate SDRAM
124 * This is a variant of the DDR memories.
125 * A registered memory has a buffer inside it, hiding
126 * part of the memory details to the memory controller.
127 * @MEM_RMBS: Rambus DRAM, used on a few Pentium III/IV controllers.
128 * @MEM_DDR2: DDR2 RAM, as described at JEDEC JESD79-2F.
129 * Those memories are labed as "PC2-" instead of "PC" to
130 * differenciate from DDR.
131 * @MEM_FB_DDR2: Fully-Buffered DDR2, as described at JEDEC Std No. 205
133 * Those memories are accessed per DIMM slot, and not by
134 * a chip select signal.
135 * @MEM_RDDR2: Registered DDR2 RAM
136 * This is a variant of the DDR2 memories.
137 * @MEM_XDR: Rambus XDR
138 * It is an evolution of the original RAMBUS memories,
139 * created to compete with DDR2. Weren't used on any
140 * x86 arch, but cell_edac PPC memory controller uses it.
141 * @MEM_DDR3: DDR3 RAM
142 * @MEM_RDDR3: Registered DDR3 RAM
143 * This is a variant of the DDR3 memories.
165 #define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
166 #define MEM_FLAG_RESERVED BIT(MEM_RESERVED)
167 #define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN)
168 #define MEM_FLAG_FPM BIT(MEM_FPM)
169 #define MEM_FLAG_EDO BIT(MEM_EDO)
170 #define MEM_FLAG_BEDO BIT(MEM_BEDO)
171 #define MEM_FLAG_SDR BIT(MEM_SDR)
172 #define MEM_FLAG_RDR BIT(MEM_RDR)
173 #define MEM_FLAG_DDR BIT(MEM_DDR)
174 #define MEM_FLAG_RDDR BIT(MEM_RDDR)
175 #define MEM_FLAG_RMBS BIT(MEM_RMBS)
176 #define MEM_FLAG_DDR2 BIT(MEM_DDR2)
177 #define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2)
178 #define MEM_FLAG_RDDR2 BIT(MEM_RDDR2)
179 #define MEM_FLAG_XDR BIT(MEM_XDR)
180 #define MEM_FLAG_DDR3 BIT(MEM_DDR3)
181 #define MEM_FLAG_RDDR3 BIT(MEM_RDDR3)
184 * enum edac-type - Error Detection and Correction capabilities and mode
185 * @EDAC_UNKNOWN: Unknown if ECC is available
186 * @EDAC_NONE: Doesn't support ECC
187 * @EDAC_RESERVED: Reserved ECC type
188 * @EDAC_PARITY: Detects parity errors
189 * @EDAC_EC: Error Checking - no correction
190 * @EDAC_SECDED: Single bit error correction, Double detection
191 * @EDAC_S2ECD2ED: Chipkill x2 devices - do these exist?
192 * @EDAC_S4ECD4ED: Chipkill x4 devices
193 * @EDAC_S8ECD8ED: Chipkill x8 devices
194 * @EDAC_S16ECD16ED: Chipkill x16 devices
209 #define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN)
210 #define EDAC_FLAG_NONE BIT(EDAC_NONE)
211 #define EDAC_FLAG_PARITY BIT(EDAC_PARITY)
212 #define EDAC_FLAG_EC BIT(EDAC_EC)
213 #define EDAC_FLAG_SECDED BIT(EDAC_SECDED)
214 #define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED)
215 #define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED)
216 #define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED)
217 #define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED)
220 * enum scrub_type - scrubbing capabilities
221 * @SCRUB_UNKNOWN Unknown if scrubber is available
222 * @SCRUB_NONE: No scrubber
223 * @SCRUB_SW_PROG: SW progressive (sequential) scrubbing
224 * @SCRUB_SW_SRC: Software scrub only errors
225 * @SCRUB_SW_PROG_SRC: Progressive software scrub from an error
226 * @SCRUB_SW_TUNABLE: Software scrub frequency is tunable
227 * @SCRUB_HW_PROG: HW progressive (sequential) scrubbing
228 * @SCRUB_HW_SRC: Hardware scrub only errors
229 * @SCRUB_HW_PROG_SRC: Progressive hardware scrub from an error
230 * SCRUB_HW_TUNABLE: Hardware scrub frequency is tunable
245 #define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG)
246 #define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC)
247 #define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC)
248 #define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE)
249 #define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG)
250 #define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC)
251 #define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC)
252 #define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE)
254 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
256 /* EDAC internal operation states */
257 #define OP_ALLOC 0x100
258 #define OP_RUNNING_POLL 0x201
259 #define OP_RUNNING_INTERRUPT 0x202
260 #define OP_RUNNING_POLL_INTR 0x203
261 #define OP_OFFLINE 0x300
264 * Concepts used at the EDAC subsystem
266 * There are several things to be aware of that aren't at all obvious:
268 * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
270 * These are some of the many terms that are thrown about that don't always
271 * mean what people think they mean (Inconceivable!). In the interest of
272 * creating a common ground for discussion, terms and their definitions
273 * will be established.
275 * Memory devices: The individual DRAM chips on a memory stick. These
276 * devices commonly output 4 and 8 bits each (x4, x8).
277 * Grouping several of these in parallel provides the
278 * number of bits that the memory controller expects:
279 * typically 72 bits, in order to provide 64 bits +
280 * 8 bits of ECC data.
282 * Memory Stick: A printed circuit board that aggregates multiple
283 * memory devices in parallel. In general, this is the
284 * Field Replaceable Unit (FRU) which gets replaced, in
285 * the case of excessive errors. Most often it is also
286 * called DIMM (Dual Inline Memory Module).
288 * Memory Socket: A physical connector on the motherboard that accepts
289 * a single memory stick. Also called as "slot" on several
292 * Channel: A memory controller channel, responsible to communicate
293 * with a group of DIMMs. Each channel has its own
294 * independent control (command) and data bus, and can
295 * be used independently or grouped with other channels.
297 * Branch: It is typically the highest hierarchy on a
298 * Fully-Buffered DIMM memory controller.
299 * Typically, it contains two channels.
300 * Two channels at the same branch can be used in single
301 * mode or in lockstep mode.
302 * When lockstep is enabled, the cacheline is doubled,
303 * but it generally brings some performance penalty.
304 * Also, it is generally not possible to point to just one
305 * memory stick when an error occurs, as the error
306 * correction code is calculated using two DIMMs instead
307 * of one. Due to that, it is capable of correcting more
308 * errors than on single mode.
310 * Single-channel: The data accessed by the memory controller is contained
311 * into one dimm only. E. g. if the data is 64 bits-wide,
312 * the data flows to the CPU using one 64 bits parallel
314 * Typically used with SDR, DDR, DDR2 and DDR3 memories.
315 * FB-DIMM and RAMBUS use a different concept for channel,
316 * so this concept doesn't apply there.
318 * Double-channel: The data size accessed by the memory controller is
319 * interlaced into two dimms, accessed at the same time.
320 * E. g. if the DIMM is 64 bits-wide (72 bits with ECC),
321 * the data flows to the CPU using a 128 bits parallel
324 * Chip-select row: This is the name of the DRAM signal used to select the
325 * DRAM ranks to be accessed. Common chip-select rows for
326 * single channel are 64 bits, for dual channel 128 bits.
327 * It may not be visible by the memory controller, as some
328 * DIMM types have a memory buffer that can hide direct
329 * access to it from the Memory Controller.
331 * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memory.
332 * Motherboards commonly drive two chip-select pins to
333 * a memory stick. A single-ranked stick, will occupy
334 * only one of those rows. The other will be unused.
336 * Double-Ranked stick: A double-ranked stick has two chip-select rows which
337 * access different sets of memory devices. The two
338 * rows cannot be accessed concurrently.
340 * Double-sided stick: DEPRECATED TERM, see Double-Ranked stick.
341 * A double-sided stick has two chip-select rows which
342 * access different sets of memory devices. The two
343 * rows cannot be accessed concurrently. "Double-sided"
344 * is irrespective of the memory devices being mounted
345 * on both sides of the memory stick.
347 * Socket set: All of the memory sticks that are required for
348 * a single memory access or all of the memory sticks
349 * spanned by a chip-select row. A single socket set
350 * has two chip-select rows and if double-sided sticks
351 * are used these will occupy those chip-select rows.
353 * Bank: This term is avoided because it is unclear when
354 * needing to distinguish between chip-select rows and
364 * STRUCTURE ORGANIZATION AND CHOICES
368 * PS - I enjoyed writing all that about as much as you enjoyed reading it.
372 * enum edac_mc_layer - memory controller hierarchy layer
374 * @EDAC_MC_LAYER_BRANCH: memory layer is named "branch"
375 * @EDAC_MC_LAYER_CHANNEL: memory layer is named "channel"
376 * @EDAC_MC_LAYER_SLOT: memory layer is named "slot"
377 * @EDAC_MC_LAYER_CHIP_SELECT: memory layer is named "chip select"
379 * This enum is used by the drivers to tell edac_mc_sysfs what name should
380 * be used when describing a memory stick location.
382 enum edac_mc_layer_type {
383 EDAC_MC_LAYER_BRANCH,
384 EDAC_MC_LAYER_CHANNEL,
386 EDAC_MC_LAYER_CHIP_SELECT,
390 * struct edac_mc_layer - describes the memory controller hierarchy
392 * @size: number of components per layer. For example,
393 * if the channel layer has two channels, size = 2
394 * @is_virt_csrow: This layer is part of the "csrow" when old API
395 * compatibility mode is enabled. Otherwise, it is
398 struct edac_mc_layer {
399 enum edac_mc_layer_type type;
405 * Maximum number of layers used by the memory controller to uniquely
406 * identify a single memory stick.
407 * NOTE: Changing this constant requires not only to change the constant
408 * below, but also to change the existing code at the core, as there are
409 * some code there that are optimized for 3 layers.
411 #define EDAC_MAX_LAYERS 3
414 * EDAC_DIMM_OFF - Macro responsible to get a pointer offset inside a pointer array
415 * for the element given by [layer0,layer1,layer2] position
417 * @layers: a struct edac_mc_layer array, describing how many elements
418 * were allocated for each layer
419 * @n_layers: Number of layers at the @layers array
420 * @layer0: layer0 position
421 * @layer1: layer1 position. Unused if n_layers < 2
422 * @layer2: layer2 position. Unused if n_layers < 3
424 * For 1 layer, this macro returns &var[layer0] - &var
425 * For 2 layers, this macro is similar to allocate a bi-dimensional array
426 * and to return "&var[layer0][layer1] - &var"
427 * For 3 layers, this macro is similar to allocate a tri-dimensional array
428 * and to return "&var[layer0][layer1][layer2] - &var"
430 * A loop could be used here to make it more generic, but, as we only have
431 * 3 layers, this is a little faster.
432 * By design, layers can never be 0 or more than 3. If that ever happens,
433 * a NULL is returned, causing an OOPS during the memory allocation routine,
434 * with would point to the developer that he's doing something wrong.
436 #define EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2) ({ \
438 if ((nlayers) == 1) \
440 else if ((nlayers) == 2) \
441 __i = (layer1) + ((layers[1]).size * (layer0)); \
442 else if ((nlayers) == 3) \
443 __i = (layer2) + ((layers[2]).size * ((layer1) + \
444 ((layers[1]).size * (layer0)))); \
451 * EDAC_DIMM_PTR - Macro responsible to get a pointer inside a pointer array
452 * for the element given by [layer0,layer1,layer2] position
454 * @layers: a struct edac_mc_layer array, describing how many elements
455 * were allocated for each layer
456 * @var: name of the var where we want to get the pointer
458 * @n_layers: Number of layers at the @layers array
459 * @layer0: layer0 position
460 * @layer1: layer1 position. Unused if n_layers < 2
461 * @layer2: layer2 position. Unused if n_layers < 3
463 * For 1 layer, this macro returns &var[layer0]
464 * For 2 layers, this macro is similar to allocate a bi-dimensional array
465 * and to return "&var[layer0][layer1]"
466 * For 3 layers, this macro is similar to allocate a tri-dimensional array
467 * and to return "&var[layer0][layer1][layer2]"
469 #define EDAC_DIMM_PTR(layers, var, nlayers, layer0, layer1, layer2) ({ \
471 int ___i = EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2); \
482 char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */
484 /* Memory location data */
485 unsigned location[EDAC_MAX_LAYERS];
487 struct mem_ctl_info *mci; /* the parent */
489 u32 grain; /* granularity of reported error in bytes */
490 enum dev_type dtype; /* memory device type */
491 enum mem_type mtype; /* memory dimm type */
492 enum edac_type edac_mode; /* EDAC mode for this dimm */
494 u32 nr_pages; /* number of pages on this dimm */
496 unsigned csrow, cschannel; /* Points to the old API data */
500 * struct rank_info - contains the information for one DIMM rank
502 * @chan_idx: channel number where the rank is (typically, 0 or 1)
503 * @ce_count: number of correctable errors for this rank
504 * @csrow: A pointer to the chip select row structure (the parent
505 * structure). The location of the rank is given by
506 * the (csrow->csrow_idx, chan_idx) vector.
507 * @dimm: A pointer to the DIMM structure, where the DIMM label
508 * information is stored.
510 * FIXME: Currently, the EDAC core model will assume one DIMM per rank.
511 * This is a bad assumption, but it makes this patch easier. Later
512 * patches in this series will fix this issue.
516 struct csrow_info *csrow;
517 struct dimm_info *dimm;
519 u32 ce_count; /* Correctable Errors for this csrow */
525 /* Used only by edac_mc_find_csrow_by_page() */
526 unsigned long first_page; /* first page number in csrow */
527 unsigned long last_page; /* last page number in csrow */
528 unsigned long page_mask; /* used for interleaving -
529 * 0UL for non intlv */
531 int csrow_idx; /* the chip-select row */
533 u32 ue_count; /* Uncorrectable Errors for this csrow */
534 u32 ce_count; /* Correctable Errors for this csrow */
535 u32 nr_pages; /* combined pages count of all channels */
537 struct mem_ctl_info *mci; /* the parent */
539 /* channel information for this csrow */
541 struct rank_info **channels;
545 * struct errcount_attribute - used to store the several error counts
547 struct errcount_attribute_data {
549 int pos[EDAC_MAX_LAYERS];
550 int layer0, layer1, layer2;
553 /* MEMORY controller information structure
555 struct mem_ctl_info {
559 struct list_head link; /* for global list of mem_ctl_info structs */
561 struct module *owner; /* Module owner of this control struct */
563 unsigned long mtype_cap; /* memory types supported by mc */
564 unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */
565 unsigned long edac_cap; /* configuration capabilities - this is
566 * closely related to edac_ctl_cap. The
567 * difference is that the controller may be
568 * capable of s4ecd4ed which would be listed
569 * in edac_ctl_cap, but if channels aren't
570 * capable of s4ecd4ed then the edac_cap would
571 * not have that capability.
573 unsigned long scrub_cap; /* chipset scrub capabilities */
574 enum scrub_type scrub_mode; /* current scrub mode */
576 /* Translates sdram memory scrub rate given in bytes/sec to the
577 internal representation and configures whatever else needs
580 int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 bw);
582 /* Get the current sdram memory scrub rate from the internal
583 representation and converts it to the closest matching
584 bandwidth in bytes/sec.
586 int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci);
589 /* pointer to edac checking routine */
590 void (*edac_check) (struct mem_ctl_info * mci);
593 * Remaps memory pages: controller pages to physical pages.
594 * For most MC's, this will be NULL.
596 /* FIXME - why not send the phys page to begin with? */
597 unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
600 struct csrow_info **csrows;
601 unsigned nr_csrows, num_cschannel;
604 * Memory Controller hierarchy
606 * There are basically two types of memory controller: the ones that
607 * sees memory sticks ("dimms"), and the ones that sees memory ranks.
608 * All old memory controllers enumerate memories per rank, but most
609 * of the recent drivers enumerate memories per DIMM, instead.
610 * When the memory controller is per rank, mem_is_per_rank is true.
613 struct edac_mc_layer *layers;
614 bool mem_is_per_rank;
617 * DIMM info. Will eventually remove the entire csrows_info some day
620 struct dimm_info **dimms;
623 * FIXME - what about controllers on other busses? - IDs must be
624 * unique. dev pointer should be sufficiently unique, but
625 * BUS:SLOT.FUNC numbers may not be unique.
628 const char *mod_name;
630 const char *ctl_name;
631 const char *dev_name;
632 char proc_name[MC_PROC_NAME_MAX_LEN + 1];
634 unsigned long start_time; /* mci load start time (in jiffies) */
637 * drivers shouldn't access those fields directly, as the core
638 * already handles that.
640 u32 ce_noinfo_count, ue_noinfo_count;
642 u32 *ce_per_layer[EDAC_MAX_LAYERS], *ue_per_layer[EDAC_MAX_LAYERS];
644 struct completion complete;
646 /* Additional top controller level attributes, but specified
647 * by the low level driver.
649 * Set by the low level driver to provide attributes at the
651 * An array of structures, NULL terminated
653 * If attributes are desired, then set to array of attributes
654 * If no attributes are desired, leave NULL
656 const struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
658 /* work struct for this MC */
659 struct delayed_work work;
661 /* the internal state of this controller instance */
664 #ifdef CONFIG_EDAC_DEBUG
665 struct dentry *debugfs;
666 u8 fake_inject_layer[EDAC_MAX_LAYERS];
668 u16 fake_inject_count;
670 __u8 csbased : 1, /* csrow-based memory controller */