5 * Please do not include this file in generic code. There is currently
6 * no requirement for any architecture to implement anything held
12 #include <linux/smp.h>
13 #include <linux/linkage.h>
14 #include <linux/cache.h>
15 #include <linux/spinlock.h>
16 #include <linux/cpumask.h>
17 #include <linux/gfp.h>
18 #include <linux/irqhandler.h>
19 #include <linux/irqreturn.h>
20 #include <linux/irqnr.h>
21 #include <linux/errno.h>
22 #include <linux/topology.h>
23 #include <linux/wait.h>
26 #include <asm/ptrace.h>
27 #include <asm/irq_regs.h>
36 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
38 * IRQ_TYPE_NONE - default, unspecified type
39 * IRQ_TYPE_EDGE_RISING - rising edge triggered
40 * IRQ_TYPE_EDGE_FALLING - falling edge triggered
41 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
42 * IRQ_TYPE_LEVEL_HIGH - high level triggered
43 * IRQ_TYPE_LEVEL_LOW - low level triggered
44 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
45 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits
46 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type
47 * to setup the HW to a sane default (used
48 * by irqdomain map() callbacks to synchronize
49 * the HW state and SW flags for a newly
50 * allocated descriptor).
52 * IRQ_TYPE_PROBE - Special flag for probing in progress
54 * Bits which can be modified via irq_set/clear/modify_status_flags()
55 * IRQ_LEVEL - Interrupt is level type. Will be also
56 * updated in the code when the above trigger
57 * bits are modified via irq_set_irq_type()
58 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect
59 * it from affinity setting
60 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing
61 * IRQ_NOREQUEST - Interrupt cannot be requested via
63 * IRQ_NOTHREAD - Interrupt cannot be threaded
64 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in
66 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set)
67 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context
68 * IRQ_NESTED_TRHEAD - Interrupt nests into another thread
69 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable
70 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude
71 * it from the spurious interrupt detection
72 * mechanism and from core side polling.
75 IRQ_TYPE_NONE = 0x00000000,
76 IRQ_TYPE_EDGE_RISING = 0x00000001,
77 IRQ_TYPE_EDGE_FALLING = 0x00000002,
78 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
79 IRQ_TYPE_LEVEL_HIGH = 0x00000004,
80 IRQ_TYPE_LEVEL_LOW = 0x00000008,
81 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
82 IRQ_TYPE_SENSE_MASK = 0x0000000f,
83 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK,
85 IRQ_TYPE_PROBE = 0x00000010,
88 IRQ_PER_CPU = (1 << 9),
89 IRQ_NOPROBE = (1 << 10),
90 IRQ_NOREQUEST = (1 << 11),
91 IRQ_NOAUTOEN = (1 << 12),
92 IRQ_NO_BALANCING = (1 << 13),
93 IRQ_MOVE_PCNTXT = (1 << 14),
94 IRQ_NESTED_THREAD = (1 << 15),
95 IRQ_NOTHREAD = (1 << 16),
96 IRQ_PER_CPU_DEVID = (1 << 17),
97 IRQ_IS_POLLED = (1 << 18),
100 #define IRQF_MODIFY_MASK \
101 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
102 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
103 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \
106 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
109 * Return value for chip->irq_set_affinity()
111 * IRQ_SET_MASK_OK - OK, core updates irq_data.affinity
112 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_data.affinity
113 * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to
114 * support stacked irqchips, which indicates skipping
115 * all descendent irqchips.
119 IRQ_SET_MASK_OK_NOCOPY,
120 IRQ_SET_MASK_OK_DONE,
127 * struct irq_data - per irq and irq chip data passed down to chip functions
128 * @mask: precomputed bitmask for accessing the chip registers
129 * @irq: interrupt number
130 * @hwirq: hardware interrupt number, local to the interrupt domain
131 * @node: node index useful for balancing
132 * @state_use_accessors: status information for irq chip functions.
133 * Use accessor functions to deal with it
134 * @chip: low level interrupt hardware access
135 * @domain: Interrupt translation domain; responsible for mapping
136 * between hwirq number and linux irq number.
137 * @parent_data: pointer to parent struct irq_data to support hierarchy
139 * @handler_data: per-IRQ data for the irq_chip methods
140 * @chip_data: platform-specific per-chip private data for the chip
141 * methods, to allow shared chip implementations
142 * @msi_desc: MSI descriptor
143 * @affinity: IRQ affinity on SMP
145 * The fields here need to overlay the ones in irq_desc until we
146 * cleaned up the direct references and switched everything over to
154 unsigned int state_use_accessors;
155 struct irq_chip *chip;
156 struct irq_domain *domain;
157 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
158 struct irq_data *parent_data;
162 struct msi_desc *msi_desc;
163 cpumask_var_t affinity;
167 * Bit masks for irq_data.state
169 * IRQD_TRIGGER_MASK - Mask for the trigger type bits
170 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending
171 * IRQD_NO_BALANCING - Balancing disabled for this IRQ
172 * IRQD_PER_CPU - Interrupt is per cpu
173 * IRQD_AFFINITY_SET - Interrupt affinity was set
174 * IRQD_LEVEL - Interrupt is level triggered
175 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup
177 * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process
179 * IRQD_IRQ_DISABLED - Disabled state of the interrupt
180 * IRQD_IRQ_MASKED - Masked state of the interrupt
181 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt
182 * IRQD_WAKEUP_ARMED - Wakeup mode armed
185 IRQD_TRIGGER_MASK = 0xf,
186 IRQD_SETAFFINITY_PENDING = (1 << 8),
187 IRQD_NO_BALANCING = (1 << 10),
188 IRQD_PER_CPU = (1 << 11),
189 IRQD_AFFINITY_SET = (1 << 12),
190 IRQD_LEVEL = (1 << 13),
191 IRQD_WAKEUP_STATE = (1 << 14),
192 IRQD_MOVE_PCNTXT = (1 << 15),
193 IRQD_IRQ_DISABLED = (1 << 16),
194 IRQD_IRQ_MASKED = (1 << 17),
195 IRQD_IRQ_INPROGRESS = (1 << 18),
196 IRQD_WAKEUP_ARMED = (1 << 19),
199 static inline bool irqd_is_setaffinity_pending(struct irq_data *d)
201 return d->state_use_accessors & IRQD_SETAFFINITY_PENDING;
204 static inline bool irqd_is_per_cpu(struct irq_data *d)
206 return d->state_use_accessors & IRQD_PER_CPU;
209 static inline bool irqd_can_balance(struct irq_data *d)
211 return !(d->state_use_accessors & (IRQD_PER_CPU | IRQD_NO_BALANCING));
214 static inline bool irqd_affinity_was_set(struct irq_data *d)
216 return d->state_use_accessors & IRQD_AFFINITY_SET;
219 static inline void irqd_mark_affinity_was_set(struct irq_data *d)
221 d->state_use_accessors |= IRQD_AFFINITY_SET;
224 static inline u32 irqd_get_trigger_type(struct irq_data *d)
226 return d->state_use_accessors & IRQD_TRIGGER_MASK;
230 * Must only be called inside irq_chip.irq_set_type() functions.
232 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type)
234 d->state_use_accessors &= ~IRQD_TRIGGER_MASK;
235 d->state_use_accessors |= type & IRQD_TRIGGER_MASK;
238 static inline bool irqd_is_level_type(struct irq_data *d)
240 return d->state_use_accessors & IRQD_LEVEL;
243 static inline bool irqd_is_wakeup_set(struct irq_data *d)
245 return d->state_use_accessors & IRQD_WAKEUP_STATE;
248 static inline bool irqd_can_move_in_process_context(struct irq_data *d)
250 return d->state_use_accessors & IRQD_MOVE_PCNTXT;
253 static inline bool irqd_irq_disabled(struct irq_data *d)
255 return d->state_use_accessors & IRQD_IRQ_DISABLED;
258 static inline bool irqd_irq_masked(struct irq_data *d)
260 return d->state_use_accessors & IRQD_IRQ_MASKED;
263 static inline bool irqd_irq_inprogress(struct irq_data *d)
265 return d->state_use_accessors & IRQD_IRQ_INPROGRESS;
268 static inline bool irqd_is_wakeup_armed(struct irq_data *d)
270 return d->state_use_accessors & IRQD_WAKEUP_ARMED;
275 * Functions for chained handlers which can be enabled/disabled by the
276 * standard disable_irq/enable_irq calls. Must be called with
277 * irq_desc->lock held.
279 static inline void irqd_set_chained_irq_inprogress(struct irq_data *d)
281 d->state_use_accessors |= IRQD_IRQ_INPROGRESS;
284 static inline void irqd_clr_chained_irq_inprogress(struct irq_data *d)
286 d->state_use_accessors &= ~IRQD_IRQ_INPROGRESS;
289 static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
295 * struct irq_chip - hardware interrupt chip descriptor
297 * @name: name for /proc/interrupts
298 * @irq_startup: start up the interrupt (defaults to ->enable if NULL)
299 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL)
300 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL)
301 * @irq_disable: disable the interrupt
302 * @irq_ack: start of a new interrupt
303 * @irq_mask: mask an interrupt source
304 * @irq_mask_ack: ack and mask an interrupt source
305 * @irq_unmask: unmask an interrupt source
306 * @irq_eoi: end of interrupt
307 * @irq_set_affinity: set the CPU affinity on SMP machines
308 * @irq_retrigger: resend an IRQ to the CPU
309 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
310 * @irq_set_wake: enable/disable power-management wake-on of an IRQ
311 * @irq_bus_lock: function to lock access to slow bus (i2c) chips
312 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
313 * @irq_cpu_online: configure an interrupt source for a secondary CPU
314 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU
315 * @irq_suspend: function called from core code on suspend once per chip
316 * @irq_resume: function called from core code on resume once per chip
317 * @irq_pm_shutdown: function called from core code on shutdown once per chip
318 * @irq_calc_mask: Optional function to set irq_data.mask for special cases
319 * @irq_print_chip: optional to print special chip info in show_interrupts
320 * @irq_request_resources: optional to request resources before calling
321 * any other callback related to this irq
322 * @irq_release_resources: optional to release resources acquired with
323 * irq_request_resources
324 * @irq_compose_msi_msg: optional to compose message content for MSI
325 * @irq_write_msi_msg: optional to write message content for MSI
326 * @flags: chip specific flags
330 unsigned int (*irq_startup)(struct irq_data *data);
331 void (*irq_shutdown)(struct irq_data *data);
332 void (*irq_enable)(struct irq_data *data);
333 void (*irq_disable)(struct irq_data *data);
335 void (*irq_ack)(struct irq_data *data);
336 void (*irq_mask)(struct irq_data *data);
337 void (*irq_mask_ack)(struct irq_data *data);
338 void (*irq_unmask)(struct irq_data *data);
339 void (*irq_eoi)(struct irq_data *data);
341 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
342 int (*irq_retrigger)(struct irq_data *data);
343 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type);
344 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
346 void (*irq_bus_lock)(struct irq_data *data);
347 void (*irq_bus_sync_unlock)(struct irq_data *data);
349 void (*irq_cpu_online)(struct irq_data *data);
350 void (*irq_cpu_offline)(struct irq_data *data);
352 void (*irq_suspend)(struct irq_data *data);
353 void (*irq_resume)(struct irq_data *data);
354 void (*irq_pm_shutdown)(struct irq_data *data);
356 void (*irq_calc_mask)(struct irq_data *data);
358 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p);
359 int (*irq_request_resources)(struct irq_data *data);
360 void (*irq_release_resources)(struct irq_data *data);
362 void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg);
363 void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg);
369 * irq_chip specific flags
371 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type()
372 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled
373 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path
374 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks
376 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip
377 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask
378 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode
381 IRQCHIP_SET_TYPE_MASKED = (1 << 0),
382 IRQCHIP_EOI_IF_HANDLED = (1 << 1),
383 IRQCHIP_MASK_ON_SUSPEND = (1 << 2),
384 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3),
385 IRQCHIP_SKIP_SET_WAKE = (1 << 4),
386 IRQCHIP_ONESHOT_SAFE = (1 << 5),
387 IRQCHIP_EOI_THREADED = (1 << 6),
390 /* This include will go away once we isolated irq_desc usage to core code */
391 #include <linux/irqdesc.h>
394 * Pick up the arch-dependent methods:
396 #include <asm/hw_irq.h>
398 #ifndef NR_IRQS_LEGACY
399 # define NR_IRQS_LEGACY 0
402 #ifndef ARCH_IRQ_INIT_FLAGS
403 # define ARCH_IRQ_INIT_FLAGS 0
406 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS
409 extern int setup_irq(unsigned int irq, struct irqaction *new);
410 extern void remove_irq(unsigned int irq, struct irqaction *act);
411 extern int setup_percpu_irq(unsigned int irq, struct irqaction *new);
412 extern void remove_percpu_irq(unsigned int irq, struct irqaction *act);
414 extern void irq_cpu_online(void);
415 extern void irq_cpu_offline(void);
416 extern int irq_set_affinity_locked(struct irq_data *data,
417 const struct cpumask *cpumask, bool force);
419 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
420 void irq_move_irq(struct irq_data *data);
421 void irq_move_masked_irq(struct irq_data *data);
423 static inline void irq_move_irq(struct irq_data *data) { }
424 static inline void irq_move_masked_irq(struct irq_data *data) { }
427 extern int no_irq_affinity;
429 #ifdef CONFIG_HARDIRQS_SW_RESEND
430 int irq_set_parent(int irq, int parent_irq);
432 static inline int irq_set_parent(int irq, int parent_irq)
439 * Built-in IRQ handlers for various IRQ types,
440 * callable via desc->handle_irq()
442 extern void handle_level_irq(unsigned int irq, struct irq_desc *desc);
443 extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc);
444 extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc);
445 extern void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc);
446 extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc);
447 extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc);
448 extern void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc);
449 extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc);
450 extern void handle_nested_irq(unsigned int irq);
452 extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg);
453 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
454 extern void irq_chip_ack_parent(struct irq_data *data);
455 extern int irq_chip_retrigger_hierarchy(struct irq_data *data);
456 extern void irq_chip_mask_parent(struct irq_data *data);
457 extern void irq_chip_unmask_parent(struct irq_data *data);
458 extern void irq_chip_eoi_parent(struct irq_data *data);
459 extern int irq_chip_set_affinity_parent(struct irq_data *data,
460 const struct cpumask *dest,
464 /* Handling of unhandled and spurious interrupts: */
465 extern void note_interrupt(unsigned int irq, struct irq_desc *desc,
466 irqreturn_t action_ret);
469 /* Enable/disable irq debugging output: */
470 extern int noirqdebug_setup(char *str);
472 /* Checks whether the interrupt can be requested by request_irq(): */
473 extern int can_request_irq(unsigned int irq, unsigned long irqflags);
475 /* Dummy irq-chip implementations: */
476 extern struct irq_chip no_irq_chip;
477 extern struct irq_chip dummy_irq_chip;
480 irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
481 irq_flow_handler_t handle, const char *name);
483 static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip,
484 irq_flow_handler_t handle)
486 irq_set_chip_and_handler_name(irq, chip, handle, NULL);
489 extern int irq_set_percpu_devid(unsigned int irq);
492 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
496 irq_set_handler(unsigned int irq, irq_flow_handler_t handle)
498 __irq_set_handler(irq, handle, 0, NULL);
502 * Set a highlevel chained flow handler for a given IRQ.
503 * (a chained handler is automatically enabled and set to
504 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
507 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle)
509 __irq_set_handler(irq, handle, 1, NULL);
512 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set);
514 static inline void irq_set_status_flags(unsigned int irq, unsigned long set)
516 irq_modify_status(irq, 0, set);
519 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr)
521 irq_modify_status(irq, clr, 0);
524 static inline void irq_set_noprobe(unsigned int irq)
526 irq_modify_status(irq, 0, IRQ_NOPROBE);
529 static inline void irq_set_probe(unsigned int irq)
531 irq_modify_status(irq, IRQ_NOPROBE, 0);
534 static inline void irq_set_nothread(unsigned int irq)
536 irq_modify_status(irq, 0, IRQ_NOTHREAD);
539 static inline void irq_set_thread(unsigned int irq)
541 irq_modify_status(irq, IRQ_NOTHREAD, 0);
544 static inline void irq_set_nested_thread(unsigned int irq, bool nest)
547 irq_set_status_flags(irq, IRQ_NESTED_THREAD);
549 irq_clear_status_flags(irq, IRQ_NESTED_THREAD);
552 static inline void irq_set_percpu_devid_flags(unsigned int irq)
554 irq_set_status_flags(irq,
555 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD |
556 IRQ_NOPROBE | IRQ_PER_CPU_DEVID);
559 /* Set/get chip/data for an IRQ: */
560 extern int irq_set_chip(unsigned int irq, struct irq_chip *chip);
561 extern int irq_set_handler_data(unsigned int irq, void *data);
562 extern int irq_set_chip_data(unsigned int irq, void *data);
563 extern int irq_set_irq_type(unsigned int irq, unsigned int type);
564 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry);
565 extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
566 struct msi_desc *entry);
567 extern struct irq_data *irq_get_irq_data(unsigned int irq);
569 static inline struct irq_chip *irq_get_chip(unsigned int irq)
571 struct irq_data *d = irq_get_irq_data(irq);
572 return d ? d->chip : NULL;
575 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d)
580 static inline void *irq_get_chip_data(unsigned int irq)
582 struct irq_data *d = irq_get_irq_data(irq);
583 return d ? d->chip_data : NULL;
586 static inline void *irq_data_get_irq_chip_data(struct irq_data *d)
591 static inline void *irq_get_handler_data(unsigned int irq)
593 struct irq_data *d = irq_get_irq_data(irq);
594 return d ? d->handler_data : NULL;
597 static inline void *irq_data_get_irq_handler_data(struct irq_data *d)
599 return d->handler_data;
602 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq)
604 struct irq_data *d = irq_get_irq_data(irq);
605 return d ? d->msi_desc : NULL;
608 static inline struct msi_desc *irq_data_get_msi(struct irq_data *d)
613 static inline u32 irq_get_trigger_type(unsigned int irq)
615 struct irq_data *d = irq_get_irq_data(irq);
616 return d ? irqd_get_trigger_type(d) : 0;
619 unsigned int arch_dynirq_lower_bound(unsigned int from);
621 int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
622 struct module *owner);
624 /* use macros to avoid needing export.h for THIS_MODULE */
625 #define irq_alloc_descs(irq, from, cnt, node) \
626 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE)
628 #define irq_alloc_desc(node) \
629 irq_alloc_descs(-1, 0, 1, node)
631 #define irq_alloc_desc_at(at, node) \
632 irq_alloc_descs(at, at, 1, node)
634 #define irq_alloc_desc_from(from, node) \
635 irq_alloc_descs(-1, from, 1, node)
637 #define irq_alloc_descs_from(from, cnt, node) \
638 irq_alloc_descs(-1, from, cnt, node)
640 void irq_free_descs(unsigned int irq, unsigned int cnt);
641 static inline void irq_free_desc(unsigned int irq)
643 irq_free_descs(irq, 1);
646 #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ
647 unsigned int irq_alloc_hwirqs(int cnt, int node);
648 static inline unsigned int irq_alloc_hwirq(int node)
650 return irq_alloc_hwirqs(1, node);
652 void irq_free_hwirqs(unsigned int from, int cnt);
653 static inline void irq_free_hwirq(unsigned int irq)
655 return irq_free_hwirqs(irq, 1);
657 int arch_setup_hwirq(unsigned int irq, int node);
658 void arch_teardown_hwirq(unsigned int irq);
661 #ifdef CONFIG_GENERIC_IRQ_LEGACY
662 void irq_init_desc(unsigned int irq);
665 #ifndef irq_reg_writel
666 # define irq_reg_writel(val, addr) writel(val, addr)
668 #ifndef irq_reg_readl
669 # define irq_reg_readl(addr) readl(addr)
673 * struct irq_chip_regs - register offsets for struct irq_gci
674 * @enable: Enable register offset to reg_base
675 * @disable: Disable register offset to reg_base
676 * @mask: Mask register offset to reg_base
677 * @ack: Ack register offset to reg_base
678 * @eoi: Eoi register offset to reg_base
679 * @type: Type configuration register offset to reg_base
680 * @polarity: Polarity configuration register offset to reg_base
682 struct irq_chip_regs {
683 unsigned long enable;
684 unsigned long disable;
689 unsigned long polarity;
693 * struct irq_chip_type - Generic interrupt chip instance for a flow type
694 * @chip: The real interrupt chip which provides the callbacks
695 * @regs: Register offsets for this chip
696 * @handler: Flow handler associated with this chip
697 * @type: Chip can handle these flow types
698 * @mask_cache_priv: Cached mask register private to the chip type
699 * @mask_cache: Pointer to cached mask register
701 * A irq_generic_chip can have several instances of irq_chip_type when
702 * it requires different functions and register offsets for different
705 struct irq_chip_type {
706 struct irq_chip chip;
707 struct irq_chip_regs regs;
708 irq_flow_handler_t handler;
715 * struct irq_chip_generic - Generic irq chip data structure
716 * @lock: Lock to protect register and cache data access
717 * @reg_base: Register base address (virtual)
718 * @irq_base: Interrupt base nr for this chip
719 * @irq_cnt: Number of interrupts handled by this chip
720 * @mask_cache: Cached mask register shared between all chip types
721 * @type_cache: Cached type register
722 * @polarity_cache: Cached polarity register
723 * @wake_enabled: Interrupt can wakeup from suspend
724 * @wake_active: Interrupt is marked as an wakeup from suspend source
725 * @num_ct: Number of available irq_chip_type instances (usually 1)
726 * @private: Private data for non generic chip callbacks
727 * @installed: bitfield to denote installed interrupts
728 * @unused: bitfield to denote unused interrupts
729 * @domain: irq domain pointer
730 * @list: List head for keeping track of instances
731 * @chip_types: Array of interrupt irq_chip_types
733 * Note, that irq_chip_generic can have multiple irq_chip_type
734 * implementations which can be associated to a particular irq line of
735 * an irq_chip_generic instance. That allows to share and protect
736 * state in an irq_chip_generic instance when we need to implement
737 * different flow mechanisms (level/edge) for it.
739 struct irq_chip_generic {
741 void __iomem *reg_base;
742 unsigned int irq_base;
743 unsigned int irq_cnt;
751 unsigned long installed;
752 unsigned long unused;
753 struct irq_domain *domain;
754 struct list_head list;
755 struct irq_chip_type chip_types[0];
759 * enum irq_gc_flags - Initialization flags for generic irq chips
760 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg
761 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for
762 * irq chips which need to call irq_set_wake() on
763 * the parent irq. Usually GPIO implementations
764 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
765 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
768 IRQ_GC_INIT_MASK_CACHE = 1 << 0,
769 IRQ_GC_INIT_NESTED_LOCK = 1 << 1,
770 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2,
771 IRQ_GC_NO_MASK = 1 << 3,
775 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains
776 * @irqs_per_chip: Number of interrupts per chip
777 * @num_chips: Number of chips
778 * @irq_flags_to_set: IRQ* flags to set on irq setup
779 * @irq_flags_to_clear: IRQ* flags to clear on irq setup
780 * @gc_flags: Generic chip specific setup flags
781 * @gc: Array of pointers to generic interrupt chips
783 struct irq_domain_chip_generic {
784 unsigned int irqs_per_chip;
785 unsigned int num_chips;
786 unsigned int irq_flags_to_clear;
787 unsigned int irq_flags_to_set;
788 enum irq_gc_flags gc_flags;
789 struct irq_chip_generic *gc[0];
792 /* Generic chip callback functions */
793 void irq_gc_noop(struct irq_data *d);
794 void irq_gc_mask_disable_reg(struct irq_data *d);
795 void irq_gc_mask_set_bit(struct irq_data *d);
796 void irq_gc_mask_clr_bit(struct irq_data *d);
797 void irq_gc_unmask_enable_reg(struct irq_data *d);
798 void irq_gc_ack_set_bit(struct irq_data *d);
799 void irq_gc_ack_clr_bit(struct irq_data *d);
800 void irq_gc_mask_disable_reg_and_ack(struct irq_data *d);
801 void irq_gc_eoi(struct irq_data *d);
802 int irq_gc_set_wake(struct irq_data *d, unsigned int on);
804 /* Setup functions for irq_chip_generic */
805 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
806 irq_hw_number_t hw_irq);
807 struct irq_chip_generic *
808 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
809 void __iomem *reg_base, irq_flow_handler_t handler);
810 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
811 enum irq_gc_flags flags, unsigned int clr,
813 int irq_setup_alt_chip(struct irq_data *d, unsigned int type);
814 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
815 unsigned int clr, unsigned int set);
817 struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq);
818 int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
819 int num_ct, const char *name,
820 irq_flow_handler_t handler,
821 unsigned int clr, unsigned int set,
822 enum irq_gc_flags flags);
825 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d)
827 return container_of(d->chip, struct irq_chip_type, chip);
830 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
833 static inline void irq_gc_lock(struct irq_chip_generic *gc)
835 raw_spin_lock(&gc->lock);
838 static inline void irq_gc_unlock(struct irq_chip_generic *gc)
840 raw_spin_unlock(&gc->lock);
843 static inline void irq_gc_lock(struct irq_chip_generic *gc) { }
844 static inline void irq_gc_unlock(struct irq_chip_generic *gc) { }
847 #endif /* _LINUX_IRQ_H */