4 * Copyright 2011-2013 Texas Instruments Inc.
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
7 * Author: Ian Lartey <ian@slimlogic.co.uk>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
16 #ifndef __LINUX_MFD_PALMAS_H
17 #define __LINUX_MFD_PALMAS_H
19 #include <linux/usb/otg.h>
20 #include <linux/leds.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/driver.h>
23 #include <linux/extcon.h>
24 #include <linux/usb/phy_companion.h>
26 #define PALMAS_NUM_CLIENTS 3
28 /* The ID_REVISION NUMBERS */
29 #define PALMAS_CHIP_OLD_ID 0x0000
30 #define PALMAS_CHIP_ID 0xC035
31 #define PALMAS_CHIP_CHARGER_ID 0xC036
33 #define is_palmas(a) (((a) == PALMAS_CHIP_OLD_ID) || \
34 ((a) == PALMAS_CHIP_ID))
35 #define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID)
38 * Palmas PMIC feature types
40 * PALMAS_PMIC_FEATURE_SMPS10_BOOST - used when the PMIC provides SMPS10_BOOST
43 * PALMAS_PMIC_HAS(b, f) - macro to check if a bandgap device is capable of a
44 * specific feature (above) or not. Return non-zero, if yes.
46 #define PALMAS_PMIC_FEATURE_SMPS10_BOOST BIT(0)
47 #define PALMAS_PMIC_HAS(b, f) \
48 ((b)->features & PALMAS_PMIC_FEATURE_ ## f)
52 struct palmas_resource;
55 enum palmas_usb_state {
56 PALMAS_USB_STATE_DISCONNECT,
57 PALMAS_USB_STATE_VBUS,
64 struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS];
65 struct regmap *regmap[PALMAS_NUM_CLIENTS];
70 unsigned int features;
74 struct mutex irq_lock;
75 struct regmap_irq_chip_data *irq_data;
78 struct palmas_pmic *pmic;
79 struct palmas_gpadc *gpadc;
80 struct palmas_resource *resource;
81 struct palmas_usb *usb;
89 struct palmas_gpadc_platform_data {
90 /* Channel 3 current source is only enabled during conversion */
93 /* Channel 0 current source can be used for battery detection.
94 * If used for battery detection this will cause a permanent current
95 * consumption depending on current level set here.
99 /* default BAT_REMOVAL_DAT setting on device probe */
102 /* Sets the START_POLARITY bit in the RT_CTRL register */
106 struct palmas_reg_init {
107 /* warm_rest controls the voltage levels after a warm reset
109 * 0: reload default values from OTP on warm reset
110 * 1: maintain voltage from VSEL on warm reset
114 /* roof_floor controls whether the regulator uses the i2c style
115 * of DVS or uses the method where a GPIO or other control method is
116 * attached to the NSLEEP/ENABLE1/ENABLE2 pins
120 * 0: i2c selection of voltage
121 * 1: pin selection of voltage.
127 /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in
144 /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE
145 * register. Set this is the default voltage set in OTP needs
152 enum palmas_regulators {
153 /* SMPS regulators */
163 PALMAS_REG_SMPS10_OUT2,
164 PALMAS_REG_SMPS10_OUT1,
177 /* External regulators */
183 /* Total number of regulators */
187 /* External controll signal name */
189 PALMAS_EXT_CONTROL_ENABLE1 = 0x1,
190 PALMAS_EXT_CONTROL_ENABLE2 = 0x2,
191 PALMAS_EXT_CONTROL_NSLEEP = 0x4,
195 * Palmas device resources can be controlled externally for
196 * enabling/disabling it rather than register write through i2c.
197 * Add the external controlled requestor ID for different resources.
199 enum palmas_external_requestor_id {
200 PALMAS_EXTERNAL_REQSTR_ID_REGEN1,
201 PALMAS_EXTERNAL_REQSTR_ID_REGEN2,
202 PALMAS_EXTERNAL_REQSTR_ID_SYSEN1,
203 PALMAS_EXTERNAL_REQSTR_ID_SYSEN2,
204 PALMAS_EXTERNAL_REQSTR_ID_CLK32KG,
205 PALMAS_EXTERNAL_REQSTR_ID_CLK32KGAUDIO,
206 PALMAS_EXTERNAL_REQSTR_ID_REGEN3,
207 PALMAS_EXTERNAL_REQSTR_ID_SMPS12,
208 PALMAS_EXTERNAL_REQSTR_ID_SMPS3,
209 PALMAS_EXTERNAL_REQSTR_ID_SMPS45,
210 PALMAS_EXTERNAL_REQSTR_ID_SMPS6,
211 PALMAS_EXTERNAL_REQSTR_ID_SMPS7,
212 PALMAS_EXTERNAL_REQSTR_ID_SMPS8,
213 PALMAS_EXTERNAL_REQSTR_ID_SMPS9,
214 PALMAS_EXTERNAL_REQSTR_ID_SMPS10,
215 PALMAS_EXTERNAL_REQSTR_ID_LDO1,
216 PALMAS_EXTERNAL_REQSTR_ID_LDO2,
217 PALMAS_EXTERNAL_REQSTR_ID_LDO3,
218 PALMAS_EXTERNAL_REQSTR_ID_LDO4,
219 PALMAS_EXTERNAL_REQSTR_ID_LDO5,
220 PALMAS_EXTERNAL_REQSTR_ID_LDO6,
221 PALMAS_EXTERNAL_REQSTR_ID_LDO7,
222 PALMAS_EXTERNAL_REQSTR_ID_LDO8,
223 PALMAS_EXTERNAL_REQSTR_ID_LDO9,
224 PALMAS_EXTERNAL_REQSTR_ID_LDOLN,
225 PALMAS_EXTERNAL_REQSTR_ID_LDOUSB,
228 PALMAS_EXTERNAL_REQSTR_ID_MAX,
231 struct palmas_pmic_platform_data {
232 /* An array of pointers to regulator init data indexed by regulator
235 struct regulator_init_data *reg_data[PALMAS_NUM_REGS];
237 /* An array of pointers to structures containing sleep mode and DVS
238 * configuration for regulators indexed by ID
240 struct palmas_reg_init *reg_init[PALMAS_NUM_REGS];
242 /* use LDO6 for vibrator control */
245 /* Enable tracking mode of LDO8 */
246 bool enable_ldo8_tracking;
249 struct palmas_usb_platform_data {
250 /* Do we enable the wakeup comparator on probe */
254 struct palmas_resource_platform_data {
255 int regen1_mode_sleep;
256 int regen2_mode_sleep;
257 int sysen1_mode_sleep;
258 int sysen2_mode_sleep;
260 /* bitfield to be loaded to NSLEEP_RES_ASSIGN */
262 /* bitfield to be loaded to NSLEEP_SMPS_ASSIGN */
264 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN1 */
266 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN2 */
269 /* bitfield to be loaded to ENABLE1_RES_ASSIGN */
271 /* bitfield to be loaded to ENABLE1_SMPS_ASSIGN */
273 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN1 */
275 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN2 */
278 /* bitfield to be loaded to ENABLE2_RES_ASSIGN */
280 /* bitfield to be loaded to ENABLE2_SMPS_ASSIGN */
282 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN1 */
284 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN2 */
288 struct palmas_clk_platform_data {
289 int clk32kg_mode_sleep;
290 int clk32kgaudio_mode_sleep;
293 struct palmas_platform_data {
297 /* bit value to be loaded to the POWER_CTRL register */
301 * boolean to select if we want to configure muxing here
302 * then the two value to load into the registers if true
308 struct palmas_pmic_platform_data *pmic_pdata;
309 struct palmas_gpadc_platform_data *gpadc_pdata;
310 struct palmas_usb_platform_data *usb_pdata;
311 struct palmas_resource_platform_data *resource_pdata;
312 struct palmas_clk_platform_data *clk_pdata;
315 struct palmas_gpadc_calibration {
321 struct palmas_gpadc {
323 struct palmas *palmas;
332 struct mutex reading_lock;
333 struct completion irq_complete;
337 struct palmas_gpadc_calibration *palmas_cal_tbl;
344 struct palmas_gpadc_result {
350 #define PALMAS_MAX_CHANNELS 16
352 /* Define the palmas IRQ numbers */
355 PALMAS_CHARG_DET_N_VBUS_OVV_IRQ,
357 PALMAS_LONG_PRESS_KEY_IRQ,
364 PALMAS_RTC_ALARM_IRQ,
365 PALMAS_RTC_TIMER_IRQ,
367 PALMAS_BATREMOVAL_IRQ,
373 PALMAS_GPADC_AUTO_0_IRQ,
374 PALMAS_GPADC_AUTO_1_IRQ,
375 PALMAS_GPADC_EOC_SW_IRQ,
376 PALMAS_GPADC_EOC_RT_IRQ,
390 /* Total Number IRQs */
395 struct palmas *palmas;
397 struct regulator_desc desc[PALMAS_NUM_REGS];
398 struct regulator_dev *rdev[PALMAS_NUM_REGS];
404 int range[PALMAS_REG_SMPS10_OUT1];
405 unsigned int ramp_delay[PALMAS_REG_SMPS10_OUT1];
406 unsigned int current_reg_mode[PALMAS_REG_SMPS10_OUT1];
409 struct palmas_resource {
410 struct palmas *palmas;
415 struct palmas *palmas;
418 struct extcon_dev *edev;
425 enum palmas_usb_state linkstat;
427 bool enable_vbus_detection;
428 bool enable_id_detection;
431 #define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator)
433 enum usb_irq_events {
434 /* Wakeup events from INT3 */
435 PALMAS_USB_ID_WAKEPUP,
436 PALMAS_USB_VBUS_WAKEUP,
448 N_PALMAS_USB_ID_FLOAT,
450 /* VBUS_OTG_EVENTS */
451 PALMAS_USB_VB_SESS_END,
452 N_PALMAS_USB_VB_SESS_END,
453 PALMAS_USB_VB_SESS_VLD,
454 N_PALMAS_USB_VB_SESS_VLD,
455 PALMAS_USB_VA_SESS_VLD,
456 N_PALMAS_USB_VA_SESS_VLD,
457 PALMAS_USB_VA_VBUS_VLD,
458 N_PALMAS_USB_VA_VBUS_VLD,
460 N_PALMAS_USB_VADP_SNS,
462 N_PALMAS_USB_VADP_PRB,
463 PALMAS_USB_VOTG_SESS_VLD,
464 N_PALMAS_USB_VOTG_SESS_VLD,
467 /* defines so we can store the mux settings */
468 #define PALMAS_GPIO_0_MUXED (1 << 0)
469 #define PALMAS_GPIO_1_MUXED (1 << 1)
470 #define PALMAS_GPIO_2_MUXED (1 << 2)
471 #define PALMAS_GPIO_3_MUXED (1 << 3)
472 #define PALMAS_GPIO_4_MUXED (1 << 4)
473 #define PALMAS_GPIO_5_MUXED (1 << 5)
474 #define PALMAS_GPIO_6_MUXED (1 << 6)
475 #define PALMAS_GPIO_7_MUXED (1 << 7)
477 #define PALMAS_LED1_MUXED (1 << 0)
478 #define PALMAS_LED2_MUXED (1 << 1)
480 #define PALMAS_PWM1_MUXED (1 << 0)
481 #define PALMAS_PWM2_MUXED (1 << 1)
483 /* helper macro to get correct slave number */
484 #define PALMAS_BASE_TO_SLAVE(x) ((x >> 8) - 1)
485 #define PALMAS_BASE_TO_REG(x, y) ((x & 0xFF) + y)
487 /* Base addresses of IP blocks in Palmas */
488 #define PALMAS_SMPS_DVS_BASE 0x020
489 #define PALMAS_RTC_BASE 0x100
490 #define PALMAS_VALIDITY_BASE 0x118
491 #define PALMAS_SMPS_BASE 0x120
492 #define PALMAS_LDO_BASE 0x150
493 #define PALMAS_DVFS_BASE 0x180
494 #define PALMAS_PMU_CONTROL_BASE 0x1A0
495 #define PALMAS_RESOURCE_BASE 0x1D4
496 #define PALMAS_PU_PD_OD_BASE 0x1F0
497 #define PALMAS_LED_BASE 0x200
498 #define PALMAS_INTERRUPT_BASE 0x210
499 #define PALMAS_USB_OTG_BASE 0x250
500 #define PALMAS_VIBRATOR_BASE 0x270
501 #define PALMAS_GPIO_BASE 0x280
502 #define PALMAS_USB_BASE 0x290
503 #define PALMAS_GPADC_BASE 0x2C0
504 #define PALMAS_TRIM_GPADC_BASE 0x3CD
506 /* Registers for function RTC */
507 #define PALMAS_SECONDS_REG 0x00
508 #define PALMAS_MINUTES_REG 0x01
509 #define PALMAS_HOURS_REG 0x02
510 #define PALMAS_DAYS_REG 0x03
511 #define PALMAS_MONTHS_REG 0x04
512 #define PALMAS_YEARS_REG 0x05
513 #define PALMAS_WEEKS_REG 0x06
514 #define PALMAS_ALARM_SECONDS_REG 0x08
515 #define PALMAS_ALARM_MINUTES_REG 0x09
516 #define PALMAS_ALARM_HOURS_REG 0x0A
517 #define PALMAS_ALARM_DAYS_REG 0x0B
518 #define PALMAS_ALARM_MONTHS_REG 0x0C
519 #define PALMAS_ALARM_YEARS_REG 0x0D
520 #define PALMAS_RTC_CTRL_REG 0x10
521 #define PALMAS_RTC_STATUS_REG 0x11
522 #define PALMAS_RTC_INTERRUPTS_REG 0x12
523 #define PALMAS_RTC_COMP_LSB_REG 0x13
524 #define PALMAS_RTC_COMP_MSB_REG 0x14
525 #define PALMAS_RTC_RES_PROG_REG 0x15
526 #define PALMAS_RTC_RESET_STATUS_REG 0x16
528 /* Bit definitions for SECONDS_REG */
529 #define PALMAS_SECONDS_REG_SEC1_MASK 0x70
530 #define PALMAS_SECONDS_REG_SEC1_SHIFT 0x04
531 #define PALMAS_SECONDS_REG_SEC0_MASK 0x0F
532 #define PALMAS_SECONDS_REG_SEC0_SHIFT 0x00
534 /* Bit definitions for MINUTES_REG */
535 #define PALMAS_MINUTES_REG_MIN1_MASK 0x70
536 #define PALMAS_MINUTES_REG_MIN1_SHIFT 0x04
537 #define PALMAS_MINUTES_REG_MIN0_MASK 0x0F
538 #define PALMAS_MINUTES_REG_MIN0_SHIFT 0x00
540 /* Bit definitions for HOURS_REG */
541 #define PALMAS_HOURS_REG_PM_NAM 0x80
542 #define PALMAS_HOURS_REG_PM_NAM_SHIFT 0x07
543 #define PALMAS_HOURS_REG_HOUR1_MASK 0x30
544 #define PALMAS_HOURS_REG_HOUR1_SHIFT 0x04
545 #define PALMAS_HOURS_REG_HOUR0_MASK 0x0F
546 #define PALMAS_HOURS_REG_HOUR0_SHIFT 0x00
548 /* Bit definitions for DAYS_REG */
549 #define PALMAS_DAYS_REG_DAY1_MASK 0x30
550 #define PALMAS_DAYS_REG_DAY1_SHIFT 0x04
551 #define PALMAS_DAYS_REG_DAY0_MASK 0x0F
552 #define PALMAS_DAYS_REG_DAY0_SHIFT 0x00
554 /* Bit definitions for MONTHS_REG */
555 #define PALMAS_MONTHS_REG_MONTH1 0x10
556 #define PALMAS_MONTHS_REG_MONTH1_SHIFT 0x04
557 #define PALMAS_MONTHS_REG_MONTH0_MASK 0x0F
558 #define PALMAS_MONTHS_REG_MONTH0_SHIFT 0x00
560 /* Bit definitions for YEARS_REG */
561 #define PALMAS_YEARS_REG_YEAR1_MASK 0xf0
562 #define PALMAS_YEARS_REG_YEAR1_SHIFT 0x04
563 #define PALMAS_YEARS_REG_YEAR0_MASK 0x0F
564 #define PALMAS_YEARS_REG_YEAR0_SHIFT 0x00
566 /* Bit definitions for WEEKS_REG */
567 #define PALMAS_WEEKS_REG_WEEK_MASK 0x07
568 #define PALMAS_WEEKS_REG_WEEK_SHIFT 0x00
570 /* Bit definitions for ALARM_SECONDS_REG */
571 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK 0x70
572 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT 0x04
573 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK 0x0F
574 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT 0x00
576 /* Bit definitions for ALARM_MINUTES_REG */
577 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK 0x70
578 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT 0x04
579 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK 0x0F
580 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT 0x00
582 /* Bit definitions for ALARM_HOURS_REG */
583 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM 0x80
584 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT 0x07
585 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK 0x30
586 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT 0x04
587 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK 0x0F
588 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT 0x00
590 /* Bit definitions for ALARM_DAYS_REG */
591 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK 0x30
592 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT 0x04
593 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK 0x0F
594 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT 0x00
596 /* Bit definitions for ALARM_MONTHS_REG */
597 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1 0x10
598 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT 0x04
599 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK 0x0F
600 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT 0x00
602 /* Bit definitions for ALARM_YEARS_REG */
603 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK 0xf0
604 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT 0x04
605 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK 0x0F
606 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT 0x00
608 /* Bit definitions for RTC_CTRL_REG */
609 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT 0x80
610 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT 0x07
611 #define PALMAS_RTC_CTRL_REG_GET_TIME 0x40
612 #define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT 0x06
613 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER 0x20
614 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT 0x05
615 #define PALMAS_RTC_CTRL_REG_TEST_MODE 0x10
616 #define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT 0x04
617 #define PALMAS_RTC_CTRL_REG_MODE_12_24 0x08
618 #define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT 0x03
619 #define PALMAS_RTC_CTRL_REG_AUTO_COMP 0x04
620 #define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT 0x02
621 #define PALMAS_RTC_CTRL_REG_ROUND_30S 0x02
622 #define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT 0x01
623 #define PALMAS_RTC_CTRL_REG_STOP_RTC 0x01
624 #define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT 0x00
626 /* Bit definitions for RTC_STATUS_REG */
627 #define PALMAS_RTC_STATUS_REG_POWER_UP 0x80
628 #define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT 0x07
629 #define PALMAS_RTC_STATUS_REG_ALARM 0x40
630 #define PALMAS_RTC_STATUS_REG_ALARM_SHIFT 0x06
631 #define PALMAS_RTC_STATUS_REG_EVENT_1D 0x20
632 #define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT 0x05
633 #define PALMAS_RTC_STATUS_REG_EVENT_1H 0x10
634 #define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT 0x04
635 #define PALMAS_RTC_STATUS_REG_EVENT_1M 0x08
636 #define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT 0x03
637 #define PALMAS_RTC_STATUS_REG_EVENT_1S 0x04
638 #define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT 0x02
639 #define PALMAS_RTC_STATUS_REG_RUN 0x02
640 #define PALMAS_RTC_STATUS_REG_RUN_SHIFT 0x01
642 /* Bit definitions for RTC_INTERRUPTS_REG */
643 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN 0x10
644 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT 0x04
645 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM 0x08
646 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT 0x03
647 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER 0x04
648 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT 0x02
649 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK 0x03
650 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT 0x00
652 /* Bit definitions for RTC_COMP_LSB_REG */
653 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK 0xFF
654 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT 0x00
656 /* Bit definitions for RTC_COMP_MSB_REG */
657 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK 0xFF
658 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT 0x00
660 /* Bit definitions for RTC_RES_PROG_REG */
661 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK 0x3F
662 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT 0x00
664 /* Bit definitions for RTC_RESET_STATUS_REG */
665 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS 0x01
666 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT 0x00
668 /* Registers for function BACKUP */
669 #define PALMAS_BACKUP0 0x00
670 #define PALMAS_BACKUP1 0x01
671 #define PALMAS_BACKUP2 0x02
672 #define PALMAS_BACKUP3 0x03
673 #define PALMAS_BACKUP4 0x04
674 #define PALMAS_BACKUP5 0x05
675 #define PALMAS_BACKUP6 0x06
676 #define PALMAS_BACKUP7 0x07
678 /* Bit definitions for BACKUP0 */
679 #define PALMAS_BACKUP0_BACKUP_MASK 0xFF
680 #define PALMAS_BACKUP0_BACKUP_SHIFT 0x00
682 /* Bit definitions for BACKUP1 */
683 #define PALMAS_BACKUP1_BACKUP_MASK 0xFF
684 #define PALMAS_BACKUP1_BACKUP_SHIFT 0x00
686 /* Bit definitions for BACKUP2 */
687 #define PALMAS_BACKUP2_BACKUP_MASK 0xFF
688 #define PALMAS_BACKUP2_BACKUP_SHIFT 0x00
690 /* Bit definitions for BACKUP3 */
691 #define PALMAS_BACKUP3_BACKUP_MASK 0xFF
692 #define PALMAS_BACKUP3_BACKUP_SHIFT 0x00
694 /* Bit definitions for BACKUP4 */
695 #define PALMAS_BACKUP4_BACKUP_MASK 0xFF
696 #define PALMAS_BACKUP4_BACKUP_SHIFT 0x00
698 /* Bit definitions for BACKUP5 */
699 #define PALMAS_BACKUP5_BACKUP_MASK 0xFF
700 #define PALMAS_BACKUP5_BACKUP_SHIFT 0x00
702 /* Bit definitions for BACKUP6 */
703 #define PALMAS_BACKUP6_BACKUP_MASK 0xFF
704 #define PALMAS_BACKUP6_BACKUP_SHIFT 0x00
706 /* Bit definitions for BACKUP7 */
707 #define PALMAS_BACKUP7_BACKUP_MASK 0xFF
708 #define PALMAS_BACKUP7_BACKUP_SHIFT 0x00
710 /* Registers for function SMPS */
711 #define PALMAS_SMPS12_CTRL 0x00
712 #define PALMAS_SMPS12_TSTEP 0x01
713 #define PALMAS_SMPS12_FORCE 0x02
714 #define PALMAS_SMPS12_VOLTAGE 0x03
715 #define PALMAS_SMPS3_CTRL 0x04
716 #define PALMAS_SMPS3_VOLTAGE 0x07
717 #define PALMAS_SMPS45_CTRL 0x08
718 #define PALMAS_SMPS45_TSTEP 0x09
719 #define PALMAS_SMPS45_FORCE 0x0A
720 #define PALMAS_SMPS45_VOLTAGE 0x0B
721 #define PALMAS_SMPS6_CTRL 0x0C
722 #define PALMAS_SMPS6_TSTEP 0x0D
723 #define PALMAS_SMPS6_FORCE 0x0E
724 #define PALMAS_SMPS6_VOLTAGE 0x0F
725 #define PALMAS_SMPS7_CTRL 0x10
726 #define PALMAS_SMPS7_VOLTAGE 0x13
727 #define PALMAS_SMPS8_CTRL 0x14
728 #define PALMAS_SMPS8_TSTEP 0x15
729 #define PALMAS_SMPS8_FORCE 0x16
730 #define PALMAS_SMPS8_VOLTAGE 0x17
731 #define PALMAS_SMPS9_CTRL 0x18
732 #define PALMAS_SMPS9_VOLTAGE 0x1B
733 #define PALMAS_SMPS10_CTRL 0x1C
734 #define PALMAS_SMPS10_STATUS 0x1F
735 #define PALMAS_SMPS_CTRL 0x24
736 #define PALMAS_SMPS_PD_CTRL 0x25
737 #define PALMAS_SMPS_DITHER_EN 0x26
738 #define PALMAS_SMPS_THERMAL_EN 0x27
739 #define PALMAS_SMPS_THERMAL_STATUS 0x28
740 #define PALMAS_SMPS_SHORT_STATUS 0x29
741 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A
742 #define PALMAS_SMPS_POWERGOOD_MASK1 0x2B
743 #define PALMAS_SMPS_POWERGOOD_MASK2 0x2C
745 /* Bit definitions for SMPS12_CTRL */
746 #define PALMAS_SMPS12_CTRL_WR_S 0x80
747 #define PALMAS_SMPS12_CTRL_WR_S_SHIFT 0x07
748 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN 0x40
749 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
750 #define PALMAS_SMPS12_CTRL_STATUS_MASK 0x30
751 #define PALMAS_SMPS12_CTRL_STATUS_SHIFT 0x04
752 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK 0x0c
753 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT 0x02
754 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK 0x03
755 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT 0x00
757 /* Bit definitions for SMPS12_TSTEP */
758 #define PALMAS_SMPS12_TSTEP_TSTEP_MASK 0x03
759 #define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT 0x00
761 /* Bit definitions for SMPS12_FORCE */
762 #define PALMAS_SMPS12_FORCE_CMD 0x80
763 #define PALMAS_SMPS12_FORCE_CMD_SHIFT 0x07
764 #define PALMAS_SMPS12_FORCE_VSEL_MASK 0x7F
765 #define PALMAS_SMPS12_FORCE_VSEL_SHIFT 0x00
767 /* Bit definitions for SMPS12_VOLTAGE */
768 #define PALMAS_SMPS12_VOLTAGE_RANGE 0x80
769 #define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT 0x07
770 #define PALMAS_SMPS12_VOLTAGE_VSEL_MASK 0x7F
771 #define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT 0x00
773 /* Bit definitions for SMPS3_CTRL */
774 #define PALMAS_SMPS3_CTRL_WR_S 0x80
775 #define PALMAS_SMPS3_CTRL_WR_S_SHIFT 0x07
776 #define PALMAS_SMPS3_CTRL_STATUS_MASK 0x30
777 #define PALMAS_SMPS3_CTRL_STATUS_SHIFT 0x04
778 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK 0x0c
779 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02
780 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03
781 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00
783 /* Bit definitions for SMPS3_VOLTAGE */
784 #define PALMAS_SMPS3_VOLTAGE_RANGE 0x80
785 #define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT 0x07
786 #define PALMAS_SMPS3_VOLTAGE_VSEL_MASK 0x7F
787 #define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT 0x00
789 /* Bit definitions for SMPS45_CTRL */
790 #define PALMAS_SMPS45_CTRL_WR_S 0x80
791 #define PALMAS_SMPS45_CTRL_WR_S_SHIFT 0x07
792 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN 0x40
793 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
794 #define PALMAS_SMPS45_CTRL_STATUS_MASK 0x30
795 #define PALMAS_SMPS45_CTRL_STATUS_SHIFT 0x04
796 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK 0x0c
797 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT 0x02
798 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK 0x03
799 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT 0x00
801 /* Bit definitions for SMPS45_TSTEP */
802 #define PALMAS_SMPS45_TSTEP_TSTEP_MASK 0x03
803 #define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT 0x00
805 /* Bit definitions for SMPS45_FORCE */
806 #define PALMAS_SMPS45_FORCE_CMD 0x80
807 #define PALMAS_SMPS45_FORCE_CMD_SHIFT 0x07
808 #define PALMAS_SMPS45_FORCE_VSEL_MASK 0x7F
809 #define PALMAS_SMPS45_FORCE_VSEL_SHIFT 0x00
811 /* Bit definitions for SMPS45_VOLTAGE */
812 #define PALMAS_SMPS45_VOLTAGE_RANGE 0x80
813 #define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT 0x07
814 #define PALMAS_SMPS45_VOLTAGE_VSEL_MASK 0x7F
815 #define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT 0x00
817 /* Bit definitions for SMPS6_CTRL */
818 #define PALMAS_SMPS6_CTRL_WR_S 0x80
819 #define PALMAS_SMPS6_CTRL_WR_S_SHIFT 0x07
820 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN 0x40
821 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
822 #define PALMAS_SMPS6_CTRL_STATUS_MASK 0x30
823 #define PALMAS_SMPS6_CTRL_STATUS_SHIFT 0x04
824 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK 0x0c
825 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT 0x02
826 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK 0x03
827 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT 0x00
829 /* Bit definitions for SMPS6_TSTEP */
830 #define PALMAS_SMPS6_TSTEP_TSTEP_MASK 0x03
831 #define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT 0x00
833 /* Bit definitions for SMPS6_FORCE */
834 #define PALMAS_SMPS6_FORCE_CMD 0x80
835 #define PALMAS_SMPS6_FORCE_CMD_SHIFT 0x07
836 #define PALMAS_SMPS6_FORCE_VSEL_MASK 0x7F
837 #define PALMAS_SMPS6_FORCE_VSEL_SHIFT 0x00
839 /* Bit definitions for SMPS6_VOLTAGE */
840 #define PALMAS_SMPS6_VOLTAGE_RANGE 0x80
841 #define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT 0x07
842 #define PALMAS_SMPS6_VOLTAGE_VSEL_MASK 0x7F
843 #define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT 0x00
845 /* Bit definitions for SMPS7_CTRL */
846 #define PALMAS_SMPS7_CTRL_WR_S 0x80
847 #define PALMAS_SMPS7_CTRL_WR_S_SHIFT 0x07
848 #define PALMAS_SMPS7_CTRL_STATUS_MASK 0x30
849 #define PALMAS_SMPS7_CTRL_STATUS_SHIFT 0x04
850 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK 0x0c
851 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT 0x02
852 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK 0x03
853 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT 0x00
855 /* Bit definitions for SMPS7_VOLTAGE */
856 #define PALMAS_SMPS7_VOLTAGE_RANGE 0x80
857 #define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT 0x07
858 #define PALMAS_SMPS7_VOLTAGE_VSEL_MASK 0x7F
859 #define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT 0x00
861 /* Bit definitions for SMPS8_CTRL */
862 #define PALMAS_SMPS8_CTRL_WR_S 0x80
863 #define PALMAS_SMPS8_CTRL_WR_S_SHIFT 0x07
864 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN 0x40
865 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
866 #define PALMAS_SMPS8_CTRL_STATUS_MASK 0x30
867 #define PALMAS_SMPS8_CTRL_STATUS_SHIFT 0x04
868 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK 0x0c
869 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT 0x02
870 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK 0x03
871 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT 0x00
873 /* Bit definitions for SMPS8_TSTEP */
874 #define PALMAS_SMPS8_TSTEP_TSTEP_MASK 0x03
875 #define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT 0x00
877 /* Bit definitions for SMPS8_FORCE */
878 #define PALMAS_SMPS8_FORCE_CMD 0x80
879 #define PALMAS_SMPS8_FORCE_CMD_SHIFT 0x07
880 #define PALMAS_SMPS8_FORCE_VSEL_MASK 0x7F
881 #define PALMAS_SMPS8_FORCE_VSEL_SHIFT 0x00
883 /* Bit definitions for SMPS8_VOLTAGE */
884 #define PALMAS_SMPS8_VOLTAGE_RANGE 0x80
885 #define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT 0x07
886 #define PALMAS_SMPS8_VOLTAGE_VSEL_MASK 0x7F
887 #define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT 0x00
889 /* Bit definitions for SMPS9_CTRL */
890 #define PALMAS_SMPS9_CTRL_WR_S 0x80
891 #define PALMAS_SMPS9_CTRL_WR_S_SHIFT 0x07
892 #define PALMAS_SMPS9_CTRL_STATUS_MASK 0x30
893 #define PALMAS_SMPS9_CTRL_STATUS_SHIFT 0x04
894 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK 0x0c
895 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT 0x02
896 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK 0x03
897 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT 0x00
899 /* Bit definitions for SMPS9_VOLTAGE */
900 #define PALMAS_SMPS9_VOLTAGE_RANGE 0x80
901 #define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT 0x07
902 #define PALMAS_SMPS9_VOLTAGE_VSEL_MASK 0x7F
903 #define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT 0x00
905 /* Bit definitions for SMPS10_CTRL */
906 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK 0xf0
907 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT 0x04
908 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK 0x0F
909 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT 0x00
911 /* Bit definitions for SMPS10_STATUS */
912 #define PALMAS_SMPS10_STATUS_STATUS_MASK 0x0F
913 #define PALMAS_SMPS10_STATUS_STATUS_SHIFT 0x00
915 /* Bit definitions for SMPS_CTRL */
916 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN 0x20
917 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT 0x05
918 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN 0x10
919 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT 0x04
920 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK 0x0c
921 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT 0x02
922 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK 0x03
923 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT 0x00
925 /* Bit definitions for SMPS_PD_CTRL */
926 #define PALMAS_SMPS_PD_CTRL_SMPS9 0x40
927 #define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT 0x06
928 #define PALMAS_SMPS_PD_CTRL_SMPS8 0x20
929 #define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT 0x05
930 #define PALMAS_SMPS_PD_CTRL_SMPS7 0x10
931 #define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT 0x04
932 #define PALMAS_SMPS_PD_CTRL_SMPS6 0x08
933 #define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT 0x03
934 #define PALMAS_SMPS_PD_CTRL_SMPS45 0x04
935 #define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT 0x02
936 #define PALMAS_SMPS_PD_CTRL_SMPS3 0x02
937 #define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT 0x01
938 #define PALMAS_SMPS_PD_CTRL_SMPS12 0x01
939 #define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT 0x00
941 /* Bit definitions for SMPS_THERMAL_EN */
942 #define PALMAS_SMPS_THERMAL_EN_SMPS9 0x40
943 #define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT 0x06
944 #define PALMAS_SMPS_THERMAL_EN_SMPS8 0x20
945 #define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT 0x05
946 #define PALMAS_SMPS_THERMAL_EN_SMPS6 0x08
947 #define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT 0x03
948 #define PALMAS_SMPS_THERMAL_EN_SMPS457 0x04
949 #define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT 0x02
950 #define PALMAS_SMPS_THERMAL_EN_SMPS123 0x01
951 #define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT 0x00
953 /* Bit definitions for SMPS_THERMAL_STATUS */
954 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9 0x40
955 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT 0x06
956 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8 0x20
957 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT 0x05
958 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6 0x08
959 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT 0x03
960 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457 0x04
961 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT 0x02
962 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123 0x01
963 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT 0x00
965 /* Bit definitions for SMPS_SHORT_STATUS */
966 #define PALMAS_SMPS_SHORT_STATUS_SMPS10 0x80
967 #define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT 0x07
968 #define PALMAS_SMPS_SHORT_STATUS_SMPS9 0x40
969 #define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT 0x06
970 #define PALMAS_SMPS_SHORT_STATUS_SMPS8 0x20
971 #define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT 0x05
972 #define PALMAS_SMPS_SHORT_STATUS_SMPS7 0x10
973 #define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT 0x04
974 #define PALMAS_SMPS_SHORT_STATUS_SMPS6 0x08
975 #define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT 0x03
976 #define PALMAS_SMPS_SHORT_STATUS_SMPS45 0x04
977 #define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT 0x02
978 #define PALMAS_SMPS_SHORT_STATUS_SMPS3 0x02
979 #define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x01
980 #define PALMAS_SMPS_SHORT_STATUS_SMPS12 0x01
981 #define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT 0x00
983 /* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
984 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9 0x40
985 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT 0x06
986 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8 0x20
987 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT 0x05
988 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7 0x10
989 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT 0x04
990 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6 0x08
991 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT 0x03
992 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45 0x04
993 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT 0x02
994 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x02
995 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x01
996 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12 0x01
997 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT 0x00
999 /* Bit definitions for SMPS_POWERGOOD_MASK1 */
1000 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10 0x80
1001 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT 0x07
1002 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9 0x40
1003 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT 0x06
1004 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8 0x20
1005 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT 0x05
1006 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7 0x10
1007 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT 0x04
1008 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6 0x08
1009 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT 0x03
1010 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45 0x04
1011 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT 0x02
1012 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3 0x02
1013 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x01
1014 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12 0x01
1015 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT 0x00
1017 /* Bit definitions for SMPS_POWERGOOD_MASK2 */
1018 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80
1019 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07
1020 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7 0x04
1021 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT 0x02
1022 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS 0x02
1023 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT 0x01
1024 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK 0x01
1025 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT 0x00
1027 /* Registers for function LDO */
1028 #define PALMAS_LDO1_CTRL 0x00
1029 #define PALMAS_LDO1_VOLTAGE 0x01
1030 #define PALMAS_LDO2_CTRL 0x02
1031 #define PALMAS_LDO2_VOLTAGE 0x03
1032 #define PALMAS_LDO3_CTRL 0x04
1033 #define PALMAS_LDO3_VOLTAGE 0x05
1034 #define PALMAS_LDO4_CTRL 0x06
1035 #define PALMAS_LDO4_VOLTAGE 0x07
1036 #define PALMAS_LDO5_CTRL 0x08
1037 #define PALMAS_LDO5_VOLTAGE 0x09
1038 #define PALMAS_LDO6_CTRL 0x0A
1039 #define PALMAS_LDO6_VOLTAGE 0x0B
1040 #define PALMAS_LDO7_CTRL 0x0C
1041 #define PALMAS_LDO7_VOLTAGE 0x0D
1042 #define PALMAS_LDO8_CTRL 0x0E
1043 #define PALMAS_LDO8_VOLTAGE 0x0F
1044 #define PALMAS_LDO9_CTRL 0x10
1045 #define PALMAS_LDO9_VOLTAGE 0x11
1046 #define PALMAS_LDOLN_CTRL 0x12
1047 #define PALMAS_LDOLN_VOLTAGE 0x13
1048 #define PALMAS_LDOUSB_CTRL 0x14
1049 #define PALMAS_LDOUSB_VOLTAGE 0x15
1050 #define PALMAS_LDO_CTRL 0x1A
1051 #define PALMAS_LDO_PD_CTRL1 0x1B
1052 #define PALMAS_LDO_PD_CTRL2 0x1C
1053 #define PALMAS_LDO_SHORT_STATUS1 0x1D
1054 #define PALMAS_LDO_SHORT_STATUS2 0x1E
1056 /* Bit definitions for LDO1_CTRL */
1057 #define PALMAS_LDO1_CTRL_WR_S 0x80
1058 #define PALMAS_LDO1_CTRL_WR_S_SHIFT 0x07
1059 #define PALMAS_LDO1_CTRL_STATUS 0x10
1060 #define PALMAS_LDO1_CTRL_STATUS_SHIFT 0x04
1061 #define PALMAS_LDO1_CTRL_MODE_SLEEP 0x04
1062 #define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02
1063 #define PALMAS_LDO1_CTRL_MODE_ACTIVE 0x01
1064 #define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00
1066 /* Bit definitions for LDO1_VOLTAGE */
1067 #define PALMAS_LDO1_VOLTAGE_VSEL_MASK 0x3F
1068 #define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT 0x00
1070 /* Bit definitions for LDO2_CTRL */
1071 #define PALMAS_LDO2_CTRL_WR_S 0x80
1072 #define PALMAS_LDO2_CTRL_WR_S_SHIFT 0x07
1073 #define PALMAS_LDO2_CTRL_STATUS 0x10
1074 #define PALMAS_LDO2_CTRL_STATUS_SHIFT 0x04
1075 #define PALMAS_LDO2_CTRL_MODE_SLEEP 0x04
1076 #define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02
1077 #define PALMAS_LDO2_CTRL_MODE_ACTIVE 0x01
1078 #define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00
1080 /* Bit definitions for LDO2_VOLTAGE */
1081 #define PALMAS_LDO2_VOLTAGE_VSEL_MASK 0x3F
1082 #define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT 0x00
1084 /* Bit definitions for LDO3_CTRL */
1085 #define PALMAS_LDO3_CTRL_WR_S 0x80
1086 #define PALMAS_LDO3_CTRL_WR_S_SHIFT 0x07
1087 #define PALMAS_LDO3_CTRL_STATUS 0x10
1088 #define PALMAS_LDO3_CTRL_STATUS_SHIFT 0x04
1089 #define PALMAS_LDO3_CTRL_MODE_SLEEP 0x04
1090 #define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02
1091 #define PALMAS_LDO3_CTRL_MODE_ACTIVE 0x01
1092 #define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00
1094 /* Bit definitions for LDO3_VOLTAGE */
1095 #define PALMAS_LDO3_VOLTAGE_VSEL_MASK 0x3F
1096 #define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT 0x00
1098 /* Bit definitions for LDO4_CTRL */
1099 #define PALMAS_LDO4_CTRL_WR_S 0x80
1100 #define PALMAS_LDO4_CTRL_WR_S_SHIFT 0x07
1101 #define PALMAS_LDO4_CTRL_STATUS 0x10
1102 #define PALMAS_LDO4_CTRL_STATUS_SHIFT 0x04
1103 #define PALMAS_LDO4_CTRL_MODE_SLEEP 0x04
1104 #define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02
1105 #define PALMAS_LDO4_CTRL_MODE_ACTIVE 0x01
1106 #define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00
1108 /* Bit definitions for LDO4_VOLTAGE */
1109 #define PALMAS_LDO4_VOLTAGE_VSEL_MASK 0x3F
1110 #define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT 0x00
1112 /* Bit definitions for LDO5_CTRL */
1113 #define PALMAS_LDO5_CTRL_WR_S 0x80
1114 #define PALMAS_LDO5_CTRL_WR_S_SHIFT 0x07
1115 #define PALMAS_LDO5_CTRL_STATUS 0x10
1116 #define PALMAS_LDO5_CTRL_STATUS_SHIFT 0x04
1117 #define PALMAS_LDO5_CTRL_MODE_SLEEP 0x04
1118 #define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02
1119 #define PALMAS_LDO5_CTRL_MODE_ACTIVE 0x01
1120 #define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00
1122 /* Bit definitions for LDO5_VOLTAGE */
1123 #define PALMAS_LDO5_VOLTAGE_VSEL_MASK 0x3F
1124 #define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT 0x00
1126 /* Bit definitions for LDO6_CTRL */
1127 #define PALMAS_LDO6_CTRL_WR_S 0x80
1128 #define PALMAS_LDO6_CTRL_WR_S_SHIFT 0x07
1129 #define PALMAS_LDO6_CTRL_LDO_VIB_EN 0x40
1130 #define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT 0x06
1131 #define PALMAS_LDO6_CTRL_STATUS 0x10
1132 #define PALMAS_LDO6_CTRL_STATUS_SHIFT 0x04
1133 #define PALMAS_LDO6_CTRL_MODE_SLEEP 0x04
1134 #define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT 0x02
1135 #define PALMAS_LDO6_CTRL_MODE_ACTIVE 0x01
1136 #define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT 0x00
1138 /* Bit definitions for LDO6_VOLTAGE */
1139 #define PALMAS_LDO6_VOLTAGE_VSEL_MASK 0x3F
1140 #define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT 0x00
1142 /* Bit definitions for LDO7_CTRL */
1143 #define PALMAS_LDO7_CTRL_WR_S 0x80
1144 #define PALMAS_LDO7_CTRL_WR_S_SHIFT 0x07
1145 #define PALMAS_LDO7_CTRL_STATUS 0x10
1146 #define PALMAS_LDO7_CTRL_STATUS_SHIFT 0x04
1147 #define PALMAS_LDO7_CTRL_MODE_SLEEP 0x04
1148 #define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT 0x02
1149 #define PALMAS_LDO7_CTRL_MODE_ACTIVE 0x01
1150 #define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT 0x00
1152 /* Bit definitions for LDO7_VOLTAGE */
1153 #define PALMAS_LDO7_VOLTAGE_VSEL_MASK 0x3F
1154 #define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT 0x00
1156 /* Bit definitions for LDO8_CTRL */
1157 #define PALMAS_LDO8_CTRL_WR_S 0x80
1158 #define PALMAS_LDO8_CTRL_WR_S_SHIFT 0x07
1159 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN 0x40
1160 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT 0x06
1161 #define PALMAS_LDO8_CTRL_STATUS 0x10
1162 #define PALMAS_LDO8_CTRL_STATUS_SHIFT 0x04
1163 #define PALMAS_LDO8_CTRL_MODE_SLEEP 0x04
1164 #define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT 0x02
1165 #define PALMAS_LDO8_CTRL_MODE_ACTIVE 0x01
1166 #define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT 0x00
1168 /* Bit definitions for LDO8_VOLTAGE */
1169 #define PALMAS_LDO8_VOLTAGE_VSEL_MASK 0x3F
1170 #define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT 0x00
1172 /* Bit definitions for LDO9_CTRL */
1173 #define PALMAS_LDO9_CTRL_WR_S 0x80
1174 #define PALMAS_LDO9_CTRL_WR_S_SHIFT 0x07
1175 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN 0x40
1176 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT 0x06
1177 #define PALMAS_LDO9_CTRL_STATUS 0x10
1178 #define PALMAS_LDO9_CTRL_STATUS_SHIFT 0x04
1179 #define PALMAS_LDO9_CTRL_MODE_SLEEP 0x04
1180 #define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT 0x02
1181 #define PALMAS_LDO9_CTRL_MODE_ACTIVE 0x01
1182 #define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT 0x00
1184 /* Bit definitions for LDO9_VOLTAGE */
1185 #define PALMAS_LDO9_VOLTAGE_VSEL_MASK 0x3F
1186 #define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT 0x00
1188 /* Bit definitions for LDOLN_CTRL */
1189 #define PALMAS_LDOLN_CTRL_WR_S 0x80
1190 #define PALMAS_LDOLN_CTRL_WR_S_SHIFT 0x07
1191 #define PALMAS_LDOLN_CTRL_STATUS 0x10
1192 #define PALMAS_LDOLN_CTRL_STATUS_SHIFT 0x04
1193 #define PALMAS_LDOLN_CTRL_MODE_SLEEP 0x04
1194 #define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT 0x02
1195 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE 0x01
1196 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT 0x00
1198 /* Bit definitions for LDOLN_VOLTAGE */
1199 #define PALMAS_LDOLN_VOLTAGE_VSEL_MASK 0x3F
1200 #define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT 0x00
1202 /* Bit definitions for LDOUSB_CTRL */
1203 #define PALMAS_LDOUSB_CTRL_WR_S 0x80
1204 #define PALMAS_LDOUSB_CTRL_WR_S_SHIFT 0x07
1205 #define PALMAS_LDOUSB_CTRL_STATUS 0x10
1206 #define PALMAS_LDOUSB_CTRL_STATUS_SHIFT 0x04
1207 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP 0x04
1208 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT 0x02
1209 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE 0x01
1210 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT 0x00
1212 /* Bit definitions for LDOUSB_VOLTAGE */
1213 #define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK 0x3F
1214 #define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT 0x00
1216 /* Bit definitions for LDO_CTRL */
1217 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS 0x01
1218 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT 0x00
1220 /* Bit definitions for LDO_PD_CTRL1 */
1221 #define PALMAS_LDO_PD_CTRL1_LDO8 0x80
1222 #define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT 0x07
1223 #define PALMAS_LDO_PD_CTRL1_LDO7 0x40
1224 #define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT 0x06
1225 #define PALMAS_LDO_PD_CTRL1_LDO6 0x20
1226 #define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT 0x05
1227 #define PALMAS_LDO_PD_CTRL1_LDO5 0x10
1228 #define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT 0x04
1229 #define PALMAS_LDO_PD_CTRL1_LDO4 0x08
1230 #define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT 0x03
1231 #define PALMAS_LDO_PD_CTRL1_LDO3 0x04
1232 #define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT 0x02
1233 #define PALMAS_LDO_PD_CTRL1_LDO2 0x02
1234 #define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT 0x01
1235 #define PALMAS_LDO_PD_CTRL1_LDO1 0x01
1236 #define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT 0x00
1238 /* Bit definitions for LDO_PD_CTRL2 */
1239 #define PALMAS_LDO_PD_CTRL2_LDOUSB 0x04
1240 #define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT 0x02
1241 #define PALMAS_LDO_PD_CTRL2_LDOLN 0x02
1242 #define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT 0x01
1243 #define PALMAS_LDO_PD_CTRL2_LDO9 0x01
1244 #define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT 0x00
1246 /* Bit definitions for LDO_SHORT_STATUS1 */
1247 #define PALMAS_LDO_SHORT_STATUS1_LDO8 0x80
1248 #define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT 0x07
1249 #define PALMAS_LDO_SHORT_STATUS1_LDO7 0x40
1250 #define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT 0x06
1251 #define PALMAS_LDO_SHORT_STATUS1_LDO6 0x20
1252 #define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT 0x05
1253 #define PALMAS_LDO_SHORT_STATUS1_LDO5 0x10
1254 #define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT 0x04
1255 #define PALMAS_LDO_SHORT_STATUS1_LDO4 0x08
1256 #define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT 0x03
1257 #define PALMAS_LDO_SHORT_STATUS1_LDO3 0x04
1258 #define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT 0x02
1259 #define PALMAS_LDO_SHORT_STATUS1_LDO2 0x02
1260 #define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01
1261 #define PALMAS_LDO_SHORT_STATUS1_LDO1 0x01
1262 #define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00
1264 /* Bit definitions for LDO_SHORT_STATUS2 */
1265 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA 0x08
1266 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x03
1267 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB 0x04
1268 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT 0x02
1269 #define PALMAS_LDO_SHORT_STATUS2_LDOLN 0x02
1270 #define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT 0x01
1271 #define PALMAS_LDO_SHORT_STATUS2_LDO9 0x01
1272 #define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT 0x00
1274 /* Registers for function PMU_CONTROL */
1275 #define PALMAS_DEV_CTRL 0x00
1276 #define PALMAS_POWER_CTRL 0x01
1277 #define PALMAS_VSYS_LO 0x02
1278 #define PALMAS_VSYS_MON 0x03
1279 #define PALMAS_VBAT_MON 0x04
1280 #define PALMAS_WATCHDOG 0x05
1281 #define PALMAS_BOOT_STATUS 0x06
1282 #define PALMAS_BATTERY_BOUNCE 0x07
1283 #define PALMAS_BACKUP_BATTERY_CTRL 0x08
1284 #define PALMAS_LONG_PRESS_KEY 0x09
1285 #define PALMAS_OSC_THERM_CTRL 0x0A
1286 #define PALMAS_BATDEBOUNCING 0x0B
1287 #define PALMAS_SWOFF_HWRST 0x0F
1288 #define PALMAS_SWOFF_COLDRST 0x10
1289 #define PALMAS_SWOFF_STATUS 0x11
1290 #define PALMAS_PMU_CONFIG 0x12
1291 #define PALMAS_SPARE 0x14
1292 #define PALMAS_PMU_SECONDARY_INT 0x15
1293 #define PALMAS_SW_REVISION 0x17
1294 #define PALMAS_EXT_CHRG_CTRL 0x18
1295 #define PALMAS_PMU_SECONDARY_INT2 0x19
1297 /* Bit definitions for DEV_CTRL */
1298 #define PALMAS_DEV_CTRL_DEV_STATUS_MASK 0x0c
1299 #define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT 0x02
1300 #define PALMAS_DEV_CTRL_SW_RST 0x02
1301 #define PALMAS_DEV_CTRL_SW_RST_SHIFT 0x01
1302 #define PALMAS_DEV_CTRL_DEV_ON 0x01
1303 #define PALMAS_DEV_CTRL_DEV_ON_SHIFT 0x00
1305 /* Bit definitions for POWER_CTRL */
1306 #define PALMAS_POWER_CTRL_ENABLE2_MASK 0x04
1307 #define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT 0x02
1308 #define PALMAS_POWER_CTRL_ENABLE1_MASK 0x02
1309 #define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT 0x01
1310 #define PALMAS_POWER_CTRL_NSLEEP_MASK 0x01
1311 #define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT 0x00
1313 /* Bit definitions for VSYS_LO */
1314 #define PALMAS_VSYS_LO_THRESHOLD_MASK 0x1F
1315 #define PALMAS_VSYS_LO_THRESHOLD_SHIFT 0x00
1317 /* Bit definitions for VSYS_MON */
1318 #define PALMAS_VSYS_MON_ENABLE 0x80
1319 #define PALMAS_VSYS_MON_ENABLE_SHIFT 0x07
1320 #define PALMAS_VSYS_MON_THRESHOLD_MASK 0x3F
1321 #define PALMAS_VSYS_MON_THRESHOLD_SHIFT 0x00
1323 /* Bit definitions for VBAT_MON */
1324 #define PALMAS_VBAT_MON_ENABLE 0x80
1325 #define PALMAS_VBAT_MON_ENABLE_SHIFT 0x07
1326 #define PALMAS_VBAT_MON_THRESHOLD_MASK 0x3F
1327 #define PALMAS_VBAT_MON_THRESHOLD_SHIFT 0x00
1329 /* Bit definitions for WATCHDOG */
1330 #define PALMAS_WATCHDOG_LOCK 0x20
1331 #define PALMAS_WATCHDOG_LOCK_SHIFT 0x05
1332 #define PALMAS_WATCHDOG_ENABLE 0x10
1333 #define PALMAS_WATCHDOG_ENABLE_SHIFT 0x04
1334 #define PALMAS_WATCHDOG_MODE 0x08
1335 #define PALMAS_WATCHDOG_MODE_SHIFT 0x03
1336 #define PALMAS_WATCHDOG_TIMER_MASK 0x07
1337 #define PALMAS_WATCHDOG_TIMER_SHIFT 0x00
1339 /* Bit definitions for BOOT_STATUS */
1340 #define PALMAS_BOOT_STATUS_BOOT1 0x02
1341 #define PALMAS_BOOT_STATUS_BOOT1_SHIFT 0x01
1342 #define PALMAS_BOOT_STATUS_BOOT0 0x01
1343 #define PALMAS_BOOT_STATUS_BOOT0_SHIFT 0x00
1345 /* Bit definitions for BATTERY_BOUNCE */
1346 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK 0x3F
1347 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT 0x00
1349 /* Bit definitions for BACKUP_BATTERY_CTRL */
1350 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15 0x80
1351 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT 0x07
1352 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP 0x40
1353 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT 0x06
1354 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF 0x20
1355 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT 0x05
1356 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN 0x10
1357 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT 0x04
1358 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG 0x08
1359 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT 0x03
1360 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK 0x06
1361 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT 0x01
1362 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN 0x01
1363 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT 0x00
1365 /* Bit definitions for LONG_PRESS_KEY */
1366 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK 0x80
1367 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT 0x07
1368 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR 0x10
1369 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT 0x04
1370 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK 0x0c
1371 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT 0x02
1372 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK 0x03
1373 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT 0x00
1375 /* Bit definitions for OSC_THERM_CTRL */
1376 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP 0x80
1377 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT 0x07
1378 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP 0x40
1379 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT 0x06
1380 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP 0x20
1381 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT 0x05
1382 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP 0x10
1383 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT 0x04
1384 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK 0x0c
1385 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT 0x02
1386 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS 0x02
1387 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT 0x01
1388 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE 0x01
1389 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT 0x00
1391 /* Bit definitions for BATDEBOUNCING */
1392 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS 0x80
1393 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT 0x07
1394 #define PALMAS_BATDEBOUNCING_BINS_DEB_MASK 0x78
1395 #define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT 0x03
1396 #define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK 0x07
1397 #define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT 0x00
1399 /* Bit definitions for SWOFF_HWRST */
1400 #define PALMAS_SWOFF_HWRST_PWRON_LPK 0x80
1401 #define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT 0x07
1402 #define PALMAS_SWOFF_HWRST_PWRDOWN 0x40
1403 #define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT 0x06
1404 #define PALMAS_SWOFF_HWRST_WTD 0x20
1405 #define PALMAS_SWOFF_HWRST_WTD_SHIFT 0x05
1406 #define PALMAS_SWOFF_HWRST_TSHUT 0x10
1407 #define PALMAS_SWOFF_HWRST_TSHUT_SHIFT 0x04
1408 #define PALMAS_SWOFF_HWRST_RESET_IN 0x08
1409 #define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT 0x03
1410 #define PALMAS_SWOFF_HWRST_SW_RST 0x04
1411 #define PALMAS_SWOFF_HWRST_SW_RST_SHIFT 0x02
1412 #define PALMAS_SWOFF_HWRST_VSYS_LO 0x02
1413 #define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT 0x01
1414 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN 0x01
1415 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT 0x00
1417 /* Bit definitions for SWOFF_COLDRST */
1418 #define PALMAS_SWOFF_COLDRST_PWRON_LPK 0x80
1419 #define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT 0x07
1420 #define PALMAS_SWOFF_COLDRST_PWRDOWN 0x40
1421 #define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT 0x06
1422 #define PALMAS_SWOFF_COLDRST_WTD 0x20
1423 #define PALMAS_SWOFF_COLDRST_WTD_SHIFT 0x05
1424 #define PALMAS_SWOFF_COLDRST_TSHUT 0x10
1425 #define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT 0x04
1426 #define PALMAS_SWOFF_COLDRST_RESET_IN 0x08
1427 #define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT 0x03
1428 #define PALMAS_SWOFF_COLDRST_SW_RST 0x04
1429 #define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT 0x02
1430 #define PALMAS_SWOFF_COLDRST_VSYS_LO 0x02
1431 #define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT 0x01
1432 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN 0x01
1433 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT 0x00
1435 /* Bit definitions for SWOFF_STATUS */
1436 #define PALMAS_SWOFF_STATUS_PWRON_LPK 0x80
1437 #define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT 0x07
1438 #define PALMAS_SWOFF_STATUS_PWRDOWN 0x40
1439 #define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT 0x06
1440 #define PALMAS_SWOFF_STATUS_WTD 0x20
1441 #define PALMAS_SWOFF_STATUS_WTD_SHIFT 0x05
1442 #define PALMAS_SWOFF_STATUS_TSHUT 0x10
1443 #define PALMAS_SWOFF_STATUS_TSHUT_SHIFT 0x04
1444 #define PALMAS_SWOFF_STATUS_RESET_IN 0x08
1445 #define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT 0x03
1446 #define PALMAS_SWOFF_STATUS_SW_RST 0x04
1447 #define PALMAS_SWOFF_STATUS_SW_RST_SHIFT 0x02
1448 #define PALMAS_SWOFF_STATUS_VSYS_LO 0x02
1449 #define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT 0x01
1450 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN 0x01
1451 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT 0x00
1453 /* Bit definitions for PMU_CONFIG */
1454 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN 0x40
1455 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT 0x06
1456 #define PALMAS_PMU_CONFIG_SPARE_MASK 0x30
1457 #define PALMAS_PMU_CONFIG_SPARE_SHIFT 0x04
1458 #define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK 0x0c
1459 #define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT 0x02
1460 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT 0x02
1461 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT 0x01
1462 #define PALMAS_PMU_CONFIG_AUTODEVON 0x01
1463 #define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT 0x00
1465 /* Bit definitions for SPARE */
1466 #define PALMAS_SPARE_SPARE_MASK 0xf8
1467 #define PALMAS_SPARE_SPARE_SHIFT 0x03
1468 #define PALMAS_SPARE_REGEN3_OD 0x04
1469 #define PALMAS_SPARE_REGEN3_OD_SHIFT 0x02
1470 #define PALMAS_SPARE_REGEN2_OD 0x02
1471 #define PALMAS_SPARE_REGEN2_OD_SHIFT 0x01
1472 #define PALMAS_SPARE_REGEN1_OD 0x01
1473 #define PALMAS_SPARE_REGEN1_OD_SHIFT 0x00
1475 /* Bit definitions for PMU_SECONDARY_INT */
1476 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC 0x80
1477 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT 0x07
1478 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC 0x40
1479 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT 0x06
1480 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC 0x20
1481 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT 0x05
1482 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC 0x10
1483 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT 0x04
1484 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK 0x08
1485 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT 0x03
1486 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK 0x04
1487 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT 0x02
1488 #define PALMAS_PMU_SECONDARY_INT_BB_MASK 0x02
1489 #define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT 0x01
1490 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK 0x01
1491 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT 0x00
1493 /* Bit definitions for SW_REVISION */
1494 #define PALMAS_SW_REVISION_SW_REVISION_MASK 0xFF
1495 #define PALMAS_SW_REVISION_SW_REVISION_SHIFT 0x00
1497 /* Bit definitions for EXT_CHRG_CTRL */
1498 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS 0x80
1499 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT 0x07
1500 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS 0x40
1501 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT 0x06
1502 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY 0x08
1503 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT 0x03
1504 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N 0x04
1505 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT 0x02
1506 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN 0x02
1507 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT 0x01
1508 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN 0x01
1509 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT 0x00
1511 /* Bit definitions for PMU_SECONDARY_INT2 */
1512 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC 0x20
1513 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT 0x05
1514 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC 0x10
1515 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT 0x04
1516 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK 0x02
1517 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT 0x01
1518 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK 0x01
1519 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT 0x00
1521 /* Registers for function RESOURCE */
1522 #define PALMAS_CLK32KG_CTRL 0x00
1523 #define PALMAS_CLK32KGAUDIO_CTRL 0x01
1524 #define PALMAS_REGEN1_CTRL 0x02
1525 #define PALMAS_REGEN2_CTRL 0x03
1526 #define PALMAS_SYSEN1_CTRL 0x04
1527 #define PALMAS_SYSEN2_CTRL 0x05
1528 #define PALMAS_NSLEEP_RES_ASSIGN 0x06
1529 #define PALMAS_NSLEEP_SMPS_ASSIGN 0x07
1530 #define PALMAS_NSLEEP_LDO_ASSIGN1 0x08
1531 #define PALMAS_NSLEEP_LDO_ASSIGN2 0x09
1532 #define PALMAS_ENABLE1_RES_ASSIGN 0x0A
1533 #define PALMAS_ENABLE1_SMPS_ASSIGN 0x0B
1534 #define PALMAS_ENABLE1_LDO_ASSIGN1 0x0C
1535 #define PALMAS_ENABLE1_LDO_ASSIGN2 0x0D
1536 #define PALMAS_ENABLE2_RES_ASSIGN 0x0E
1537 #define PALMAS_ENABLE2_SMPS_ASSIGN 0x0F
1538 #define PALMAS_ENABLE2_LDO_ASSIGN1 0x10
1539 #define PALMAS_ENABLE2_LDO_ASSIGN2 0x11
1540 #define PALMAS_REGEN3_CTRL 0x12
1542 /* Bit definitions for CLK32KG_CTRL */
1543 #define PALMAS_CLK32KG_CTRL_STATUS 0x10
1544 #define PALMAS_CLK32KG_CTRL_STATUS_SHIFT 0x04
1545 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP 0x04
1546 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT 0x02
1547 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE 0x01
1548 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT 0x00
1550 /* Bit definitions for CLK32KGAUDIO_CTRL */
1551 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS 0x10
1552 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT 0x04
1553 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3 0x08
1554 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT 0x03
1555 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP 0x04
1556 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT 0x02
1557 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE 0x01
1558 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT 0x00
1560 /* Bit definitions for REGEN1_CTRL */
1561 #define PALMAS_REGEN1_CTRL_STATUS 0x10
1562 #define PALMAS_REGEN1_CTRL_STATUS_SHIFT 0x04
1563 #define PALMAS_REGEN1_CTRL_MODE_SLEEP 0x04
1564 #define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02
1565 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE 0x01
1566 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
1568 /* Bit definitions for REGEN2_CTRL */
1569 #define PALMAS_REGEN2_CTRL_STATUS 0x10
1570 #define PALMAS_REGEN2_CTRL_STATUS_SHIFT 0x04
1571 #define PALMAS_REGEN2_CTRL_MODE_SLEEP 0x04
1572 #define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02
1573 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE 0x01
1574 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
1576 /* Bit definitions for SYSEN1_CTRL */
1577 #define PALMAS_SYSEN1_CTRL_STATUS 0x10
1578 #define PALMAS_SYSEN1_CTRL_STATUS_SHIFT 0x04
1579 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP 0x04
1580 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT 0x02
1581 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE 0x01
1582 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
1584 /* Bit definitions for SYSEN2_CTRL */
1585 #define PALMAS_SYSEN2_CTRL_STATUS 0x10
1586 #define PALMAS_SYSEN2_CTRL_STATUS_SHIFT 0x04
1587 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP 0x04
1588 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT 0x02
1589 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE 0x01
1590 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
1592 /* Bit definitions for NSLEEP_RES_ASSIGN */
1593 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3 0x40
1594 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x06
1595 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO 0x20
1596 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
1597 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG 0x10
1598 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT 0x04
1599 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2 0x08
1600 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT 0x03
1601 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1 0x04
1602 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT 0x02
1603 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2 0x02
1604 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01
1605 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1 0x01
1606 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00
1608 /* Bit definitions for NSLEEP_SMPS_ASSIGN */
1609 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10 0x80
1610 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT 0x07
1611 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9 0x40
1612 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT 0x06
1613 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8 0x20
1614 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT 0x05
1615 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7 0x10
1616 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT 0x04
1617 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6 0x08
1618 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT 0x03
1619 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45 0x04
1620 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT 0x02
1621 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3 0x02
1622 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x01
1623 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12 0x01
1624 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT 0x00
1626 /* Bit definitions for NSLEEP_LDO_ASSIGN1 */
1627 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8 0x80
1628 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT 0x07
1629 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7 0x40
1630 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT 0x06
1631 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6 0x20
1632 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT 0x05
1633 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5 0x10
1634 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT 0x04
1635 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4 0x08
1636 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x03
1637 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3 0x04
1638 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT 0x02
1639 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2 0x02
1640 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01
1641 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1 0x01
1642 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00
1644 /* Bit definitions for NSLEEP_LDO_ASSIGN2 */
1645 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB 0x04
1646 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
1647 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN 0x02
1648 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT 0x01
1649 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9 0x01
1650 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT 0x00
1652 /* Bit definitions for ENABLE1_RES_ASSIGN */
1653 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3 0x40
1654 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x06
1655 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO 0x20
1656 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
1657 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG 0x10
1658 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT 0x04
1659 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2 0x08
1660 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT 0x03
1661 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1 0x04
1662 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT 0x02
1663 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2 0x02
1664 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01
1665 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1 0x01
1666 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00
1668 /* Bit definitions for ENABLE1_SMPS_ASSIGN */
1669 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10 0x80
1670 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT 0x07
1671 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9 0x40
1672 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT 0x06
1673 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8 0x20
1674 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT 0x05
1675 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7 0x10
1676 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT 0x04
1677 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6 0x08
1678 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT 0x03
1679 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45 0x04
1680 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT 0x02
1681 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3 0x02
1682 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x01
1683 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12 0x01
1684 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT 0x00
1686 /* Bit definitions for ENABLE1_LDO_ASSIGN1 */
1687 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8 0x80
1688 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT 0x07
1689 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7 0x40
1690 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT 0x06
1691 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6 0x20
1692 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT 0x05
1693 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5 0x10
1694 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT 0x04
1695 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4 0x08
1696 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x03
1697 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3 0x04
1698 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT 0x02
1699 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2 0x02
1700 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01
1701 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1 0x01
1702 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00
1704 /* Bit definitions for ENABLE1_LDO_ASSIGN2 */
1705 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB 0x04
1706 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
1707 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN 0x02
1708 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT 0x01
1709 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9 0x01
1710 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT 0x00
1712 /* Bit definitions for ENABLE2_RES_ASSIGN */
1713 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3 0x40
1714 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x06
1715 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO 0x20
1716 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
1717 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG 0x10
1718 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT 0x04
1719 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2 0x08
1720 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT 0x03
1721 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1 0x04
1722 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT 0x02
1723 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2 0x02
1724 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01
1725 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1 0x01
1726 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00
1728 /* Bit definitions for ENABLE2_SMPS_ASSIGN */
1729 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10 0x80
1730 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT 0x07
1731 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9 0x40
1732 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT 0x06
1733 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8 0x20
1734 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT 0x05
1735 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7 0x10
1736 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT 0x04
1737 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6 0x08
1738 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT 0x03
1739 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45 0x04
1740 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT 0x02
1741 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3 0x02
1742 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x01
1743 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12 0x01
1744 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT 0x00
1746 /* Bit definitions for ENABLE2_LDO_ASSIGN1 */
1747 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8 0x80
1748 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT 0x07
1749 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7 0x40
1750 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT 0x06
1751 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6 0x20
1752 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT 0x05
1753 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5 0x10
1754 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT 0x04
1755 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4 0x08
1756 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x03
1757 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3 0x04
1758 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT 0x02
1759 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2 0x02
1760 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01
1761 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1 0x01
1762 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00
1764 /* Bit definitions for ENABLE2_LDO_ASSIGN2 */
1765 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB 0x04
1766 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
1767 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN 0x02
1768 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT 0x01
1769 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9 0x01
1770 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT 0x00
1772 /* Bit definitions for REGEN3_CTRL */
1773 #define PALMAS_REGEN3_CTRL_STATUS 0x10
1774 #define PALMAS_REGEN3_CTRL_STATUS_SHIFT 0x04
1775 #define PALMAS_REGEN3_CTRL_MODE_SLEEP 0x04
1776 #define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02
1777 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE 0x01
1778 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00
1780 /* Registers for function PAD_CONTROL */
1781 #define PALMAS_OD_OUTPUT_CTRL2 0x02
1782 #define PALMAS_POLARITY_CTRL2 0x03
1783 #define PALMAS_PU_PD_INPUT_CTRL1 0x04
1784 #define PALMAS_PU_PD_INPUT_CTRL2 0x05
1785 #define PALMAS_PU_PD_INPUT_CTRL3 0x06
1786 #define PALMAS_PU_PD_INPUT_CTRL5 0x07
1787 #define PALMAS_OD_OUTPUT_CTRL 0x08
1788 #define PALMAS_POLARITY_CTRL 0x09
1789 #define PALMAS_PRIMARY_SECONDARY_PAD1 0x0A
1790 #define PALMAS_PRIMARY_SECONDARY_PAD2 0x0B
1791 #define PALMAS_I2C_SPI 0x0C
1792 #define PALMAS_PU_PD_INPUT_CTRL4 0x0D
1793 #define PALMAS_PRIMARY_SECONDARY_PAD3 0x0E
1794 #define PALMAS_PRIMARY_SECONDARY_PAD4 0x0F
1796 /* Bit definitions for PU_PD_INPUT_CTRL1 */
1797 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40
1798 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT 0x06
1799 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU 0x20
1800 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT 0x05
1801 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD 0x10
1802 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT 0x04
1803 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD 0x04
1804 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT 0x02
1805 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU 0x02
1806 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT 0x01
1808 /* Bit definitions for PU_PD_INPUT_CTRL2 */
1809 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU 0x20
1810 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT 0x05
1811 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD 0x10
1812 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT 0x04
1813 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU 0x08
1814 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT 0x03
1815 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD 0x04
1816 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT 0x02
1817 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU 0x02
1818 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT 0x01
1819 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD 0x01
1820 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT 0x00
1822 /* Bit definitions for PU_PD_INPUT_CTRL3 */
1823 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD 0x40
1824 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT 0x06
1825 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD 0x10
1826 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT 0x04
1827 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD 0x04
1828 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT 0x02
1829 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD 0x01
1830 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT 0x00
1832 /* Bit definitions for OD_OUTPUT_CTRL */
1833 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD 0x80
1834 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT 0x07
1835 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD 0x40
1836 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT 0x06
1837 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD 0x20
1838 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT 0x05
1839 #define PALMAS_OD_OUTPUT_CTRL_INT_OD 0x08
1840 #define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT 0x03
1842 /* Bit definitions for POLARITY_CTRL */
1843 #define PALMAS_POLARITY_CTRL_INT_POLARITY 0x80
1844 #define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT 0x07
1845 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY 0x40
1846 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT 0x06
1847 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY 0x20
1848 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT 0x05
1849 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY 0x10
1850 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT 0x04
1851 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY 0x08
1852 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT 0x03
1853 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY 0x04
1854 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT 0x02
1855 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY 0x02
1856 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT 0x01
1857 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY 0x01
1858 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT 0x00
1860 /* Bit definitions for PRIMARY_SECONDARY_PAD1 */
1861 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3 0x80
1862 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT 0x07
1863 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK 0x60
1864 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT 0x05
1865 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK 0x18
1866 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT 0x03
1867 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0 0x04
1868 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT 0x02
1869 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC 0x02
1870 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT 0x01
1871 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD 0x01
1872 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT 0x00
1874 /* Bit definitions for PRIMARY_SECONDARY_PAD2 */
1875 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK 0x30
1876 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT 0x04
1877 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6 0x08
1878 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT 0x03
1879 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0x06
1880 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT 0x01
1881 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4 0x01
1882 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT 0x00
1884 /* Bit definitions for I2C_SPI */
1885 #define PALMAS_I2C_SPI_I2C2OTP_EN 0x80
1886 #define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT 0x07
1887 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL 0x40
1888 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT 0x06
1889 #define PALMAS_I2C_SPI_ID_I2C2 0x20
1890 #define PALMAS_I2C_SPI_ID_I2C2_SHIFT 0x05
1891 #define PALMAS_I2C_SPI_I2C_SPI 0x10
1892 #define PALMAS_I2C_SPI_I2C_SPI_SHIFT 0x04
1893 #define PALMAS_I2C_SPI_ID_I2C1_MASK 0x0F
1894 #define PALMAS_I2C_SPI_ID_I2C1_SHIFT 0x00
1896 /* Bit definitions for PU_PD_INPUT_CTRL4 */
1897 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD 0x40
1898 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT 0x06
1899 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD 0x10
1900 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT 0x04
1901 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD 0x04
1902 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT 0x02
1903 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD 0x01
1904 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT 0x00
1906 /* Bit definitions for PRIMARY_SECONDARY_PAD3 */
1907 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 0x02
1908 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT 0x01
1909 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 0x01
1910 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT 0x00
1912 /* Registers for function LED_PWM */
1913 #define PALMAS_LED_PERIOD_CTRL 0x00
1914 #define PALMAS_LED_CTRL 0x01
1915 #define PALMAS_PWM_CTRL1 0x02
1916 #define PALMAS_PWM_CTRL2 0x03
1918 /* Bit definitions for LED_PERIOD_CTRL */
1919 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK 0x38
1920 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT 0x03
1921 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK 0x07
1922 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT 0x00
1924 /* Bit definitions for LED_CTRL */
1925 #define PALMAS_LED_CTRL_LED_2_SEQ 0x20
1926 #define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT 0x05
1927 #define PALMAS_LED_CTRL_LED_1_SEQ 0x10
1928 #define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT 0x04
1929 #define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK 0x0c
1930 #define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT 0x02
1931 #define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK 0x03
1932 #define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT 0x00
1934 /* Bit definitions for PWM_CTRL1 */
1935 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN 0x02
1936 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT 0x01
1937 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL 0x01
1938 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT 0x00
1940 /* Bit definitions for PWM_CTRL2 */
1941 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK 0xFF
1942 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT 0x00
1944 /* Registers for function INTERRUPT */
1945 #define PALMAS_INT1_STATUS 0x00
1946 #define PALMAS_INT1_MASK 0x01
1947 #define PALMAS_INT1_LINE_STATE 0x02
1948 #define PALMAS_INT1_EDGE_DETECT1_RESERVED 0x03
1949 #define PALMAS_INT1_EDGE_DETECT2_RESERVED 0x04
1950 #define PALMAS_INT2_STATUS 0x05
1951 #define PALMAS_INT2_MASK 0x06
1952 #define PALMAS_INT2_LINE_STATE 0x07
1953 #define PALMAS_INT2_EDGE_DETECT1_RESERVED 0x08
1954 #define PALMAS_INT2_EDGE_DETECT2_RESERVED 0x09
1955 #define PALMAS_INT3_STATUS 0x0A
1956 #define PALMAS_INT3_MASK 0x0B
1957 #define PALMAS_INT3_LINE_STATE 0x0C
1958 #define PALMAS_INT3_EDGE_DETECT1_RESERVED 0x0D
1959 #define PALMAS_INT3_EDGE_DETECT2_RESERVED 0x0E
1960 #define PALMAS_INT4_STATUS 0x0F
1961 #define PALMAS_INT4_MASK 0x10
1962 #define PALMAS_INT4_LINE_STATE 0x11
1963 #define PALMAS_INT4_EDGE_DETECT1 0x12
1964 #define PALMAS_INT4_EDGE_DETECT2 0x13
1965 #define PALMAS_INT_CTRL 0x14
1967 /* Bit definitions for INT1_STATUS */
1968 #define PALMAS_INT1_STATUS_VBAT_MON 0x80
1969 #define PALMAS_INT1_STATUS_VBAT_MON_SHIFT 0x07
1970 #define PALMAS_INT1_STATUS_VSYS_MON 0x40
1971 #define PALMAS_INT1_STATUS_VSYS_MON_SHIFT 0x06
1972 #define PALMAS_INT1_STATUS_HOTDIE 0x20
1973 #define PALMAS_INT1_STATUS_HOTDIE_SHIFT 0x05
1974 #define PALMAS_INT1_STATUS_PWRDOWN 0x10
1975 #define PALMAS_INT1_STATUS_PWRDOWN_SHIFT 0x04
1976 #define PALMAS_INT1_STATUS_RPWRON 0x08
1977 #define PALMAS_INT1_STATUS_RPWRON_SHIFT 0x03
1978 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY 0x04
1979 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02
1980 #define PALMAS_INT1_STATUS_PWRON 0x02
1981 #define PALMAS_INT1_STATUS_PWRON_SHIFT 0x01
1982 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV 0x01
1983 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
1985 /* Bit definitions for INT1_MASK */
1986 #define PALMAS_INT1_MASK_VBAT_MON 0x80
1987 #define PALMAS_INT1_MASK_VBAT_MON_SHIFT 0x07
1988 #define PALMAS_INT1_MASK_VSYS_MON 0x40
1989 #define PALMAS_INT1_MASK_VSYS_MON_SHIFT 0x06
1990 #define PALMAS_INT1_MASK_HOTDIE 0x20
1991 #define PALMAS_INT1_MASK_HOTDIE_SHIFT 0x05
1992 #define PALMAS_INT1_MASK_PWRDOWN 0x10
1993 #define PALMAS_INT1_MASK_PWRDOWN_SHIFT 0x04
1994 #define PALMAS_INT1_MASK_RPWRON 0x08
1995 #define PALMAS_INT1_MASK_RPWRON_SHIFT 0x03
1996 #define PALMAS_INT1_MASK_LONG_PRESS_KEY 0x04
1997 #define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02
1998 #define PALMAS_INT1_MASK_PWRON 0x02
1999 #define PALMAS_INT1_MASK_PWRON_SHIFT 0x01
2000 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV 0x01
2001 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
2003 /* Bit definitions for INT1_LINE_STATE */
2004 #define PALMAS_INT1_LINE_STATE_VBAT_MON 0x80
2005 #define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT 0x07
2006 #define PALMAS_INT1_LINE_STATE_VSYS_MON 0x40
2007 #define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06
2008 #define PALMAS_INT1_LINE_STATE_HOTDIE 0x20
2009 #define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT 0x05
2010 #define PALMAS_INT1_LINE_STATE_PWRDOWN 0x10
2011 #define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04
2012 #define PALMAS_INT1_LINE_STATE_RPWRON 0x08
2013 #define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT 0x03
2014 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY 0x04
2015 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02
2016 #define PALMAS_INT1_LINE_STATE_PWRON 0x02
2017 #define PALMAS_INT1_LINE_STATE_PWRON_SHIFT 0x01
2018 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV 0x01
2019 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
2021 /* Bit definitions for INT2_STATUS */
2022 #define PALMAS_INT2_STATUS_VAC_ACOK 0x80
2023 #define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT 0x07
2024 #define PALMAS_INT2_STATUS_SHORT 0x40
2025 #define PALMAS_INT2_STATUS_SHORT_SHIFT 0x06
2026 #define PALMAS_INT2_STATUS_FBI_BB 0x20
2027 #define PALMAS_INT2_STATUS_FBI_BB_SHIFT 0x05
2028 #define PALMAS_INT2_STATUS_RESET_IN 0x10
2029 #define PALMAS_INT2_STATUS_RESET_IN_SHIFT 0x04
2030 #define PALMAS_INT2_STATUS_BATREMOVAL 0x08
2031 #define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT 0x03
2032 #define PALMAS_INT2_STATUS_WDT 0x04
2033 #define PALMAS_INT2_STATUS_WDT_SHIFT 0x02
2034 #define PALMAS_INT2_STATUS_RTC_TIMER 0x02
2035 #define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT 0x01
2036 #define PALMAS_INT2_STATUS_RTC_ALARM 0x01
2037 #define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT 0x00
2039 /* Bit definitions for INT2_MASK */
2040 #define PALMAS_INT2_MASK_VAC_ACOK 0x80
2041 #define PALMAS_INT2_MASK_VAC_ACOK_SHIFT 0x07
2042 #define PALMAS_INT2_MASK_SHORT 0x40
2043 #define PALMAS_INT2_MASK_SHORT_SHIFT 0x06
2044 #define PALMAS_INT2_MASK_FBI_BB 0x20
2045 #define PALMAS_INT2_MASK_FBI_BB_SHIFT 0x05
2046 #define PALMAS_INT2_MASK_RESET_IN 0x10
2047 #define PALMAS_INT2_MASK_RESET_IN_SHIFT 0x04
2048 #define PALMAS_INT2_MASK_BATREMOVAL 0x08
2049 #define PALMAS_INT2_MASK_BATREMOVAL_SHIFT 0x03
2050 #define PALMAS_INT2_MASK_WDT 0x04
2051 #define PALMAS_INT2_MASK_WDT_SHIFT 0x02
2052 #define PALMAS_INT2_MASK_RTC_TIMER 0x02
2053 #define PALMAS_INT2_MASK_RTC_TIMER_SHIFT 0x01
2054 #define PALMAS_INT2_MASK_RTC_ALARM 0x01
2055 #define PALMAS_INT2_MASK_RTC_ALARM_SHIFT 0x00
2057 /* Bit definitions for INT2_LINE_STATE */
2058 #define PALMAS_INT2_LINE_STATE_VAC_ACOK 0x80
2059 #define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT 0x07
2060 #define PALMAS_INT2_LINE_STATE_SHORT 0x40
2061 #define PALMAS_INT2_LINE_STATE_SHORT_SHIFT 0x06
2062 #define PALMAS_INT2_LINE_STATE_FBI_BB 0x20
2063 #define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT 0x05
2064 #define PALMAS_INT2_LINE_STATE_RESET_IN 0x10
2065 #define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT 0x04
2066 #define PALMAS_INT2_LINE_STATE_BATREMOVAL 0x08
2067 #define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT 0x03
2068 #define PALMAS_INT2_LINE_STATE_WDT 0x04
2069 #define PALMAS_INT2_LINE_STATE_WDT_SHIFT 0x02
2070 #define PALMAS_INT2_LINE_STATE_RTC_TIMER 0x02
2071 #define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT 0x01
2072 #define PALMAS_INT2_LINE_STATE_RTC_ALARM 0x01
2073 #define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT 0x00
2075 /* Bit definitions for INT3_STATUS */
2076 #define PALMAS_INT3_STATUS_VBUS 0x80
2077 #define PALMAS_INT3_STATUS_VBUS_SHIFT 0x07
2078 #define PALMAS_INT3_STATUS_VBUS_OTG 0x40
2079 #define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT 0x06
2080 #define PALMAS_INT3_STATUS_ID 0x20
2081 #define PALMAS_INT3_STATUS_ID_SHIFT 0x05
2082 #define PALMAS_INT3_STATUS_ID_OTG 0x10
2083 #define PALMAS_INT3_STATUS_ID_OTG_SHIFT 0x04
2084 #define PALMAS_INT3_STATUS_GPADC_EOC_RT 0x08
2085 #define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT 0x03
2086 #define PALMAS_INT3_STATUS_GPADC_EOC_SW 0x04
2087 #define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02
2088 #define PALMAS_INT3_STATUS_GPADC_AUTO_1 0x02
2089 #define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01
2090 #define PALMAS_INT3_STATUS_GPADC_AUTO_0 0x01
2091 #define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00
2093 /* Bit definitions for INT3_MASK */
2094 #define PALMAS_INT3_MASK_VBUS 0x80
2095 #define PALMAS_INT3_MASK_VBUS_SHIFT 0x07
2096 #define PALMAS_INT3_MASK_VBUS_OTG 0x40
2097 #define PALMAS_INT3_MASK_VBUS_OTG_SHIFT 0x06
2098 #define PALMAS_INT3_MASK_ID 0x20
2099 #define PALMAS_INT3_MASK_ID_SHIFT 0x05
2100 #define PALMAS_INT3_MASK_ID_OTG 0x10
2101 #define PALMAS_INT3_MASK_ID_OTG_SHIFT 0x04
2102 #define PALMAS_INT3_MASK_GPADC_EOC_RT 0x08
2103 #define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT 0x03
2104 #define PALMAS_INT3_MASK_GPADC_EOC_SW 0x04
2105 #define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02
2106 #define PALMAS_INT3_MASK_GPADC_AUTO_1 0x02
2107 #define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01
2108 #define PALMAS_INT3_MASK_GPADC_AUTO_0 0x01
2109 #define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00
2111 /* Bit definitions for INT3_LINE_STATE */
2112 #define PALMAS_INT3_LINE_STATE_VBUS 0x80
2113 #define PALMAS_INT3_LINE_STATE_VBUS_SHIFT 0x07
2114 #define PALMAS_INT3_LINE_STATE_VBUS_OTG 0x40
2115 #define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT 0x06
2116 #define PALMAS_INT3_LINE_STATE_ID 0x20
2117 #define PALMAS_INT3_LINE_STATE_ID_SHIFT 0x05
2118 #define PALMAS_INT3_LINE_STATE_ID_OTG 0x10
2119 #define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT 0x04
2120 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT 0x08
2121 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT 0x03
2122 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW 0x04
2123 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02
2124 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1 0x02
2125 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01
2126 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0 0x01
2127 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00
2129 /* Bit definitions for INT4_STATUS */
2130 #define PALMAS_INT4_STATUS_GPIO_7 0x80
2131 #define PALMAS_INT4_STATUS_GPIO_7_SHIFT 0x07
2132 #define PALMAS_INT4_STATUS_GPIO_6 0x40
2133 #define PALMAS_INT4_STATUS_GPIO_6_SHIFT 0x06
2134 #define PALMAS_INT4_STATUS_GPIO_5 0x20
2135 #define PALMAS_INT4_STATUS_GPIO_5_SHIFT 0x05
2136 #define PALMAS_INT4_STATUS_GPIO_4 0x10
2137 #define PALMAS_INT4_STATUS_GPIO_4_SHIFT 0x04
2138 #define PALMAS_INT4_STATUS_GPIO_3 0x08
2139 #define PALMAS_INT4_STATUS_GPIO_3_SHIFT 0x03
2140 #define PALMAS_INT4_STATUS_GPIO_2 0x04
2141 #define PALMAS_INT4_STATUS_GPIO_2_SHIFT 0x02
2142 #define PALMAS_INT4_STATUS_GPIO_1 0x02
2143 #define PALMAS_INT4_STATUS_GPIO_1_SHIFT 0x01
2144 #define PALMAS_INT4_STATUS_GPIO_0 0x01
2145 #define PALMAS_INT4_STATUS_GPIO_0_SHIFT 0x00
2147 /* Bit definitions for INT4_MASK */
2148 #define PALMAS_INT4_MASK_GPIO_7 0x80
2149 #define PALMAS_INT4_MASK_GPIO_7_SHIFT 0x07
2150 #define PALMAS_INT4_MASK_GPIO_6 0x40
2151 #define PALMAS_INT4_MASK_GPIO_6_SHIFT 0x06
2152 #define PALMAS_INT4_MASK_GPIO_5 0x20
2153 #define PALMAS_INT4_MASK_GPIO_5_SHIFT 0x05
2154 #define PALMAS_INT4_MASK_GPIO_4 0x10
2155 #define PALMAS_INT4_MASK_GPIO_4_SHIFT 0x04
2156 #define PALMAS_INT4_MASK_GPIO_3 0x08
2157 #define PALMAS_INT4_MASK_GPIO_3_SHIFT 0x03
2158 #define PALMAS_INT4_MASK_GPIO_2 0x04
2159 #define PALMAS_INT4_MASK_GPIO_2_SHIFT 0x02
2160 #define PALMAS_INT4_MASK_GPIO_1 0x02
2161 #define PALMAS_INT4_MASK_GPIO_1_SHIFT 0x01
2162 #define PALMAS_INT4_MASK_GPIO_0 0x01
2163 #define PALMAS_INT4_MASK_GPIO_0_SHIFT 0x00
2165 /* Bit definitions for INT4_LINE_STATE */
2166 #define PALMAS_INT4_LINE_STATE_GPIO_7 0x80
2167 #define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT 0x07
2168 #define PALMAS_INT4_LINE_STATE_GPIO_6 0x40
2169 #define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT 0x06
2170 #define PALMAS_INT4_LINE_STATE_GPIO_5 0x20
2171 #define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT 0x05
2172 #define PALMAS_INT4_LINE_STATE_GPIO_4 0x10
2173 #define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT 0x04
2174 #define PALMAS_INT4_LINE_STATE_GPIO_3 0x08
2175 #define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT 0x03
2176 #define PALMAS_INT4_LINE_STATE_GPIO_2 0x04
2177 #define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT 0x02
2178 #define PALMAS_INT4_LINE_STATE_GPIO_1 0x02
2179 #define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT 0x01
2180 #define PALMAS_INT4_LINE_STATE_GPIO_0 0x01
2181 #define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT 0x00
2183 /* Bit definitions for INT4_EDGE_DETECT1 */
2184 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80
2185 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07
2186 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40
2187 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06
2188 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20
2189 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05
2190 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10
2191 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04
2192 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08
2193 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03
2194 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04
2195 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02
2196 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02
2197 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01
2198 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01
2199 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00
2201 /* Bit definitions for INT4_EDGE_DETECT2 */
2202 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING 0x80
2203 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT 0x07
2204 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING 0x40
2205 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT 0x06
2206 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20
2207 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05
2208 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10
2209 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04
2210 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08
2211 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03
2212 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04
2213 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02
2214 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02
2215 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01
2216 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01
2217 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00
2219 /* Bit definitions for INT_CTRL */
2220 #define PALMAS_INT_CTRL_INT_PENDING 0x04
2221 #define PALMAS_INT_CTRL_INT_PENDING_SHIFT 0x02
2222 #define PALMAS_INT_CTRL_INT_CLEAR 0x01
2223 #define PALMAS_INT_CTRL_INT_CLEAR_SHIFT 0x00
2225 /* Registers for function USB_OTG */
2226 #define PALMAS_USB_WAKEUP 0x03
2227 #define PALMAS_USB_VBUS_CTRL_SET 0x04
2228 #define PALMAS_USB_VBUS_CTRL_CLR 0x05
2229 #define PALMAS_USB_ID_CTRL_SET 0x06
2230 #define PALMAS_USB_ID_CTRL_CLEAR 0x07
2231 #define PALMAS_USB_VBUS_INT_SRC 0x08
2232 #define PALMAS_USB_VBUS_INT_LATCH_SET 0x09
2233 #define PALMAS_USB_VBUS_INT_LATCH_CLR 0x0A
2234 #define PALMAS_USB_VBUS_INT_EN_LO_SET 0x0B
2235 #define PALMAS_USB_VBUS_INT_EN_LO_CLR 0x0C
2236 #define PALMAS_USB_VBUS_INT_EN_HI_SET 0x0D
2237 #define PALMAS_USB_VBUS_INT_EN_HI_CLR 0x0E
2238 #define PALMAS_USB_ID_INT_SRC 0x0F
2239 #define PALMAS_USB_ID_INT_LATCH_SET 0x10
2240 #define PALMAS_USB_ID_INT_LATCH_CLR 0x11
2241 #define PALMAS_USB_ID_INT_EN_LO_SET 0x12
2242 #define PALMAS_USB_ID_INT_EN_LO_CLR 0x13
2243 #define PALMAS_USB_ID_INT_EN_HI_SET 0x14
2244 #define PALMAS_USB_ID_INT_EN_HI_CLR 0x15
2245 #define PALMAS_USB_OTG_ADP_CTRL 0x16
2246 #define PALMAS_USB_OTG_ADP_HIGH 0x17
2247 #define PALMAS_USB_OTG_ADP_LOW 0x18
2248 #define PALMAS_USB_OTG_ADP_RISE 0x19
2249 #define PALMAS_USB_OTG_REVISION 0x1A
2251 /* Bit definitions for USB_WAKEUP */
2252 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP 0x01
2253 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT 0x00
2255 /* Bit definitions for USB_VBUS_CTRL_SET */
2256 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS 0x80
2257 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT 0x07
2258 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG 0x20
2259 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT 0x05
2260 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC 0x10
2261 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT 0x04
2262 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK 0x08
2263 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT 0x03
2264 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP 0x04
2265 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT 0x02
2267 /* Bit definitions for USB_VBUS_CTRL_CLR */
2268 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS 0x80
2269 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT 0x07
2270 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG 0x20
2271 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT 0x05
2272 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC 0x10
2273 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT 0x04
2274 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK 0x08
2275 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT 0x03
2276 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP 0x04
2277 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT 0x02
2279 /* Bit definitions for USB_ID_CTRL_SET */
2280 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K 0x80
2281 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT 0x07
2282 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K 0x40
2283 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT 0x06
2284 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV 0x20
2285 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT 0x05
2286 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U 0x10
2287 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT 0x04
2288 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U 0x08
2289 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT 0x03
2290 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP 0x04
2291 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT 0x02
2293 /* Bit definitions for USB_ID_CTRL_CLEAR */
2294 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K 0x80
2295 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT 0x07
2296 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K 0x40
2297 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT 0x06
2298 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV 0x20
2299 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT 0x05
2300 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U 0x10
2301 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT 0x04
2302 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U 0x08
2303 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT 0x03
2304 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP 0x04
2305 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT 0x02
2307 /* Bit definitions for USB_VBUS_INT_SRC */
2308 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD 0x80
2309 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT 0x07
2310 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB 0x40
2311 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT 0x06
2312 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS 0x20
2313 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT 0x05
2314 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD 0x08
2315 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT 0x03
2316 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD 0x04
2317 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT 0x02
2318 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD 0x02
2319 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT 0x01
2320 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END 0x01
2321 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT 0x00
2323 /* Bit definitions for USB_VBUS_INT_LATCH_SET */
2324 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD 0x80
2325 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT 0x07
2326 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB 0x40
2327 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT 0x06
2328 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS 0x20
2329 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT 0x05
2330 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP 0x10
2331 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT 0x04
2332 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD 0x08
2333 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT 0x03
2334 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD 0x04
2335 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT 0x02
2336 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD 0x02
2337 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT 0x01
2338 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END 0x01
2339 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT 0x00
2341 /* Bit definitions for USB_VBUS_INT_LATCH_CLR */
2342 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD 0x80
2343 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT 0x07
2344 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB 0x40
2345 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT 0x06
2346 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS 0x20
2347 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT 0x05
2348 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP 0x10
2349 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT 0x04
2350 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD 0x08
2351 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT 0x03
2352 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD 0x04
2353 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT 0x02
2354 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD 0x02
2355 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT 0x01
2356 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END 0x01
2357 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT 0x00
2359 /* Bit definitions for USB_VBUS_INT_EN_LO_SET */
2360 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD 0x80
2361 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT 0x07
2362 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB 0x40
2363 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT 0x06
2364 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS 0x20
2365 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT 0x05
2366 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD 0x08
2367 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT 0x03
2368 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD 0x04
2369 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT 0x02
2370 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD 0x02
2371 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT 0x01
2372 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END 0x01
2373 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT 0x00
2375 /* Bit definitions for USB_VBUS_INT_EN_LO_CLR */
2376 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD 0x80
2377 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT 0x07
2378 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB 0x40
2379 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT 0x06
2380 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS 0x20
2381 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT 0x05
2382 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD 0x08
2383 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT 0x03
2384 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD 0x04
2385 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT 0x02
2386 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD 0x02
2387 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT 0x01
2388 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END 0x01
2389 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT 0x00
2391 /* Bit definitions for USB_VBUS_INT_EN_HI_SET */
2392 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD 0x80
2393 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT 0x07
2394 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB 0x40
2395 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT 0x06
2396 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS 0x20
2397 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT 0x05
2398 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP 0x10
2399 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT 0x04
2400 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD 0x08
2401 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT 0x03
2402 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD 0x04
2403 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT 0x02
2404 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD 0x02
2405 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT 0x01
2406 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END 0x01
2407 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT 0x00
2409 /* Bit definitions for USB_VBUS_INT_EN_HI_CLR */
2410 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD 0x80
2411 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT 0x07
2412 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB 0x40
2413 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT 0x06
2414 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS 0x20
2415 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT 0x05
2416 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP 0x10
2417 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT 0x04
2418 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD 0x08
2419 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT 0x03
2420 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD 0x04
2421 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT 0x02
2422 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD 0x02
2423 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT 0x01
2424 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END 0x01
2425 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT 0x00
2427 /* Bit definitions for USB_ID_INT_SRC */
2428 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT 0x10
2429 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT 0x04
2430 #define PALMAS_USB_ID_INT_SRC_ID_A 0x08
2431 #define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT 0x03
2432 #define PALMAS_USB_ID_INT_SRC_ID_B 0x04
2433 #define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT 0x02
2434 #define PALMAS_USB_ID_INT_SRC_ID_C 0x02
2435 #define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT 0x01
2436 #define PALMAS_USB_ID_INT_SRC_ID_GND 0x01
2437 #define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT 0x00
2439 /* Bit definitions for USB_ID_INT_LATCH_SET */
2440 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT 0x10
2441 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT 0x04
2442 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A 0x08
2443 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT 0x03
2444 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B 0x04
2445 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT 0x02
2446 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C 0x02
2447 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT 0x01
2448 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND 0x01
2449 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT 0x00
2451 /* Bit definitions for USB_ID_INT_LATCH_CLR */
2452 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT 0x10
2453 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT 0x04
2454 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A 0x08
2455 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT 0x03
2456 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B 0x04
2457 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT 0x02
2458 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C 0x02
2459 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT 0x01
2460 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND 0x01
2461 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT 0x00
2463 /* Bit definitions for USB_ID_INT_EN_LO_SET */
2464 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT 0x10
2465 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT 0x04
2466 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A 0x08
2467 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT 0x03
2468 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B 0x04
2469 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT 0x02
2470 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C 0x02
2471 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT 0x01
2472 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND 0x01
2473 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT 0x00
2475 /* Bit definitions for USB_ID_INT_EN_LO_CLR */
2476 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT 0x10
2477 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT 0x04
2478 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A 0x08
2479 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT 0x03
2480 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B 0x04
2481 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT 0x02
2482 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C 0x02
2483 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT 0x01
2484 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND 0x01
2485 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT 0x00
2487 /* Bit definitions for USB_ID_INT_EN_HI_SET */
2488 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT 0x10
2489 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT 0x04
2490 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A 0x08
2491 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT 0x03
2492 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B 0x04
2493 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT 0x02
2494 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C 0x02
2495 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT 0x01
2496 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND 0x01
2497 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT 0x00
2499 /* Bit definitions for USB_ID_INT_EN_HI_CLR */
2500 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT 0x10
2501 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT 0x04
2502 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A 0x08
2503 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT 0x03
2504 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B 0x04
2505 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT 0x02
2506 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C 0x02
2507 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT 0x01
2508 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND 0x01
2509 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT 0x00
2511 /* Bit definitions for USB_OTG_ADP_CTRL */
2512 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN 0x04
2513 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT 0x02
2514 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK 0x03
2515 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT 0x00
2517 /* Bit definitions for USB_OTG_ADP_HIGH */
2518 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK 0xFF
2519 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT 0x00
2521 /* Bit definitions for USB_OTG_ADP_LOW */
2522 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK 0xFF
2523 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT 0x00
2525 /* Bit definitions for USB_OTG_ADP_RISE */
2526 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK 0xFF
2527 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT 0x00
2529 /* Bit definitions for USB_OTG_REVISION */
2530 #define PALMAS_USB_OTG_REVISION_OTG_REV 0x01
2531 #define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT 0x00
2533 /* Registers for function VIBRATOR */
2534 #define PALMAS_VIBRA_CTRL 0x00
2536 /* Bit definitions for VIBRA_CTRL */
2537 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK 0x06
2538 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT 0x01
2539 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL 0x01
2540 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT 0x00
2542 /* Registers for function GPIO */
2543 #define PALMAS_GPIO_DATA_IN 0x00
2544 #define PALMAS_GPIO_DATA_DIR 0x01
2545 #define PALMAS_GPIO_DATA_OUT 0x02
2546 #define PALMAS_GPIO_DEBOUNCE_EN 0x03
2547 #define PALMAS_GPIO_CLEAR_DATA_OUT 0x04
2548 #define PALMAS_GPIO_SET_DATA_OUT 0x05
2549 #define PALMAS_PU_PD_GPIO_CTRL1 0x06
2550 #define PALMAS_PU_PD_GPIO_CTRL2 0x07
2551 #define PALMAS_OD_OUTPUT_GPIO_CTRL 0x08
2552 #define PALMAS_GPIO_DATA_IN2 0x09
2553 #define PALMAS_GPIO_DATA_DIR2 0x0A
2554 #define PALMAS_GPIO_DATA_OUT2 0x0B
2555 #define PALMAS_GPIO_DEBOUNCE_EN2 0x0C
2556 #define PALMAS_GPIO_CLEAR_DATA_OUT2 0x0D
2557 #define PALMAS_GPIO_SET_DATA_OUT2 0x0E
2558 #define PALMAS_PU_PD_GPIO_CTRL3 0x0F
2559 #define PALMAS_PU_PD_GPIO_CTRL4 0x10
2560 #define PALMAS_OD_OUTPUT_GPIO_CTRL2 0x11
2562 /* Bit definitions for GPIO_DATA_IN */
2563 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80
2564 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT 0x07
2565 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN 0x40
2566 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT 0x06
2567 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN 0x20
2568 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT 0x05
2569 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN 0x10
2570 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT 0x04
2571 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN 0x08
2572 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT 0x03
2573 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN 0x04
2574 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT 0x02
2575 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN 0x02
2576 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT 0x01
2577 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN 0x01
2578 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT 0x00
2580 /* Bit definitions for GPIO_DATA_DIR */
2581 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR 0x80
2582 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT 0x07
2583 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR 0x40
2584 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT 0x06
2585 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR 0x20
2586 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT 0x05
2587 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR 0x10
2588 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT 0x04
2589 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR 0x08
2590 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT 0x03
2591 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR 0x04
2592 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT 0x02
2593 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR 0x02
2594 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT 0x01
2595 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR 0x01
2596 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT 0x00
2598 /* Bit definitions for GPIO_DATA_OUT */
2599 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT 0x80
2600 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT 0x07
2601 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT 0x40
2602 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT 0x06
2603 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT 0x20
2604 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT 0x05
2605 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT 0x10
2606 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT 0x04
2607 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT 0x08
2608 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT 0x03
2609 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT 0x04
2610 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT 0x02
2611 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT 0x02
2612 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT 0x01
2613 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT 0x01
2614 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT 0x00
2616 /* Bit definitions for GPIO_DEBOUNCE_EN */
2617 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN 0x80
2618 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT 0x07
2619 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN 0x40
2620 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT 0x06
2621 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN 0x20
2622 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT 0x05
2623 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN 0x10
2624 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT 0x04
2625 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN 0x08
2626 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT 0x03
2627 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN 0x04
2628 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT 0x02
2629 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN 0x02
2630 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT 0x01
2631 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN 0x01
2632 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT 0x00
2634 /* Bit definitions for GPIO_CLEAR_DATA_OUT */
2635 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT 0x80
2636 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT 0x07
2637 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT 0x40
2638 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT 0x06
2639 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT 0x20
2640 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT 0x05
2641 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT 0x10
2642 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT 0x04
2643 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT 0x08
2644 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT 0x03
2645 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT 0x04
2646 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT 0x02
2647 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT 0x02
2648 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT 0x01
2649 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT 0x01
2650 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT 0x00
2652 /* Bit definitions for GPIO_SET_DATA_OUT */
2653 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT 0x80
2654 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT 0x07
2655 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT 0x40
2656 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT 0x06
2657 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT 0x20
2658 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT 0x05
2659 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT 0x10
2660 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT 0x04
2661 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT 0x08
2662 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT 0x03
2663 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT 0x04
2664 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT 0x02
2665 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT 0x02
2666 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT 0x01
2667 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT 0x01
2668 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT 0x00
2670 /* Bit definitions for PU_PD_GPIO_CTRL1 */
2671 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD 0x40
2672 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT 0x06
2673 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU 0x20
2674 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT 0x05
2675 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD 0x10
2676 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT 0x04
2677 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU 0x08
2678 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT 0x03
2679 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD 0x04
2680 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT 0x02
2681 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD 0x01
2682 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT 0x00
2684 /* Bit definitions for PU_PD_GPIO_CTRL2 */
2685 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD 0x40
2686 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT 0x06
2687 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU 0x20
2688 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT 0x05
2689 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD 0x10
2690 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT 0x04
2691 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU 0x08
2692 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT 0x03
2693 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD 0x04
2694 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT 0x02
2695 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU 0x02
2696 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT 0x01
2697 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD 0x01
2698 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT 0x00
2700 /* Bit definitions for OD_OUTPUT_GPIO_CTRL */
2701 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD 0x20
2702 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT 0x05
2703 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD 0x04
2704 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT 0x02
2705 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD 0x02
2706 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT 0x01
2708 /* Registers for function GPADC */
2709 #define PALMAS_GPADC_CTRL1 0x00
2710 #define PALMAS_GPADC_CTRL2 0x01
2711 #define PALMAS_GPADC_RT_CTRL 0x02
2712 #define PALMAS_GPADC_AUTO_CTRL 0x03
2713 #define PALMAS_GPADC_STATUS 0x04
2714 #define PALMAS_GPADC_RT_SELECT 0x05
2715 #define PALMAS_GPADC_RT_CONV0_LSB 0x06
2716 #define PALMAS_GPADC_RT_CONV0_MSB 0x07
2717 #define PALMAS_GPADC_AUTO_SELECT 0x08
2718 #define PALMAS_GPADC_AUTO_CONV0_LSB 0x09
2719 #define PALMAS_GPADC_AUTO_CONV0_MSB 0x0A
2720 #define PALMAS_GPADC_AUTO_CONV1_LSB 0x0B
2721 #define PALMAS_GPADC_AUTO_CONV1_MSB 0x0C
2722 #define PALMAS_GPADC_SW_SELECT 0x0D
2723 #define PALMAS_GPADC_SW_CONV0_LSB 0x0E
2724 #define PALMAS_GPADC_SW_CONV0_MSB 0x0F
2725 #define PALMAS_GPADC_THRES_CONV0_LSB 0x10
2726 #define PALMAS_GPADC_THRES_CONV0_MSB 0x11
2727 #define PALMAS_GPADC_THRES_CONV1_LSB 0x12
2728 #define PALMAS_GPADC_THRES_CONV1_MSB 0x13
2729 #define PALMAS_GPADC_SMPS_ILMONITOR_EN 0x14
2730 #define PALMAS_GPADC_SMPS_VSEL_MONITORING 0x15
2732 /* Bit definitions for GPADC_CTRL1 */
2733 #define PALMAS_GPADC_CTRL1_RESERVED_MASK 0xc0
2734 #define PALMAS_GPADC_CTRL1_RESERVED_SHIFT 0x06
2735 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK 0x30
2736 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT 0x04
2737 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK 0x0c
2738 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT 0x02
2739 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET 0x02
2740 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT 0x01
2741 #define PALMAS_GPADC_CTRL1_GPADC_FORCE 0x01
2742 #define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT 0x00
2744 /* Bit definitions for GPADC_CTRL2 */
2745 #define PALMAS_GPADC_CTRL2_RESERVED_MASK 0x06
2746 #define PALMAS_GPADC_CTRL2_RESERVED_SHIFT 0x01
2748 /* Bit definitions for GPADC_RT_CTRL */
2749 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY 0x02
2750 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT 0x01
2751 #define PALMAS_GPADC_RT_CTRL_START_POLARITY 0x01
2752 #define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT 0x00
2754 /* Bit definitions for GPADC_AUTO_CTRL */
2755 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 0x80
2756 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT 0x07
2757 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 0x40
2758 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT 0x06
2759 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN 0x20
2760 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT 0x05
2761 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN 0x10
2762 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT 0x04
2763 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK 0x0F
2764 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT 0x00
2766 /* Bit definitions for GPADC_STATUS */
2767 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE 0x10
2768 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT 0x04
2770 /* Bit definitions for GPADC_RT_SELECT */
2771 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN 0x80
2772 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT 0x07
2773 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK 0x0F
2774 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT 0x00
2776 /* Bit definitions for GPADC_RT_CONV0_LSB */
2777 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK 0xFF
2778 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT 0x00
2780 /* Bit definitions for GPADC_RT_CONV0_MSB */
2781 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK 0x0F
2782 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT 0x00
2784 /* Bit definitions for GPADC_AUTO_SELECT */
2785 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK 0xF0
2786 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT 0x04
2787 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK 0x0F
2788 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT 0x00
2790 /* Bit definitions for GPADC_AUTO_CONV0_LSB */
2791 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK 0xFF
2792 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT 0x00
2794 /* Bit definitions for GPADC_AUTO_CONV0_MSB */
2795 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK 0x0F
2796 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT 0x00
2798 /* Bit definitions for GPADC_AUTO_CONV1_LSB */
2799 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK 0xFF
2800 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT 0x00
2802 /* Bit definitions for GPADC_AUTO_CONV1_MSB */
2803 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK 0x0F
2804 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT 0x00
2806 /* Bit definitions for GPADC_SW_SELECT */
2807 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN 0x80
2808 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT 0x07
2809 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0 0x10
2810 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT 0x04
2811 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK 0x0F
2812 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT 0x00
2814 /* Bit definitions for GPADC_SW_CONV0_LSB */
2815 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK 0xFF
2816 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT 0x00
2818 /* Bit definitions for GPADC_SW_CONV0_MSB */
2819 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK 0x0F
2820 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT 0x00
2822 /* Bit definitions for GPADC_THRES_CONV0_LSB */
2823 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK 0xFF
2824 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT 0x00
2826 /* Bit definitions for GPADC_THRES_CONV0_MSB */
2827 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL 0x80
2828 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT 0x07
2829 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK 0x0F
2830 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT 0x00
2832 /* Bit definitions for GPADC_THRES_CONV1_LSB */
2833 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK 0xFF
2834 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT 0x00
2836 /* Bit definitions for GPADC_THRES_CONV1_MSB */
2837 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL 0x80
2838 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT 0x07
2839 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK 0x0F
2840 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT 0x00
2842 /* Bit definitions for GPADC_SMPS_ILMONITOR_EN */
2843 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN 0x20
2844 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT 0x05
2845 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT 0x10
2846 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT 0x04
2847 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK 0x0F
2848 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT 0x00
2850 /* Bit definitions for GPADC_SMPS_VSEL_MONITORING */
2851 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE 0x80
2852 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT 0x07
2853 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK 0x7F
2854 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT 0x00
2856 /* Registers for function GPADC */
2857 #define PALMAS_GPADC_TRIM1 0x00
2858 #define PALMAS_GPADC_TRIM2 0x01
2859 #define PALMAS_GPADC_TRIM3 0x02
2860 #define PALMAS_GPADC_TRIM4 0x03
2861 #define PALMAS_GPADC_TRIM5 0x04
2862 #define PALMAS_GPADC_TRIM6 0x05
2863 #define PALMAS_GPADC_TRIM7 0x06
2864 #define PALMAS_GPADC_TRIM8 0x07
2865 #define PALMAS_GPADC_TRIM9 0x08
2866 #define PALMAS_GPADC_TRIM10 0x09
2867 #define PALMAS_GPADC_TRIM11 0x0A
2868 #define PALMAS_GPADC_TRIM12 0x0B
2869 #define PALMAS_GPADC_TRIM13 0x0C
2870 #define PALMAS_GPADC_TRIM14 0x0D
2871 #define PALMAS_GPADC_TRIM15 0x0E
2872 #define PALMAS_GPADC_TRIM16 0x0F
2874 static inline int palmas_read(struct palmas *palmas, unsigned int base,
2875 unsigned int reg, unsigned int *val)
2877 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2878 int slave_id = PALMAS_BASE_TO_SLAVE(base);
2880 return regmap_read(palmas->regmap[slave_id], addr, val);
2883 static inline int palmas_write(struct palmas *palmas, unsigned int base,
2884 unsigned int reg, unsigned int value)
2886 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2887 int slave_id = PALMAS_BASE_TO_SLAVE(base);
2889 return regmap_write(palmas->regmap[slave_id], addr, value);
2892 static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base,
2893 unsigned int reg, const void *val, size_t val_count)
2895 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2896 int slave_id = PALMAS_BASE_TO_SLAVE(base);
2898 return regmap_bulk_write(palmas->regmap[slave_id], addr,
2902 static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base,
2903 unsigned int reg, void *val, size_t val_count)
2905 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2906 int slave_id = PALMAS_BASE_TO_SLAVE(base);
2908 return regmap_bulk_read(palmas->regmap[slave_id], addr,
2912 static inline int palmas_update_bits(struct palmas *palmas, unsigned int base,
2913 unsigned int reg, unsigned int mask, unsigned int val)
2915 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
2916 int slave_id = PALMAS_BASE_TO_SLAVE(base);
2918 return regmap_update_bits(palmas->regmap[slave_id], addr, mask, val);
2921 static inline int palmas_irq_get_virq(struct palmas *palmas, int irq)
2923 return regmap_irq_get_virq(palmas->irq_data, irq);
2927 int palmas_ext_control_req_config(struct palmas *palmas,
2928 enum palmas_external_requestor_id ext_control_req_id,
2929 int ext_ctrl, bool enable);
2931 #endif /* __LINUX_MFD_PALMAS_H */