include/linux/mfd/rk610_core.h

   1 #ifndef __RK610_CONTROL_H_
   2 #define __RK610_CONTROL_H_
   3
   4 #define INVALID_GPIO -1
   5 //#define RK610_DEBUG
   6
   7 #ifdef RK610_DEBUG
   8 #define RK610_DBG(dev, format, arg...)          \
   9 do{\
  10                 dev_printk(KERN_INFO , dev , format , ## arg);\
  11 }while(0)
  12 #else
  13 #define RK610_DBG(dev, format, arg...)
  14 #endif
  15 #define RK610_ERR(dev, format, arg...)          \
  16 do{\
  17                 dev_printk(KERN_ERR , dev , format , ## arg);\
  18 }while(0)
  19
  20 #define RK610_CONTROL_REG_C_PLL_CON0    0x00
  21 #define RK610_CONTROL_REG_C_PLL_CON1    0x01
  22 #define RK610_CONTROL_REG_C_PLL_CON2    0x02
  23 #define RK610_CONTROL_REG_C_PLL_CON3    0x03
  24 #define RK610_CONTROL_REG_C_PLL_CON4    0x04
  25 #define RK610_CONTROL_REG_C_PLL_CON5    0x05
  26         #define C_PLL_DISABLE_FRAC              1 << 0
  27         #define C_PLL_BYPSS_ENABLE              1 << 1
  28         #define C_PLL_POWER_ON                  1 << 2
  29         #define C_PLL_LOCLED                    1 << 7
  30
  31 #define RK610_CONTROL_REG_TVE_CON               0x29
  32         #define TVE_CONTROL_VDAC_R_BYPASS_ENABLE        1 << 7
  33         #define TVE_CONTROL_VDAC_R_BYPASS_DISABLE       0 << 7
  34         #define TVE_CONTROL_CVBS_3_CHANNEL_ENALBE       1 << 6
  35         #define TVE_CONTROL_CVBS_3_CHANNEL_DISALBE      0 << 5
  36 enum {
  37         INPUT_DATA_FORMAT_RGB888 = 0,
  38         INPUT_DATA_FORMAT_RGB666,
  39         INPUT_DATA_FORMAT_RGB565,
  40         INPUT_DATA_FORMAT_YUV
  41 };
  42         #define RGB2CCIR_INPUT_DATA_FORMAT(n)   n << 4
  43
  44         #define RGB2CCIR_RGB_SWAP_ENABLE                1 << 3
  45         #define RGB2CCIR_RGB_SWAP_DISABLE               0 << 3
  46
  47         #define RGB2CCIR_INPUT_INTERLACE                1 << 2
  48         #define RGB2CCIR_INPUT_PROGRESSIVE              0 << 2
  49
  50         #define RGB2CCIR_CVBS_PAL                               0 << 1
  51         #define RGB2CCIR_CVBS_NTSC                              1 << 1
  52
  53         #define RGB2CCIR_DISABLE                                0
  54         #define RGB2CCIR_ENABLE                                 1
  55
  56 #define RK610_CONTROL_REG_CCIR_RESET    0x2a
  57
  58 #define RK610_CONTROL_REG_CLOCK_CON0    0x2b
  59 #define RK610_CONTROL_REG_CLOCK_CON1    0x2c
  60         #define CLOCK_CON1_I2S_CLK_CODEC_PLL    1 << 5
  61         #define CLOCK_CON1_I2S_DVIDER_MASK              0x1F
  62 #define RK610_CONTROL_REG_CODEC_CON             0x2d
  63         #define CODEC_CON_BIT_HDMI_BLCK_INTERANL                1<<4
  64         #define CODEC_CON_BIT_DAC_LRCL_OUTPUT_DISABLE   1<<3
  65         #define CODEC_CON_BIT_ADC_LRCK_OUTPUT_DISABLE   1<<2
  66         #define CODEC_CON_BIT_INTERAL_CODEC_DISABLE             1<<0
  67
  68 #define RK610_CONTROL_REG_I2C_CON               0x2e
  69
  70 /********************************************************************
  71 **                          ½á¹¹¶¨Òå                                *
  72 ********************************************************************/
  73 /* RK610µÄ¼Ä´æÆ÷½á¹¹ */
  74 /* CODEC PLL REG */
  75 #define C_PLL_CON0      0x00
  76 #define C_PLL_CON1      0x01
  77 #define C_PLL_CON2      0x02
  78 #define C_PLL_CON3      0x03
  79 #define C_PLL_CON4      0x04
  80 #define C_PLL_CON5      0x05
  81
  82 /*  SCALER PLL REG */
  83 #define S_PLL_CON0      0x06
  84 #define S_PLL_CON1      0x07
  85 #define S_PLL_CON2      0x08
  86
  87 /*  LVDS REG */
  88 #define LVDS_CON0       0x09
  89 #define LVDS_CON1       0x0a
  90
  91 /*  LCD1 REG */
  92 #define LCD1_CON        0x0b
  93
  94 /*  SCALER REG  */
  95 #define SCL_CON0        0x0c
  96 #define SCL_CON1        0x0d
  97 #define SCL_CON2        0x0e
  98 #define SCL_CON3        0x0f
  99 #define SCL_CON4        0x10
 100 #define SCL_CON5        0x11
 101 #define SCL_CON6        0x12
 102 #define SCL_CON7        0x13
 103 #define SCL_CON8        0x14
 104 #define SCL_CON9        0x15
 105 #define SCL_CON10       0x16
 106 #define SCL_CON11       0x17
 107 #define SCL_CON12       0x18
 108 #define SCL_CON13       0x19
 109 #define SCL_CON14       0x1a
 110 #define SCL_CON15       0x1b
 111 #define SCL_CON16       0x1c
 112 #define SCL_CON17       0x1d
 113 #define SCL_CON18       0x1e
 114 #define SCL_CON19       0x1f
 115 #define SCL_CON20       0x20
 116 #define SCL_CON21       0x21
 117 #define SCL_CON22       0x22
 118 #define SCL_CON23       0x23
 119 #define SCL_CON24       0x24
 120 #define SCL_CON25       0x25
 121 #define SCL_CON26       0x26
 122 #define SCL_CON27       0x27
 123 #define SCL_CON28       0x28
 124
 125 /*  TVE REG  */
 126 #define TVE_CON         0x29
 127
 128 /*  CCIR REG    */
 129 #define CCIR_RESET      0X2a
 130
 131 /*  CLOCK REG    */
 132 #define CLOCK_CON0      0X2b
 133 #define CLOCK_CON1      0X2c
 134
 135 /*  CODEC REG    */
 136 #define CODEC_CON       0x2e
 137 #define I2C_CON         0x2f
 138
 139
 140 struct rk610_core_info{
 141     struct i2c_client *client;
 142     struct device *dev;
 143
 144     struct dentry *debugfs_dir;
 145     void *lcd_pdata;
 146         struct clk *i2s_clk;
 147         int reset_gpio;
 148 };
 149
 150 extern int rk610_control_send_byte(const char reg, const char data);
 151
 152 #endif /*end of __RK610_CONTROL_H_*/