4 #include <linux/types.h>
6 #include <linux/rk_fb.h>
8 #include <linux/delay.h>
10 #if defined(CONFIG_RK616_DEBUG)
11 #define rk616_dbg(dev, format, arg...) \
12 dev_info(dev , format , ## arg)
14 #define rk616_dbg(dev, format, arg...) do{}while(0)
17 #define VIF0_REG0 0x0000
18 #define VIF0_DDR_CLK_EN (1<<3)
19 #define VIF0_DDR_PHASEN_EN (1<<2) //negative edge first en
20 #define VIF0_DDR_MODE_EN (1<<1)
21 #define VIF0_EN (1<<0)
23 #define VIF0_REG1 0x0004
24 #define VIF0_REG2 0x0008
25 #define VIF0_REG3 0x000C
26 #define VIF0_REG4 0x0010
27 #define VIF0_REG5 0x0014
28 #define VIF1_REG0 0x0018
29 #define VIF1_REG1 0x001C
30 #define VIF1_REG2 0x0020
31 #define VIF1_REG3 0x0024
32 #define VIF1_REG4 0x0028
33 #define VIF1_REG5 0x002C
34 #define SCL_REG0 0x0030
37 #define SCL_REG1 0x0034
38 #define SCL_REG2 0x0038
39 #define SCL_REG3 0x003C
40 #define SCL_REG4 0x0040
41 #define SCL_REG5 0x0044
42 #define SCL_REG6 0x0048
43 #define SCL_REG7 0x004C
44 #define SCL_REG8 0x0050
45 #define FRC_REG 0x0054
46 #define FRC_DEN_INV (1<<6)
47 #define FRC_SYNC_INV (1<<5)
48 #define FRC_DCLK_INV (1<<4)
49 #define FRC_OUT_ZERO (1<<3)
50 #define FRC_RGB18_MODE (1<<2)
51 #define FRC_HIFRC_MODE (1<<1)
52 #define FRC_DITHER_EN (1<<0)
54 #define CRU_CLKSEL0_CON 0x0058
55 #define PLL1_CLK_SEL_MASK (0x3<<24)
56 #define PLL0_CLK_SEL_MASK (0x3<<22)
57 #define LCD1_CLK_DIV_MASK (0x7<<19)
58 #define LCD0_CLK_DIV_MASK (0x7<<16)
59 #define PLL1_CLK_SEL(x) (((x)&3)<<8)
60 #define PLL0_CLK_SEL(x) (((x)&3)<<6)
64 #define LCD1_CLK_DIV(x) (((x)&7)<<3)
65 #define LCD0_CLK_DIV(x) (((x)&7)<<0)
67 #define CRU_CLKSEL1_CON 0x005C
68 #define SCLK_SEL_MASK (1<<19)
69 #define CODEC_MCLK_SEL_MASK (3<<16)
70 #define LCDC_CLK_GATE (1<<12)
71 #define LCDC1_CLK_GATE (1<<11)
72 #define MIPI_CLK_GATE (1<<10)
73 #define LVDS_CLK_GATE (1<<9)
74 #define HDMI_CLK_GATE (1<<8)
75 #define SCL_CLK_DIV(x) (((x)&7)<<5)
76 #define SCL_CLK_GATE (1<<4)
77 #define SCLK_SEL(x) (((x)&1)<<3)
78 #define SCLK_SEL_PLL0 0
79 #define SCLK_SEL_PLL1 1
80 #define CODEC_CLK_GATE (1<<2)
81 #define CODEC_MCLK_SEL(x) (((x)&3)<<0)
82 #define CODEC_MCLK_SEL_PLL0 0
83 #define CODEC_MCLK_SEL_PLL1 1
84 #define CODEC_MCLK_SEL_12M 2
86 #define CRU_CODEC_DIV 0x0060
88 #define CRU_CLKSEL2_CON 0x0064
89 #define SCL_IN_SEL_MASK (1<<31)
90 #define DITHER_IN_SEL_MASK (1<<30)
91 #define HDMI_IN_SEL_MASK (3<<28)
92 #define VIF1_CLK_DIV_MASK (7<<25)
93 #define VIF0_CLK_DIV_MASK (7<<19)
94 #define VIF1_CLKIN_SEL_MASK (1<<22)
95 #define VIF0_CLKIN_SEL_MASK (1<<16)
96 #define SCL_IN_SEL(x) (((x)&1)<<15)
97 #define SCL_SEL_VIF0 0
98 #define SCL_SEL_VIF1 1
99 #define DITHER_IN_SEL(x) (((x)&1)<<14)
100 #define DITHER_SEL_VIF0 0
101 #define DITHER_SEL_SCL 1
103 #define HDMI_IN_SEL(x) (((x)&3)<<12) //hdmi data in select
104 #define HDMI_IN_SEL_VIF1 0
105 #define HDMI_IN_SEL_SCL 1
106 #define HDMI_IN_SEL_VIF0 2
107 #define VIF1_CLK_DIV(x) (((x)&7)<<9)
108 #define VIF1_CLK_GATE (1<<8)
109 #define VIF1_CLK_BYPASS (1<<7)
110 #define VIF1_CLKIN_SEL(x) (((x)&1)<<6)
111 #define VIF_CLKIN_SEL_PLL0 0
112 #define VIF_CLKIN_SEL_PLL1 1
113 #define VIF0_CLK_DIV(x) (((x)&7)<<3)
114 #define VIF0_CLK_GATE (1<<2)
115 #define VIF0_CLK_BYPASS (1<<1)
116 #define VIF0_CLKIN_SEL(x) (((x)&1)<<0)
119 #define CRU_PLL0_CON0 0x0068
120 #define PLL0_POSTDIV1_MASK (7<<28)
121 #define PLL0_FBDIV_MASK (0xfff << 16)
122 #define PLL0_BYPASS (1<<15)
123 #define PLL0_POSTDIV1(x) (((x)&7)<<12)
124 #define PLL0_FBDIV(x) (((x)&0xfff)<<0)
126 #define CRU_PLL0_CON1 0x006C
127 #define PLL0_DIV_MODE_MASK (1<<25)
128 #define PLL0_POSTDIV2_MASK (7<<22)
129 #define PLL0_REFDIV_MASK (0x3f<<16)
130 #define PLL0_LOCK (1<<15)
131 #define PLL0_PWR_DN (1<<10)
132 #define PLL0_DIV_MODE(x) (((x)&1)<<9)
133 #define PLL0_POSTDIV2(x) (((x)&7)<<6)
134 #define PLL0_REFDIV(x) (((x)&0x3f)<<0)
136 #define CRU_PLL0_CON2 0x0070
137 #define PLL0_FOUT4_PWR_DN (1<<27)
138 #define PLL0_FOUTVCO_PWR_DN (1<<26)
139 #define PLL0_POSTDIV_PWR_DN (1<<25)
140 #define PLL0_DAC_PWR_DN (1<<24)
141 #define PLL0_FRAC(x) (((x)&0xffffff)<<0)
143 #define CRU_PLL1_CON0 0x0074
144 #define PLL1_POSTDIV1_MASK (7<<28)
145 #define PLL1_FBDIV_MASK (0xfff << 16)
146 #define PLL1_BYPASS (1<<15)
147 #define PLL1_POSTDIV1(x) (((x)&7)<<12)
148 #define PLL1_FBDIV(x) (((x)&0xfff)<<0)
150 #define CRU_PLL1_CON1 0x0078
151 #define PLL1_POSTDIV2_MASK (7<<22)
152 #define PLL1_REFDIV_MASK (0x3f<<16)
153 #define PLL1_LOCK (1<<15)
154 #define PLL1_PWR_DN (1<<10)
155 #define PLL1_DIV_MODE (1<<9)
156 #define PLL1_POSTDIV2(x) (((x)&7)<<6)
157 #define PLL1_REFDIV(x) (((x)&0x3f)<<0)
159 #define CRU_PLL1_CON2 0x007C
160 #define PLL1_FOUT4_PWR_DN (1<<27)
161 #define PLL1_FOUTVCO_PWR_DN (1<<26)
162 #define PLL1_POSTDIV_PWR_DN (1<<25)
163 #define PLL1_DAC_PWR_DN (1<<24)
164 #define PLL1_FRAC(x) (((x)&0xffffff)<<0)
166 #define CRU_I2C_CON0 0x0080
168 #define CRU_LVDS_CON0 0x0084
169 #define LVDS_HBP_ODD_MASK (0x1<<30)
170 #define LVDS_OUT_FORMAT_MASK (3<<16)
171 #define LVDS_HBP_ODD(x) (((x)&1)<<14)
172 #define LVDS_DCLK_INV (1<<13)
173 #define LVDS_CH1_LOAD (1<<12)
174 #define LVDS_CH0_LOAD (1<<11)
175 #define LVDS_CH1TTL_EN (1<<10)
176 #define LVDS_CH0TTL_EN (1<<9)
177 #define LVDS_CH1_PWR_EN (1<<8)
178 #define LVDS_CH0_PWR_EN (1<<7)
179 #define LVDS_CBG_PWR_EN (1<<6)
180 #define LVDS_PLL_PWR_DN (1<<5)
181 #define LVDS_START_CH_SEL (1<<4)
182 #define LVDS_CH_SEL (1<<3)
183 #define LVDS_MSB_SEL (1<<2)
184 #define LVDS_OUT_FORMAT(x) (((x)&3)<<0)
187 #define CRU_IO_CON0 0x0088
188 #define VIF1_SYNC_EN (1<<15)
189 #define VIF0_SYNC_EN (1<<14)
190 #define I2S1_OUT_DISABLE (1<<13)
191 #define I2S0_OUT_DISABLE (1<<12)
192 #define LVDS_OUT_EN (1<<11)
193 #define LCD1_INPUT_EN (1<<10)
194 #define LVDS_RGBIO_PD_DISABLE (1<<9)
195 #define LCD1_IO_PD_DISABLE (1<<8)
196 #define LCD0_IO_PD_DISABLE (1<<7)
197 #define HDMI_IO_PU_DISABLE (1<<6)
198 #define SPDIF_IO_PD_DISABLE (1<<5)
199 #define I2S1_PD_DISABLE (1<<4)
200 #define I2S0_PD_DISABLE (1<<3)
201 #define I2C_PU_DISABLE (1<<2)
202 #define INT_IO_PU (1<<1)
203 #define CLKIN_PU (1<<0)
206 #define CRU_IO_CON1 0x008C
207 #define LVDS_RGBIO_SI_EN (1<<9) //shmitt input enable
208 #define LCD1_SI_EN (1<<8)
209 #define LCD0_SI_EN (1<<7)
210 #define HDMI_SI_EN (1<<6)
211 #define SPDIF_SI_EN (1<<5)
212 #define I2S1_SI_EN (1<<4)
213 #define I2S0_SI_EN (1<<3)
214 #define I2C_SI_EN (1<<2)
215 #define INT_SI_EN (1<<1)
216 #define CLKIN_SI_EN (1<<0)
217 #define CRU_PCM2IS2_CON0 0x0090
218 #define CRU_PCM2IS2_CON1 0x0094
219 #define CRU_PCM2IS2_CON2 0x0098
220 #define CRU_CFGMISC_CON 0x009C
221 #define HDMI_CLK_SEL_MASK (3<<12)
222 #define HDMI_CLK_SEL(x) (((x)&3)<<12) //hdmi data in select
223 #define HDMI_CLK_SEL_VIF1 0
224 #define HDMI_CLK_SEL_SCL 1
225 #define HDMI_CLK_SEL_VIF0 2
228 enum lcd_port_func{ // the function of lcd ports(lcd0,lcd1),the lcd0 only can be used as input or unused
229 UNUSED, // the lcd1 can be used as input,output or unused
238 struct rk616_platform_data {
239 int (*power_init)(void);
240 int (*power_deinit)(void);
242 enum lcd_port_func lcd0_func;
243 enum lcd_port_func lcd1_func;
244 int lvds_ch_nr; //the number of used lvds channel
266 enum lvds_mode lvds_mode; //RGB or LVDS
267 int lvds_ch_nr; //the number of used lvds channel
271 struct mutex reg_lock;
274 unsigned int irq_base;
275 struct rk616_platform_data *pdata;
276 struct rk616_route route; //display path router
277 struct i2c_client *client;
282 struct dentry *debugfs_dir;
283 int (*read_dev)(struct mfd_rk616 *rk616,u16 reg,u32 *pval);
284 int (*write_dev)(struct mfd_rk616 *rk616,u16 reg,u32 *pval);
285 int (*write_dev_bits)(struct mfd_rk616 *rk616,u16 reg,u32 mask,u32 *pval);
286 int (*write_bulk)(struct mfd_rk616 *rk616,u16 reg,int count,u32 *pval);
289 extern int rk616_set_vif(struct mfd_rk616 * rk616,struct rk_screen * screen,bool connect);
290 extern int rk616_display_router_cfg(struct mfd_rk616 *rk616,struct rk_screen *screen,bool enable);
291 extern void rk616_mclk_set_rate(struct clk *mclk,unsigned long rate);