include/linux/mfd/rt5025.h

   1 /*
   2  *  include/linux/mfd/rt5025.h
   3  *  Include header file for Richtek RT5025 Core file
   4  *
   5  *  Copyright (C) 2013 Richtek Electronics
   6  *  cy_huang <cy_huang@richtek.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #ifndef __LINUX_MFD_RT5025_H
  14 #define __LINUX_MFD_RT5025_H
  15
  16 #include <linux/power_supply.h>
  17
  18 #define RT5025_DEVICE_NAME "RT5025"
  19
  20 enum {
  21         RT5025_RSTDELAY1_100MS,
  22         RT5025_RSTDELAY1_500MS,
  23         RT5025_RSTDELAY1_1S,
  24         RT5025_RSTDELAY1_2S,
  25 };
  26
  27 enum {
  28         RT5025_RSTDELAY2_100MS,
  29         RT5025_RSTDELAY2_500MS,
  30         RT5025_RSTDELAY2_1S,
  31         RT5025_RSTDELAY2_2S,
  32 };
  33
  34 enum {
  35         RT5025_VOFF_2P8V,
  36         RT5025_VOFF_2P9V,
  37         RT5025_VOFF_3P0V,
  38         RT5025_VOFF_3P1V,
  39         RT5025_VOFF_3P2V,
  40         RT5025_VOFF_3P3V,
  41         RT5025_VOFF_3P4V,
  42         RT5025_VOFF_3P5V,
  43 };
  44
  45 enum {
  46         RT5025_STARTIME_100MS,
  47         RT5025_STARTIME_1S,
  48         RT5025_STARTIME_2S,
  49         RT5025_STARTIME_3S,
  50 };
  51
  52 enum {
  53         RT5025_LPRESS_1S,
  54         RT5025_LPRESS_1P5S,
  55         RT5025_LPRESS_2S,
  56         RT5025_LPRESS_2P5S,
  57 };
  58
  59 enum {
  60         RT5025_SHDNPRESS_4S,
  61         RT5025_SHDNPRESS_6S,
  62         RT5025_SHDNPRESS_8S,
  63         RT5025_SHDNPRESS_10S,
  64 };
  65
  66 enum {
  67         RT5025_PGDLY_10MS,
  68         RT5025_PGDLY_50MS,
  69         RT5025_PGDLY_100MS,
  70         RT5025_PGDLY_200MS,
  71 };
  72
  73 enum {
  74         RT5025_SHDNDLY_100MS,
  75         RT5025_SHDNDLY_500MS,
  76         RT5025_SHDNDLY_1S,
  77         RT5025_SHDNDLY_2S,
  78 };
  79
  80 enum {
  81         RT5025_CCCHG_TO_4H,
  82         RT5025_CCCHG_TO_6H,
  83         RT5025_CCCHG_TO_8H,
  84         RT5025_CCCHG_TO_10H,
  85 };
  86
  87 enum {
  88         RT5025_PRECHG_TO_30M,
  89         RT5025_PRECHG_TO_40M,
  90         RT5025_PRECHG_TO_50M,
  91         RT5025_PRECHG_TO_60M,
  92 };
  93
  94 enum {
  95         RT5025_ICC_0P5A,
  96         RT5025_ICC_0P6A,
  97         RT5025_ICC_0P7A,
  98         RT5025_ICC_0P8A,
  99         RT5025_ICC_0P9A,
 100         RT5025_ICC_1A,
 101         RT5025_ICC_1P1A,
 102         RT5025_ICC_1P2A,
 103         RT5025_ICC_1P3A,
 104         RT5025_ICC_1P4A,
 105         RT5025_ICC_1P5A,
 106         RT5025_ICC_1P6A,
 107         RT5025_ICC_1P7A,
 108         RT5025_ICC_1P8A,
 109         RT5025_ICC_1P9A,
 110         RT5025_ICC_2A,
 111         RT5025_ICC_MAX,
 112 };
 113
 114 enum {
 115         RT5025_AICR_100MA,
 116         RT5025_AICR_500MA,
 117         RT5025_AICR_1A,
 118         RT5025_AICR_NOLIMIT,
 119 };
 120
 121 enum {
 122         RT5025_DPM_4V,
 123         RT5025_DPM_4P25V,
 124         RT5025_DPM_4P5V,
 125         RT5025_DPM_DIS,
 126 };
 127
 128 enum {
 129         RT5025_VPREC_2V,
 130         RT5025_VPREC_2P2V,
 131         RT5025_VPREC_2P4V,
 132         RT5025_VPREC_2P6V,
 133         RT5025_VPREC_2P8V,
 134         RT5025_VPREC_3V,
 135         RT5025_VPREC_3V_1,
 136         RT5025_VPREC_3V_2,
 137 };
 138
 139 enum {
 140         RT5025_IEOC_10P,
 141         RT5025_IEOC_20P,
 142 };
 143
 144 enum {
 145         RT5025_IPREC_10P,
 146         RT5025_IPREC_20P,
 147 };
 148
 149 enum {
 150         RT5025_ID_DCDC1,
 151         RT5025_ID_DCDC2,
 152         RT5025_ID_DCDC3,
 153         RT5025_ID_DCDC4,
 154         RT5025_ID_LDO1,
 155         RT5025_ID_LDO2,
 156         RT5025_ID_LDO3,
 157         RT5025_ID_LDO4,
 158         RT5025_ID_LDO5,
 159         RT5025_ID_LDO6,
 160         RT5025_MAX_REGULATOR,
 161 };
 162
 163 struct rt5025_power_data {
 164         union {
 165                 struct {
 166                         unsigned char Resv1:1;
 167                         unsigned char CHGBC_EN:1;
 168                         unsigned char TE:1;
 169                         unsigned char Resv2:1;
 170                         unsigned char CCCHG_TIMEOUT:2;
 171                         unsigned char PRECHG_TIMEOUT:2;
 172                 }bitfield;
 173                 unsigned char val;
 174         }CHGControl2;
 175         union {
 176                 struct {
 177                         unsigned char Resv:2;
 178                         unsigned char VOREG:6;
 179                 }bitfield;
 180                 unsigned char val;
 181         }CHGControl3;
 182         union {
 183                 struct {
 184                         unsigned char Resv:1;
 185                         unsigned char AICR:2;
 186                         unsigned char ICC:4;
 187                         unsigned char CHG_RST:1;
 188                 }bitfield;
 189                 unsigned char val;
 190         }CHGControl4;
 191         union {
 192                 struct {
 193                         unsigned char Resv1:4;
 194                         unsigned char DPM:2;
 195                         unsigned char Resv2:2;
 196                 }bitfield;
 197                 unsigned char val;
 198         }CHGControl5;
 199         union {
 200                 struct {
 201                         unsigned char IPREC:1;
 202                         unsigned char IEOC:1;
 203                         unsigned char VPREC:3;
 204                         unsigned char Resv:3;
 205                 }bitfield;
 206                 unsigned char val;
 207         }CHGControl6;
 208         union {
 209                 struct {
 210                         unsigned char Resv1:4;
 211                         unsigned char CHGC_EN:1;
 212                         unsigned char CHG_DCDC_MODE:1;
 213                         unsigned char BATD_EN:1;
 214                         unsigned char Resv2:1;
 215                 }bitfield;
 216                 unsigned char val;
 217         }CHGControl7;
 218 };
 219
 220 struct rt5025_gpio_data {
 221         unsigned gpio_base;
 222         unsigned irq_base;
 223 };
 224
 225 struct rt5025_misc_data {
 226         union {
 227                 struct {
 228                         unsigned char Action:2;
 229                         unsigned char Delayed1:2;
 230                         unsigned char Delayed2:2;
 231                         unsigned char Resv:2;
 232                 }bitfield;
 233                 unsigned char val;
 234         }RSTCtrl;
 235         union {
 236                 struct {
 237                         unsigned char Resv:5;
 238                         unsigned char VOFF:3;
 239                 }bitfield;
 240                 unsigned char val;
 241         }VSYSCtrl;
 242         union {
 243                 struct {
 244                         unsigned char PG_DLY:2;
 245                         unsigned char SHDN_PRESS:2;
 246                         unsigned char LPRESS_TIME:2;
 247                         unsigned char START_TIME:2;
 248                 }bitfield;
 249                 unsigned char val;
 250         }PwrOnCfg;
 251         union {
 252                 struct {
 253                         unsigned char Resv:4;
 254                         unsigned char SHDN_DLYTIME:2;
 255                         unsigned char SHDN_TIMING:1;
 256                         unsigned char SHDN_CTRL:1;
 257                 }bitfield;
 258                 unsigned char val;
 259         }SHDNCtrl;
 260         union {
 261                 struct {
 262                         unsigned char Resv:2;
 263                         unsigned char OT_ENSHDN:1;
 264                         unsigned char PWRON_ENSHDN:1;
 265                         unsigned char DCDC3LV_ENSHDN:1;
 266                         unsigned char DCDC2LV_ENSHDN:1;
 267                         unsigned char DCDC1LV_ENSHDN:1;
 268                         unsigned char SYSLV_ENSHDN:1;
 269                 }bitfield;
 270                 unsigned char val;
 271         }PwrOffCond;
 272 };
 273
 274 struct rt5025_irq_data {
 275         union {
 276                 struct {
 277                         unsigned char BATABS:1;
 278                         unsigned char Resv1:2;
 279                         unsigned char INUSB_PLUGIN:1;
 280                         unsigned char INUSBOVP:1;
 281                         unsigned char Resv2:1;
 282                         unsigned char INAC_PLUGIN:1;
 283                         unsigned char INACOVP:1;
 284                 }bitfield;
 285                 unsigned char val;
 286         }irq_enable1;
 287         union {
 288                 struct {
 289                         unsigned char CHTERMI:1;
 290                         unsigned char CHBATOVI:1;
 291                         unsigned char CHGOODI_INUSB:1;
 292                         unsigned char CHBADI_INUSB:1;
 293                         unsigned char CHSLPI_INUSB:1;
 294                         unsigned char CHGOODI_INAC:1;
 295                         unsigned char CHBADI_INAC:1;
 296                         unsigned char CHSLPI_INAC:1;
 297                 }bitfield;
 298                 unsigned char val;
 299         }irq_enable2;
 300         union {
 301                 struct {
 302                         unsigned char TIMEOUT_CC:1;
 303                         unsigned char TIMEOUT_PC:1;
 304                         unsigned char Resv:3;
 305                         unsigned char CHVSREGI:1;
 306                         unsigned char CHTREGI:1;
 307                         unsigned char CHRCHGI:1;
 308                 }bitfield;
 309                 unsigned char val;
 310         }irq_enable3;
 311         union {
 312                 struct {
 313                         unsigned char SYSLV:1;
 314                         unsigned char DCDC4LVHV:1;
 315                         unsigned char PWRONLP:1;
 316                         unsigned char PWRONSP:1;
 317                         unsigned char DCDC3LV:1;
 318                         unsigned char DCDC2LV:1;
 319                         unsigned char DCDC1LV:1;
 320                         unsigned char OT:1;
 321                 }bitfield;
 322                 unsigned char val;
 323         }irq_enable4;
 324         union {
 325                 struct {
 326                         unsigned char Resv:1;
 327                         unsigned char GPIO0_IE:1;
 328                         unsigned char GPIO1_IE:1;
 329                         unsigned char GPIO2_IE:1;
 330                         unsigned char RESETB:1;
 331                         unsigned char PWRONF:1;
 332                         unsigned char PWRONR:1;
 333                         unsigned char KPSHDN:1;
 334                 }bitfield;
 335                 unsigned char val;
 336         }irq_enable5;
 337 };
 338
 339 #define CHG_EVENT_INACOVP       (0x80<<16)
 340 #define CHG_EVENT_INAC_PLUGIN   (0x40<<16)
 341 #define CHG_EVENT_INUSBOVP      (0x10<<16)
 342 #define CHG_EVENT_INUSB_PLUGIN  (0x08<<16)
 343 #define CHG_EVENT_BAT_ABS       (0x01<<16)
 344
 345 #define CHG_EVENT_CHSLPI_INAC   (0x80<<8)
 346 #define CHG_EVENT_CHBADI_INAC   (0x40<<8)
 347 #define CHG_EVENT_CHGOODI_INAC  (0x20<<8)
 348 #define CHG_EVENT_CHSLPI_INUSB  (0x10<<8)
 349 #define CHG_EVENT_CHBADI_INUSB  (0x08<<8)
 350 #define CHG_EVENT_CHGOODI_INUSB (0x04<<8)
 351 #define CHG_EVENT_CHBATOVI      (0x02<<8)
 352 #define CHG_EVENT_CHTERMI       (0x01<<8)
 353
 354 #define CHG_EVENT_CHRCHGI       (0x80<<0)
 355 #define CHG_EVENT_CHTREGI       (0x40<<0)
 356 #define CHG_EVENT_CHVSREGI      (0x20<<0)
 357 #define CHG_EVENT_TIMEOUTPC     (0x02<<0)
 358 #define CHG_EVENT_TIMEOUTCC     (0x01<<0)
 359
 360 #define CHARGER_DETECT_MASK     (CHG_EVENT_INAC_PLUGIN | CHG_EVENT_INUSB_PLUGIN | \
 361                                  CHG_EVENT_CHSLPI_INAC | CHG_EVENT_CHSLPI_INUSB | \
 362                                  CHG_EVENT_CHBADI_INAC | CHG_EVENT_CHBADI_INUSB)
 363
 364 #define PWR_EVENT_OTIQ          (0x80<<8)
 365 #define PWR_EVENT_DCDC1LV       (0x40<<8)
 366 #define PWR_EVENT_DCDC2LV       (0x20<<8)
 367 #define PWR_EVENT_DCDC3LV       (0x10<<8)
 368 #define PWR_EVENT_PWRONSP       (0x08<<8)
 369 #define PWR_EVENT_PWRONLP       (0x04<<8)
 370 #define PWR_EVENT_DCDC4LVHV     (0x02<<8)
 371 #define PWR_EVENT_SYSLV         (0x01<<8)
 372
 373 #define PWR_EVENT_KPSHDN        (0x80<<0)
 374 #define PWR_EVNET_PWRONR        (0x40<<0)
 375 #define PWR_EVENT_PWRONF        (0x20<<0)
 376 #define PWR_EVENT_RESETB        (0x10<<0)
 377 #define PWR_EVENT_GPIO2IE       (0x08<<0)
 378 #define PWR_EVENT_GPIO1IE       (0x04<<0)
 379 #define PWR_EVENT_GPIO0IE       (0x02<<0)
 380
 381 struct rt5025_event_callback {
 382         #if 1
 383         void (*charger_event_callback)(uint32_t detected);
 384         void (*power_event_callkback)(uint32_t detected);
 385         #else
 386         void (*over_temperature_callback)(uint8_t detected);
 387         void (*charging_complete_callback)(void);
 388         void (*over_voltage_callback)(uint8_t detected);
 389         void (*under_voltage_callback)(uint8_t detected);
 390         void (*charge_fault_callback)(uint8_t detected);
 391         void (*charge_warning_callback)(uint8_t detected);
 392         #endif
 393 };
 394
 395 struct rt5025_power_info {
 396         struct i2c_client       *i2c;
 397         struct device           *dev;
 398         struct rt5025_gauge_callbacks *event_callback;
 399         struct power_supply     ac;
 400         struct power_supply     usb;
 401         unsigned                ac_online:1;
 402         unsigned                usb_online:1;
 403         unsigned                chg_stat:3;
 404 };
 405
 406 struct rt5025_chip {
 407         struct i2c_client *i2c;
 408         struct workqueue_struct *wq;
 409         struct device *dev;
 410         struct rt5025_power_info *power_info;
 411         int suspend;
 412         int irq;
 413         struct delayed_work delayed_work;
 414         struct mutex io_lock;
 415 };
 416
 417 struct rt5025_platform_data {
 418         struct regulator_init_data* regulator[RT5025_MAX_REGULATOR];
 419         struct rt5025_power_data* power_data;
 420         struct rt5025_gpio_data* gpio_data;
 421         struct rt5025_misc_data* misc_data;
 422         struct rt5025_irq_data* irq_data;
 423         struct rt5025_event_callback *cb;
 424         int (*pre_init)(struct rt5025_chip *rt5025_chip);
 425         /** Called after subdevices are set up */
 426         int (*post_init)(void);
 427         int intr_pin;
 428 };
 429
 430 #ifdef CONFIG_MFD_RT5025_MISC
 431 extern void rt5025_power_off(void);
 432 #endif /* CONFIG_MFD_RT5025_MISC */
 433
 434 #ifdef CONFIG_POWER_RT5025
 435 extern int rt5025_gauge_init(struct rt5025_power_info *);
 436 extern int rt5025_power_passirq_to_gauge(struct rt5025_power_info *);
 437 extern int rt5025_power_charge_detect(struct rt5025_power_info *);
 438 #endif /* CONFIG_POEWR_RT5025 */
 439
 440 extern int rt5025_reg_block_read(struct i2c_client *, int, int, void *);
 441 extern int rt5025_reg_read(struct i2c_client *, int);
 442 extern int rt5025_reg_write(struct i2c_client *, int, unsigned char);
 443 extern int rt5025_assign_bits(struct i2c_client *, int, unsigned char, unsigned char);
 444 extern int rt5025_set_bits(struct i2c_client *, int, unsigned char);
 445 extern int rt5025_clr_bits(struct i2c_client *, int, unsigned char);
 446
 447 extern int rt5025_core_init(struct rt5025_chip *, struct rt5025_platform_data *);
 448 extern int rt5025_core_deinit(struct rt5025_chip *);
 449
 450 #ifdef CONFIG_MFD_RT_SHOW_INFO
 451 #define RTINFO(format, args...) \
 452         printk(KERN_INFO "%s:%s() line-%d: " format, RT5025_DEVICE_NAME,__FUNCTION__,__LINE__, ##args)
 453 #else
 454 #define RTINFO(format,args...)
 455 #endif /* CONFIG_MFD_RT_SHOW_INFO */
 456
 457 #endif /* __LINUX_MFD_RT5025_H */