2 #ifndef __MFD_AIC3262_REGISTERS_H__
3 #define __MFD_AIC3262_REGISTERS_H__
4 /*typedef union aic326x_reg_union {
11 unsigned int aic326x_register_int;
13 #define MAKE_REG(book, page, offset) (unsigned int)((book << 16)|(page << 8)|offset)
15 /* ****************** Book 0 Registers **************************************/
17 /* ****************** Page 0 Registers **************************************/
18 #define AIC3262_PAGE_SEL_REG MAKE_REG(0,0,0)
19 #define AIC3262_RESET_REG MAKE_REG(0,0,1)
20 #define AIC3262_REV_PG_ID MAKE_REG(0,0,2)
21 #define AIC3262_REV_MASK (0b01110000)
22 #define AIC3262_REV_SHIFT 4
23 #define AIC3262_PG_MASK (0b00000111)
24 #define AIC3262_PG_SHIFT 0
25 #define AIC3262_DAC_ADC_CLKIN_REG MAKE_REG(0,0,4)
26 #define AIC3262_PLL_CLKIN_REG MAKE_REG(0,0,5)
27 #define AIC3262_PLL_CLKIN_MASK (0b00111100)
28 #define AIC3262_PLL_CLKIN_SHIFT 2
29 #define AIC3262_PLL_CLKIN_MCLK1 0
30 #define AIC3262_PLL_CLKIN_BCLK1 1
31 #define AIC3262_PLL_CLKIN_GPIO1 2
32 #define AIC3262_PLL_CLKIN_DIN1 3
33 #define AIC3262_PLL_CLKIN_BCLK2 4
34 #define AIC3262_PLL_CLKIN_GPI1 5
35 #define AIC3262_PLL_CLKIN_HF_REF_CLK 6
36 #define AIC3262_PLL_CLKIN_GPIO2 7
37 #define AIC3262_PLL_CLKIN_GPI2 8
38 #define AIC3262_PLL_CLKIN_MCLK2 9
39 #define AIC3262_CLK_VAL_MASK 0x7f
40 #define AIC3262_PLL_CLK_RANGE_REG MAKE_REG(0,0,5)
41 #define AIC3262_PLL_PR_POW_REG MAKE_REG(0,0,6)
42 #define AIC3262_PLL_PVAL_MASK 0x70
43 #define AIC3262_PLL_RVAL_MASK 0x0F
45 #define AIC3262_ENABLE_CLK_MASK 0x80
46 #define AIC3262_ENABLE_CLK 0x80
49 #define AIC3262_PLL_J_REG MAKE_REG(0,0,7)
50 #define AIC3262_JVAL_MASK 0x3f
51 #define AIC3262_PLL_D_MSB MAKE_REG(0,0,8)
52 #define AIC3262_DVAL_MSB_MASK 0xf
53 #define AIC3262_DVAL_LSB_MASK 0xff
54 #define AIC3262_PLL_D_LSB MAKE_REG(0,0,9)
55 #define AIC3262_PLL_CKIN_DIV MAKE_REG(0,0,10)
57 #define AIC3262_NDAC_DIV_POW_REG MAKE_REG(0,0,11)
58 #define AIC3262_MDAC_DIV_POW_REG MAKE_REG(0,0,12)
59 #define AIC3262_DOSR_MSB_REG MAKE_REG(0,0,13)
60 #define AIC3262_DOSR_MSB_MASK 0x3
61 #define AIC3262_DOSR_LSB_REG MAKE_REG(0,0,14)
62 #define AIC3262_DOSR_LSB_MASK 0xFF
64 #define AIC3262_NADC_DIV_POW_REG MAKE_REG(0,0,18)
65 #define AIC3262_MADC_DIV_POW_REG MAKE_REG(0,0,19)
66 #define AIC3262_AOSR_REG MAKE_REG(0,0,20)
67 #define AIC3262_CLKOUT_MUX MAKE_REG(0,0,21)
68 #define AIC3262_CLKOUT_MDIV_VAL MAKE_REG(0,0,22)
69 #define AIC3262_TIMER_REG MAKE_REG(0,0,23)
71 #define AIC3262_LF_CLK_CNTL MAKE_REG(0,0,24)
72 #define AIC3262_HF_CLK_CNTL_R1 MAKE_REG(0,0,25)
73 #define AIC3262_HF_CLK_CNTL_R2 MAKE_REG(0,0,26)
74 #define AIC3262_HF_CLK_CNTL_R3 MAKE_REG(0,0,27)
75 #define AIC3262_HF_CLK_CNTL_R4 MAKE_REG(0,0,28)
76 #define AIC3262_HF_CLK_TRIM_R1 MAKE_REG(0,0,29)
77 #define AIC3262_HF_CLK_TRIM_R2 MAKE_REG(0,0,30)
78 #define AIC3262_HF_CLK_TRIM_R3 MAKE_REG(0,0,31)
79 #define AIC3262_HF_CLK_TRIM_R4 MAKE_REG(0,0,32)
80 #define AIC3262_LDAC_POWER_MASK 0x80
81 #define AIC3262_RDAC_POWER_MASK 0x08
82 #define AIC3262_DAC_FLAG MAKE_REG(0,0,37)
83 #define AIC3262_ADC_FLAG MAKE_REG(0,0,36)
84 #define AIC3262_JACK_WITH_STEREO_HS (0b00000010)
85 #define AIC3262_JACK_WITH_MIC (0b00110000)
86 #define AIC3262_HEADSET_NOT_INSERTED (0b00000011)
88 #define AIC3262_INT_STICKY_FLAG1 MAKE_REG(0,0,42)
89 #define AIC3262_LEFT_DAC_OVERFLOW_INT 0x80
90 #define AIC3262_RIGHT_DAC_OVERFLOW_INT 0x40
91 #define AIC3262_MINIDSP_D_BARREL_SHIFT_OVERFLOW_INT 0x20
92 #define AIC3262_LEFT_ADC_OVERFLOW_INT 0x08
93 #define AIC3262_RIGHT_ADC_OVERFLOW_INT 0x04
94 #define AIC3262_MINIDSP_A_BARREL_SHIFT_OVERFLOW_INT 0x02
95 #define AIC3262_INT_STICKY_FLAG2 MAKE_REG(0,0,44)
96 #define AIC3262_LEFT_OUTPUT_DRIVER_OVERCURRENT_INT 0x80
97 #define AIC3262_RIGHT_OUTPUT_DRIVER_OVERCURRENT_INT 0x40
98 #define AIC3262_BUTTON_PRESS_INT 0x20
99 #define AIC3262_HEADSET_PLUG_UNPLUG_INT 0x10
100 #define AIC3262_LEFT_DRC_THRES_INT 0x08
101 #define AIC3262_RIGHT_DRC_THRES_INT 0x04
102 #define AIC3262_MINIDSP_D_STD_INT 0x02
103 #define AIC3262_RIGHT_DRC_AUX_INT 0x01
104 #define AIC3262_INT_STICKY_FLAG3 MAKE_REG(0,0,45)
105 #define AIC3262_SPK_OVER_CURRENT_INT 0x80
106 #define AIC3262_LEFT_AGC_NOISE_INT 0x40
107 #define AIC3262_RIGHT_AGC_NOISE_INT 0x20
108 #define AIC3262_INT1_CNTL MAKE_REG(0,0,48)
109 #define AIC3262_HEADSET_IN_MASK 0x80
110 #define AIC3262_BUTTON_PRESS_MASK 0x40
111 #define AIC3262_DAC_DRC_THRES_MASK 0x20
112 #define AIC3262_AGC_NOISE_MASK 0x10
113 #define AIC3262_OVER_CURRENT_MASK 0x08
114 #define AIC3262_OVERFLOW_MASK 0x04
115 #define AIC3262_SPK_OVERCURRENT_MASK 0x02
116 #define AIC3262_INT2_CNTL MAKE_REG(0,0,49)
117 #define AIC3262_INT_FMT MAKE_REG(0,0,51)
119 #define AIC3262_DAC_PRB MAKE_REG(0,0,60)
120 #define AIC3262_ADC_PRB MAKE_REG(0,0,61)
121 #define AIC3262_PASI_DAC_DP_SETUP MAKE_REG(0,0,63)
123 #define AIC3262_DAC_MVOL_CONF MAKE_REG(0,0,64)
124 #define AIC3262_DAC_LR_MUTE_MASK 0xc
125 #define AIC3262_DAC_LR_MUTE 0xc
127 #define AIC3262_DAC_LVOL MAKE_REG(0,0,65)
128 #define AIC3262_DAC_RVOL MAKE_REG(0,0,66)
129 #define AIC3262_HP_DETECT MAKE_REG(0,0,67)
130 #define AIC3262_DRC_CNTL_R1 MAKE_REG(0,0,68)
131 #define AIC3262_DRC_CNTL_R2 MAKE_REG(0,0,69)
132 #define AIC3262_DRC_CNTL_R3 MAKE_REG(0,0,70)
133 #define AIC3262_BEEP_CNTL_R1 MAKE_REG(0,0,71)
134 #define AIC3262_BEEP_CNTL_R2 MAKE_REG(0,0,72)
136 #define AIC3262_ADC_CHANNEL_POW MAKE_REG(0,0,81)
137 #define AIC3262_ADC_FINE_GAIN MAKE_REG(0,0,82)
138 #define AIC3262_LADC_VOL MAKE_REG(0,0,83)
139 #define AIC3262_RADC_VOL MAKE_REG(0,0,84)
140 #define AIC3262_ADC_PHASE MAKE_REG(0,0,85)
142 #define AIC3262_LAGC_CNTL MAKE_REG(0,0,86)
143 #define AIC3262_LAGC_CNTL_R2 MAKE_REG(0,0,87)
144 #define AIC3262_LAGC_CNTL_R3 MAKE_REG(0,0,88)
145 #define AIC3262_LAGC_CNTL_R4 MAKE_REG(0,0,89)
146 #define AIC3262_LAGC_CNTL_R5 MAKE_REG(0,0,90)
147 #define AIC3262_LAGC_CNTL_R6 MAKE_REG(0,0,91)
148 #define AIC3262_LAGC_CNTL_R7 MAKE_REG(0,0,92)
149 #define AIC3262_LAGC_CNTL_R8 MAKE_REG(0,0,93)
151 #define AIC3262_RAGC_CNTL MAKE_REG(0,0,94)
152 #define AIC3262_RAGC_CNTL_R2 MAKE_REG(0,0,95)
153 #define AIC3262_RAGC_CNTL_R3 MAKE_REG(0,0,96)
154 #define AIC3262_RAGC_CNTL_R4 MAKE_REG(0,0,97)
155 #define AIC3262_RAGC_CNTL_R5 MAKE_REG(0,0,98)
156 #define AIC3262_RAGC_CNTL_R6 MAKE_REG(0,0,99)
157 #define AIC3262_RAGC_CNTL_R7 MAKE_REG(0,0,100)
158 #define AIC3262_RAGC_CNTL_R8 MAKE_REG(0,0,101)
159 #define AIC3262_MINIDSP_ACCESS_CTRL MAKE_REG(0,0,121)
160 /* ****************** Page 1 Registers **************************************/
161 #define AIC3262_PAGE_1 128
163 #define AIC3262_POWER_CONF MAKE_REG(0,1, 1)
165 #define AIC3262_AVDD_TO_DVDD_MASK (0b00001000)
166 #define AIC3262_AVDD_TO_DVDD 0x8
167 #define AIC3262_EXT_ANALOG_SUPPLY_MASK (0b00000100)
168 #define AIC3262_EXT_ANALOG_SUPPLY_OFF 0x4
170 #define AIC3262_LDAC_PTM MAKE_REG(0,1, 3)
171 #define AIC3262_RDAC_PTM MAKE_REG(0,1, 4)
172 #define AIC3262_CM_REG MAKE_REG(0,1, 8)
173 #define AIC3262_HP_CTL MAKE_REG(0,1, 9)
174 #define AIC3262_HP_DEPOP MAKE_REG(0,1, 11)
175 #define AIC3262_RECV_DEPOP MAKE_REG(0,1, 12)
176 #define AIC3262_MA_CNTL MAKE_REG(0,1, 17)
177 #define AIC3262_LADC_PGA_MAL_VOL MAKE_REG(0,1, 18)
178 #define AIC3262_RADC_PGA_MAR_VOL MAKE_REG(0,1, 19)
181 #define AIC3262_LINE_AMP_CNTL_R1 MAKE_REG(0,1, 22)
182 #define AIC3262_LINE_AMP_CNTL_R2 MAKE_REG(0,1, 23)
184 #define AIC3262_HP_AMP_CNTL_R1 MAKE_REG(0,1, 27)
185 #define AIC3262_HP_AMP_CNTL_R2 MAKE_REG(0,1, 28)
186 #define AIC3262_HP_AMP_CNTL_R3 MAKE_REG(0,1, 29)
188 #define AIC3262_HPL_VOL MAKE_REG(0,1, 31)
189 #define AIC3262_HPR_VOL MAKE_REG(0,1, 32)
190 #define AIC3262_INT1_SEL_L MAKE_REG(0,1, 34)
191 #define AIC3262_CHARGE_PUMP_CNTL MAKE_REG(0,1, 35)
192 #define AIC3262_RAMP_CNTL_R1 MAKE_REG(0,1, 36)
193 #define AIC3262_RAMP_CNTL_R2 MAKE_REG(0,1, 37)
194 #define AIC3262_IN1L_SEL_RM MAKE_REG(0,1, 38)
195 #define AIC3262_IN1R_SEL_RM MAKE_REG(0,1, 39)
196 #define AIC3262_REC_AMP_CNTL_R5 MAKE_REG(0,1, 40)
197 #define AIC3262_RAMPR_VOL MAKE_REG(0,1, 41)
198 #define AIC3262_RAMP_TIME_CNTL MAKE_REG(0,1, 42)
199 #define AIC3262_SPK_AMP_CNTL_R1 MAKE_REG(0,1, 45)
200 #define AIC3262_SPK_AMP_CNTL_R2 MAKE_REG(0,1, 46)
201 #define AIC3262_SPK_AMP_CNTL_R3 MAKE_REG(0,1, 47)
202 #define AIC3262_SPK_AMP_CNTL_R4 MAKE_REG(0,1, 48)
203 #define AIC3262_MIC_BIAS_CNTL MAKE_REG(0,1, 51)
205 #define AIC3262_LMIC_PGA_PIN MAKE_REG(0,1, 52)
206 #define AIC3262_LMIC_PGA_PM_IN4 MAKE_REG(0,1, 53)
207 #define AIC3262_LMIC_PGA_MIN MAKE_REG(0,1, 54)
208 #define AIC3262_RMIC_PGA_PIN MAKE_REG(0,1, 55)
209 #define AIC3262_RMIC_PGA_PM_IN4 MAKE_REG(0,1, 56)
210 #define AIC3262_RMIC_PGA_MIN MAKE_REG(0,1, 57)
211 #define AIC3262_HP_FLAG MAKE_REG(0,1,66)
212 #define AIC3262_SPKL_POWER_MASK 0x2
213 #define AIC3262_SPKR_POWER_MASK 0x1
214 #define AIC3262_HPL_POWER_MASK 0x20
215 #define AIC3262_HPR_POWER_MASK 0x10
216 /* MIC PGA Gain Registers */
217 #define AIC3262_MICL_PGA MAKE_REG(0,1, 59)
218 #define AIC3262_MICR_PGA MAKE_REG(0,1, 60)
219 #define AIC3262_HEADSET_TUNING1_REG MAKE_REG(0,1, 119)
220 #define AIC3262_HEADSET_DETECTOR_PULSE_MASK (0b11000000)
221 #define AIC3262_HEADSET_DETECTOR_PULSE_RESET (0B10000000)
222 #define AIC3262_MIC_PWR_DLY MAKE_REG(0,1, 121)
223 #define AIC3262_REF_PWR_DLY MAKE_REG(0,1, 122)
224 #define AIC3262_CHIP_REF_PWR_ON_MASK 0x4
225 #define AIC3262_CHIP_REF_PWR_ON 0x4
226 /* ****************** Page 4 Registers **************************************/
227 #define AIC3262_PAGE_4 512
228 #define AIC3262_ASI1_BUS_FMT MAKE_REG(0,4, 1)
229 #define AIC3262_ASI_SELECTION_MASK (0b1100000)
230 #define AIC3262_ASI_DATA_WORD_LENGTH_MASK (0b0011000)
231 #define AIC3262_ASI_BCLK_N_MASK (0b01111111)
232 #define AIC3262_ASI1_LCH_OFFSET MAKE_REG(0,4, 2)
233 #define AIC3262_ASI1_RCH_OFFSET MAKE_REG(0,4, 3)
234 #define AIC3262_ASI1_CHNL_SETUP MAKE_REG(0,4, 4)
235 #define AIC3262_ASI1_MULTI_CH_SETUP_R1 MAKE_REG(0,4, 5)
236 #define AIC3262_ASI1_MULTI_CH_SETUP_R2 MAKE_REG(0,4, 6)
237 #define AIC3262_ASI1_ADC_INPUT_CNTL MAKE_REG(0,4, 7)
238 #define AIC3262_ASI1_DAC_OUT_CNTL MAKE_REG(0,4, 8)
239 #define AIC3262_ASI1_ADC_OUT_TRISTATE MAKE_REG(0,4, 9)
240 #define AIC3262_ASI1_BWCLK_CNTL_REG MAKE_REG(0,4, 10)
241 #define AIC3262_ASI1_BCLK_N_CNTL MAKE_REG(0,4, 11)
242 #define AIC3262_ASI1_BCLK_N MAKE_REG(0,4, 12)
243 #define AIC3262_ASI1_WCLK_N MAKE_REG(0,4, 13)
244 #define AIC3262_ASI1_BWCLK_OUT_CNTL MAKE_REG(0,4, 14)
245 #define AIC3262_ASI1_DOUT_CNTL MAKE_REG(0,4, 15)
246 #define AIC3262_ASI2_BUS_FMT MAKE_REG(0,4, 17)
247 #define AIC3262_ASI2_LCH_OFFSET MAKE_REG(0,4, 18)
248 #define AIC3262_ASI2_ADC_INPUT_CNTL MAKE_REG(0,4, 23)
249 #define AIC3262_ASI2_DAC_OUT_CNTL MAKE_REG(0,4, 24)
250 #define AIC3262_ASI2_BWCLK_CNTL_REG MAKE_REG(0,4, 26)
251 #define AIC3262_ASI2_BCLK_N_CNTL MAKE_REG(0,4, 27)
252 #define AIC3262_ASI2_BCLK_N MAKE_REG(0,4, 28)
253 #define AIC3262_ASI2_WCLK_N MAKE_REG(0,4, 29)
254 #define AIC3262_ASI2_BWCLK_OUT_CNTL MAKE_REG(0,4, 30)
255 #define AIC3262_ASI2_DOUT_CNTL MAKE_REG(0,4, 31)
256 #define AIC3262_ASI3_BUS_FMT MAKE_REG(0,4, 33)
257 #define AIC3262_ASI3_LCH_OFFSET MAKE_REG(0,4, 34)
258 #define AIC3262_ASI3_ADC_INPUT_CNTL MAKE_REG(0,4, 39)
259 #define AIC3262_ASI3_DAC_OUT_CNTL MAKE_REG(0,4, 40)
260 #define AIC3262_ASI3_BWCLK_CNTL_REG MAKE_REG(0,4, 42)
261 #define AIC3262_ASI3_BCLK_N_CNTL MAKE_REG(0,4, 43)
262 #define AIC3262_ASI3_BCLK_N MAKE_REG(0,4, 44)
263 #define AIC3262_ASI3_WCLK_N MAKE_REG(0,4, 45)
264 #define AIC3262_ASI3_BWCLK_OUT_CNTL MAKE_REG(0,4, 46)
265 #define AIC3262_ASI3_DOUT_CNTL MAKE_REG(0,4, 47)
266 #define AIC3262_DMIC_INPUT_CNTL MAKE_REG(0,4, 101)
267 #define AIC3262_GPIO1_IO_CNTL MAKE_REG(0,4, 86)
268 #define AIC3262_GPIO_D6_D2 (0b01111100)
269 #define AIC3262_GPIO_D2_SHIFT (2)
270 #define AIC3262_GPIO_D1_SHIFT (1)
271 #define AIC3262_GPIO_D4_SHIFT (4)
272 #define AIC3262_GPIO2_IO_CNTL MAKE_REG(0,4, 87)
273 #define AIC3262_GPI1_EN MAKE_REG(0,4, 91)
274 #define AIC3262_GPI1_D2_D1 (0b00000110)
275 #define AIC3262_GPI2_D5_D4 (0b00110000)
276 #define AIC3262_GPI2_EN MAKE_REG(0, 4, 92)
277 #define AIC3262_GPO1_OUT_CNTL MAKE_REG(0, 4, 96)
278 #define AIC3262_GPO1_D4_D1 (0b00011110)
279 #define AIC3262_DMIC_INPUT_CONTROL MAKE_REG(0, 4, 101)
280 #define AIC3262_DMIC_CONFIGURE_MASK (0b00011111)
281 #define AIC3262_DMIC_CONFIGURE_SHIFT (0)
282 #define AIC3262_MINIDSP_DATA_PORT_CNTL MAKE_REG(0, 4, 118)
284 #define AIC3262_DAC_ASI_LR_UNMUTE_MASK 0x50
285 #define AIC3262_DAC_ASI_LR_UNMUTE 0x50
286 #define AIC3262_WCLK_BCLK_MASTER_MASK (0b00100110)
287 #define AIC3262_WCLK_MASTER_MASK (0b00100000)
288 #define AIC3262_BCLK_MASTER_MASK (0b00000100)
289 #define AIC3262_BCLK_OFFSET_MASK (0b11111111)
290 #define AIC3262_ASI_INTERFACE_MASK (0b11100000)
291 #define AIC3262_WCLK_OUT_MASK (0b00100000)
292 #define AIC3262_BCLK_OUT_MASK (0b00000100)
293 #define AIC3262_BCLK_INV_MASK (0b00000010)
295 #define AIC3262_ADC_ADAPTIVE_CRAM_REG MAKE_REG(40,0,1)
296 #define AIC3262_DAC_ADAPTIVE_BANK1_REG MAKE_REG(80,0,1)
297 #define AIC3262_DAC_ADAPTIVE_BANK2_REG MAKE_REG(82,0,1)
298 #define AIC3262_ADC_DATAPATH_SETUP MAKE_REG(0,0,81)
299 #define AIC3262_DAC_DATAPATH_SETUP MAKE_REG(0,0,63)