2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/types.h>
37 #include <uapi/linux/if_ether.h>
39 #include <linux/mlx4/device.h>
40 #include <linux/mlx4/doorbell.h>
44 __be32 immed_rss_invalid;
67 u8 vendor_err_syndrome;
75 __be32 immed_rss_invalid;
90 MLX4_CQE_L2_TUNNEL_IPOK = 1 << 31,
91 MLX4_CQE_VLAN_PRESENT_MASK = 1 << 29,
92 MLX4_CQE_L2_TUNNEL = 1 << 27,
93 MLX4_CQE_L2_TUNNEL_CSUM = 1 << 26,
94 MLX4_CQE_L2_TUNNEL_IPV4 = 1 << 25,
96 MLX4_CQE_QPN_MASK = 0xffffff,
97 MLX4_CQE_VID_MASK = 0xfff,
101 MLX4_CQE_OWNER_MASK = 0x80,
102 MLX4_CQE_IS_SEND_MASK = 0x40,
103 MLX4_CQE_OPCODE_MASK = 0x1f
107 MLX4_CQE_SYNDROME_LOCAL_LENGTH_ERR = 0x01,
108 MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR = 0x02,
109 MLX4_CQE_SYNDROME_LOCAL_PROT_ERR = 0x04,
110 MLX4_CQE_SYNDROME_WR_FLUSH_ERR = 0x05,
111 MLX4_CQE_SYNDROME_MW_BIND_ERR = 0x06,
112 MLX4_CQE_SYNDROME_BAD_RESP_ERR = 0x10,
113 MLX4_CQE_SYNDROME_LOCAL_ACCESS_ERR = 0x11,
114 MLX4_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR = 0x12,
115 MLX4_CQE_SYNDROME_REMOTE_ACCESS_ERR = 0x13,
116 MLX4_CQE_SYNDROME_REMOTE_OP_ERR = 0x14,
117 MLX4_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR = 0x15,
118 MLX4_CQE_SYNDROME_RNR_RETRY_EXC_ERR = 0x16,
119 MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR = 0x22,
123 MLX4_CQE_STATUS_IPV4 = 1 << 6,
124 MLX4_CQE_STATUS_IPV4F = 1 << 7,
125 MLX4_CQE_STATUS_IPV6 = 1 << 8,
126 MLX4_CQE_STATUS_IPV4OPT = 1 << 9,
127 MLX4_CQE_STATUS_TCP = 1 << 10,
128 MLX4_CQE_STATUS_UDP = 1 << 11,
129 MLX4_CQE_STATUS_IPOK = 1 << 12,
134 MLX4_CQE_SNAP = 1 << 1,
135 MLX4_CQE_BAD_FCS = 1 << 4,
138 static inline void mlx4_cq_arm(struct mlx4_cq *cq, u32 cmd,
139 void __iomem *uar_page,
140 spinlock_t *doorbell_lock)
147 ci = cq->cons_index & 0xffffff;
149 *cq->arm_db = cpu_to_be32(sn << 28 | cmd | ci);
152 * Make sure that the doorbell record in host memory is
153 * written before ringing the doorbell via PCI MMIO.
157 doorbell[0] = cpu_to_be32(sn << 28 | cmd | cq->cqn);
158 doorbell[1] = cpu_to_be32(ci);
160 mlx4_write64(doorbell, uar_page + MLX4_CQ_DOORBELL, doorbell_lock);
163 static inline void mlx4_cq_set_ci(struct mlx4_cq *cq)
165 *cq->set_ci_db = cpu_to_be32(cq->cons_index & 0xffffff);
169 MLX4_CQ_DB_REQ_NOT_SOL = 1 << 24,
170 MLX4_CQ_DB_REQ_NOT = 2 << 24
173 int mlx4_cq_modify(struct mlx4_dev *dev, struct mlx4_cq *cq,
174 u16 count, u16 period);
175 int mlx4_cq_resize(struct mlx4_dev *dev, struct mlx4_cq *cq,
176 int entries, struct mlx4_mtt *mtt);
178 #endif /* MLX4_CQ_H */