2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/pci.h>
37 #include <linux/completion.h>
38 #include <linux/radix-tree.h>
40 #include <linux/atomic.h>
42 #define MAX_MSIX_P_PORT 17
44 #define MSIX_LEGACY_SZ 4
45 #define MIN_MSIX_P_PORT 5
48 MLX4_FLAG_MSI_X = 1 << 0,
49 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
50 MLX4_FLAG_MASTER = 1 << 2,
51 MLX4_FLAG_SLAVE = 1 << 3,
52 MLX4_FLAG_SRIOV = 1 << 4,
60 MLX4_BOARD_ID_LEN = 64
67 MLX4_MFUNC_EQ_NUM = 4,
68 MLX4_MFUNC_MAX_EQES = 8,
69 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
73 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
74 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
75 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
76 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
77 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
78 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
79 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
80 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
81 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
82 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
83 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
84 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
85 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
86 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
87 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
88 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
89 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
90 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
91 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
92 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
93 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
94 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
95 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
96 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
97 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48
100 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
103 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
107 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
108 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
109 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
110 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
111 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
115 MLX4_EVENT_TYPE_COMP = 0x00,
116 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
117 MLX4_EVENT_TYPE_COMM_EST = 0x02,
118 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
119 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
120 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
121 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
122 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
123 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
124 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
125 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
126 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
127 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
128 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
129 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
130 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
131 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
132 MLX4_EVENT_TYPE_CMD = 0x0a,
133 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
134 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
135 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
136 MLX4_EVENT_TYPE_NONE = 0xff,
140 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
141 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
145 MLX4_PERM_LOCAL_READ = 1 << 10,
146 MLX4_PERM_LOCAL_WRITE = 1 << 11,
147 MLX4_PERM_REMOTE_READ = 1 << 12,
148 MLX4_PERM_REMOTE_WRITE = 1 << 13,
149 MLX4_PERM_ATOMIC = 1 << 14
153 MLX4_OPCODE_NOP = 0x00,
154 MLX4_OPCODE_SEND_INVAL = 0x01,
155 MLX4_OPCODE_RDMA_WRITE = 0x08,
156 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
157 MLX4_OPCODE_SEND = 0x0a,
158 MLX4_OPCODE_SEND_IMM = 0x0b,
159 MLX4_OPCODE_LSO = 0x0e,
160 MLX4_OPCODE_RDMA_READ = 0x10,
161 MLX4_OPCODE_ATOMIC_CS = 0x11,
162 MLX4_OPCODE_ATOMIC_FA = 0x12,
163 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
164 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
165 MLX4_OPCODE_BIND_MW = 0x18,
166 MLX4_OPCODE_FMR = 0x19,
167 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
168 MLX4_OPCODE_CONFIG_CMD = 0x1f,
170 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
171 MLX4_RECV_OPCODE_SEND = 0x01,
172 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
173 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
175 MLX4_CQE_OPCODE_ERROR = 0x1e,
176 MLX4_CQE_OPCODE_RESIZE = 0x16,
180 MLX4_STAT_RATE_OFFSET = 5
184 MLX4_PROT_IB_IPV6 = 0,
191 MLX4_MTT_FLAG_PRESENT = 1
194 enum mlx4_qp_region {
195 MLX4_QP_REGION_FW = 0,
196 MLX4_QP_REGION_ETH_ADDR,
197 MLX4_QP_REGION_FC_ADDR,
198 MLX4_QP_REGION_FC_EXCH,
202 enum mlx4_port_type {
203 MLX4_PORT_TYPE_NONE = 0,
204 MLX4_PORT_TYPE_IB = 1,
205 MLX4_PORT_TYPE_ETH = 2,
206 MLX4_PORT_TYPE_AUTO = 3
209 enum mlx4_special_vlan_idx {
210 MLX4_NO_VLAN_IDX = 0,
215 enum mlx4_steer_type {
222 MLX4_NUM_FEXCH = 64 * 1024,
226 MLX4_MAX_FAST_REG_PAGES = 511,
229 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
231 return (major << 32) | (minor << 16) | subminor;
238 int vl_cap[MLX4_MAX_PORTS + 1];
239 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
240 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
241 u64 def_mac[MLX4_MAX_PORTS + 1];
242 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
243 int gid_table_len[MLX4_MAX_PORTS + 1];
244 int pkey_table_len[MLX4_MAX_PORTS + 1];
245 int trans_type[MLX4_MAX_PORTS + 1];
246 int vendor_oui[MLX4_MAX_PORTS + 1];
247 int wavelength[MLX4_MAX_PORTS + 1];
248 u64 trans_code[MLX4_MAX_PORTS + 1];
249 int local_ca_ack_delay;
252 int bf_regs_per_page;
259 int max_qp_init_rdma;
260 int max_qp_dest_rdma;
271 int num_comp_vectors;
276 int fmr_reserved_mtts;
294 u16 stat_rate_support;
295 u8 port_width_cap[MLX4_MAX_PORTS + 1];
297 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
299 int reserved_qps_base[MLX4_NUM_QP_REGION];
303 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
304 u8 supported_type[MLX4_MAX_PORTS + 1];
305 u32 port_mask[MLX4_MAX_PORTS + 1];
306 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
308 u8 ext_port_cap[MLX4_MAX_PORTS + 1];
311 struct mlx4_buf_list {
317 struct mlx4_buf_list direct;
318 struct mlx4_buf_list *page_list;
331 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
334 struct mlx4_db_pgdir {
335 struct list_head list;
336 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
337 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
338 unsigned long *bits[2];
343 struct mlx4_ib_user_db_page;
348 struct mlx4_db_pgdir *pgdir;
349 struct mlx4_ib_user_db_page *user_page;
356 struct mlx4_hwq_resources {
374 struct mlx4_mpt_entry *mpt;
376 dma_addr_t dma_handle;
386 struct list_head bf_list;
387 unsigned free_bf_bmap;
389 void __iomem *bf_map;
393 unsigned long offset;
395 struct mlx4_uar *uar;
400 void (*comp) (struct mlx4_cq *);
401 void (*event) (struct mlx4_cq *, enum mlx4_event);
403 struct mlx4_uar *uar;
415 struct completion free;
419 void (*event) (struct mlx4_qp *, enum mlx4_event);
424 struct completion free;
428 void (*event) (struct mlx4_srq *, enum mlx4_event);
436 struct completion free;
448 __be32 sl_tclass_flowlabel;
461 __be32 sl_tclass_flowlabel;
470 struct mlx4_eth_av eth;
473 struct mlx4_counter {
485 struct pci_dev *pdev;
487 unsigned long num_slaves;
488 struct mlx4_caps caps;
489 struct radix_tree_root qp_table_tree;
491 char board_id[MLX4_BOARD_ID_LEN];
494 struct mlx4_init_port_param {
508 #define mlx4_foreach_port(port, dev, type) \
509 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
510 if ((type) == (dev)->caps.port_mask[(port)])
512 #define mlx4_foreach_ib_transport_port(port, dev) \
513 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
514 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
515 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
517 static inline int mlx4_is_master(struct mlx4_dev *dev)
519 return dev->flags & MLX4_FLAG_MASTER;
522 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
524 return (qpn < dev->caps.sqp_start + 8);
527 static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
529 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
532 static inline int mlx4_is_slave(struct mlx4_dev *dev)
534 return dev->flags & MLX4_FLAG_SLAVE;
537 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
538 struct mlx4_buf *buf);
539 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
540 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
542 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
543 return buf->direct.buf + offset;
545 return buf->page_list[offset >> PAGE_SHIFT].buf +
546 (offset & (PAGE_SIZE - 1));
549 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
550 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
551 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
552 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
554 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
555 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
556 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf);
557 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
559 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
560 struct mlx4_mtt *mtt);
561 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
562 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
564 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
565 int npages, int page_shift, struct mlx4_mr *mr);
566 void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
567 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
568 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
569 int start_index, int npages, u64 *page_list);
570 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
571 struct mlx4_buf *buf);
573 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
574 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
576 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
577 int size, int max_direct);
578 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
581 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
582 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
583 unsigned vector, int collapsed);
584 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
586 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
587 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
589 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
590 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
592 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
593 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
594 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
595 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
596 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
598 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
599 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
601 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
602 int block_mcast_loopback, enum mlx4_protocol protocol);
603 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
604 enum mlx4_protocol protocol);
605 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
606 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
607 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
608 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
609 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
611 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *qpn, u8 wrap);
612 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, int qpn);
613 int mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac, u8 wrap);
615 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
616 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
617 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);
619 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
620 int npages, u64 iova, u32 *lkey, u32 *rkey);
621 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
622 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
623 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
624 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
625 u32 *lkey, u32 *rkey);
626 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
627 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
628 int mlx4_test_interrupts(struct mlx4_dev *dev);
629 int mlx4_assign_eq(struct mlx4_dev *dev, char* name , int* vector);
630 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
632 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
633 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
635 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
636 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
638 #endif /* MLX4_DEVICE_H */