2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/if_ether.h>
37 #include <linux/pci.h>
38 #include <linux/completion.h>
39 #include <linux/radix-tree.h>
40 #include <linux/cpu_rmap.h>
41 #include <linux/crash_dump.h>
43 #include <linux/atomic.h>
45 #include <linux/timecounter.h>
47 #define MAX_MSIX_P_PORT 17
49 #define MSIX_LEGACY_SZ 4
50 #define MIN_MSIX_P_PORT 5
54 #define MLX4_MAX_100M_UNITS_VAL 255 /*
55 * work around: can't set values
56 * greater then this value when
57 * using 100 Mbps units.
59 #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */
60 #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */
61 #define MLX4_RATELIMIT_DEFAULT 0x00ff
63 #define MLX4_ROCE_MAX_GIDS 128
64 #define MLX4_ROCE_PF_GIDS 16
67 MLX4_FLAG_MSI_X = 1 << 0,
68 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
69 MLX4_FLAG_MASTER = 1 << 2,
70 MLX4_FLAG_SLAVE = 1 << 3,
71 MLX4_FLAG_SRIOV = 1 << 4,
72 MLX4_FLAG_OLD_REG_MAC = 1 << 6,
73 MLX4_FLAG_BONDED = 1 << 7
77 MLX4_PORT_CAP_IS_SM = 1 << 1,
78 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
83 MLX4_MAX_PORT_PKEYS = 128
86 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
87 * These qkeys must not be allowed for general use. This is a 64k range,
88 * and to test for violation, we use the mask (protect against future chg).
90 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
91 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
94 MLX4_BOARD_ID_LEN = 64
99 MLX4_MAX_NUM_VF = 126,
100 MLX4_MAX_NUM_VF_P_PORT = 64,
101 MLX4_MFUNC_MAX = 128,
102 MLX4_MAX_EQ_NUM = 1024,
103 MLX4_MFUNC_EQ_NUM = 4,
104 MLX4_MFUNC_MAX_EQES = 8,
105 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
108 /* Driver supports 3 diffrent device methods to manage traffic steering:
109 * -device managed - High level API for ib and eth flow steering. FW is
110 * managing flow steering tables.
111 * - B0 steering mode - Common low level API for ib and (if supported) eth.
112 * - A0 steering mode - Limited low level API for eth. In case of IB,
116 MLX4_STEERING_MODE_A0,
117 MLX4_STEERING_MODE_B0,
118 MLX4_STEERING_MODE_DEVICE_MANAGED
122 MLX4_STEERING_DMFS_A0_DEFAULT,
123 MLX4_STEERING_DMFS_A0_DYNAMIC,
124 MLX4_STEERING_DMFS_A0_STATIC,
125 MLX4_STEERING_DMFS_A0_DISABLE,
126 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED
129 static inline const char *mlx4_steering_mode_str(int steering_mode)
131 switch (steering_mode) {
132 case MLX4_STEERING_MODE_A0:
133 return "A0 steering";
135 case MLX4_STEERING_MODE_B0:
136 return "B0 steering";
138 case MLX4_STEERING_MODE_DEVICE_MANAGED:
139 return "Device managed flow steering";
142 return "Unrecognize steering mode";
147 MLX4_TUNNEL_OFFLOAD_MODE_NONE,
148 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
152 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
153 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
154 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
155 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
156 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
157 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
158 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
159 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
160 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
161 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
162 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
163 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
164 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
165 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
166 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
167 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
168 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
169 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
170 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
171 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
172 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
173 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
174 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
175 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
176 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
177 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53,
178 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
179 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
180 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
181 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62
185 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
186 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
187 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
188 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
189 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4,
190 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5,
191 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6,
192 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7,
193 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8,
194 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9,
195 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10,
196 MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11,
197 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12,
198 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13,
199 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14,
200 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15,
201 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16,
202 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17,
203 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18,
204 MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19,
205 MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20,
206 MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21
210 MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0,
211 MLX4_QUERY_FUNC_FLAGS_A0_RES_QP = 1LL << 1
215 MLX4_VF_CAP_FLAG_RESET = 1 << 0
218 /* bit enums for an 8-bit flags field indicating special use
219 * QPs which require special handling in qp_reserve_range.
220 * Currently, this only includes QPs used by the ETH interface,
221 * where we expect to use blueflame. These QPs must not have
222 * bits 6 and 7 set in their qp number.
224 * This enum may use only bits 0..7.
227 MLX4_RESERVE_A0_QP = 1 << 6,
228 MLX4_RESERVE_ETH_BF_QP = 1 << 7,
232 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
233 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1,
234 MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2,
235 MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3
239 MLX4_USER_DEV_CAP_LARGE_CQE = 1L << 0
243 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0,
244 MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1,
245 MLX4_FUNC_CAP_DMFS_A0_STATIC = 1L << 2
249 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
252 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1,
253 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
254 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
255 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
256 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
257 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
258 MLX4_BMME_FLAG_PORT_REMAP = 1 << 24,
259 MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28,
263 MLX4_FLAG_PORT_REMAP = MLX4_BMME_FLAG_PORT_REMAP
267 MLX4_EVENT_TYPE_COMP = 0x00,
268 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
269 MLX4_EVENT_TYPE_COMM_EST = 0x02,
270 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
271 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
272 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
273 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
274 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
275 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
276 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
277 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
278 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
279 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
280 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
281 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
282 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
283 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
284 MLX4_EVENT_TYPE_CMD = 0x0a,
285 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
286 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
287 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a,
288 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
289 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
290 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
291 MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e,
292 MLX4_EVENT_TYPE_NONE = 0xff,
296 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
297 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
301 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1,
302 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2,
306 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
309 enum slave_port_state {
315 enum slave_port_gen_event {
316 SLAVE_PORT_GEN_EVENT_DOWN = 0,
317 SLAVE_PORT_GEN_EVENT_UP,
318 SLAVE_PORT_GEN_EVENT_NONE,
321 enum slave_port_state_event {
322 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
323 MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
324 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
325 MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
329 MLX4_PERM_LOCAL_READ = 1 << 10,
330 MLX4_PERM_LOCAL_WRITE = 1 << 11,
331 MLX4_PERM_REMOTE_READ = 1 << 12,
332 MLX4_PERM_REMOTE_WRITE = 1 << 13,
333 MLX4_PERM_ATOMIC = 1 << 14,
334 MLX4_PERM_BIND_MW = 1 << 15,
335 MLX4_PERM_MASK = 0xFC00
339 MLX4_OPCODE_NOP = 0x00,
340 MLX4_OPCODE_SEND_INVAL = 0x01,
341 MLX4_OPCODE_RDMA_WRITE = 0x08,
342 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
343 MLX4_OPCODE_SEND = 0x0a,
344 MLX4_OPCODE_SEND_IMM = 0x0b,
345 MLX4_OPCODE_LSO = 0x0e,
346 MLX4_OPCODE_RDMA_READ = 0x10,
347 MLX4_OPCODE_ATOMIC_CS = 0x11,
348 MLX4_OPCODE_ATOMIC_FA = 0x12,
349 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
350 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
351 MLX4_OPCODE_BIND_MW = 0x18,
352 MLX4_OPCODE_FMR = 0x19,
353 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
354 MLX4_OPCODE_CONFIG_CMD = 0x1f,
356 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
357 MLX4_RECV_OPCODE_SEND = 0x01,
358 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
359 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
361 MLX4_CQE_OPCODE_ERROR = 0x1e,
362 MLX4_CQE_OPCODE_RESIZE = 0x16,
366 MLX4_STAT_RATE_OFFSET = 5
370 MLX4_PROT_IB_IPV6 = 0,
377 MLX4_MTT_FLAG_PRESENT = 1
380 enum mlx4_qp_region {
381 MLX4_QP_REGION_FW = 0,
382 MLX4_QP_REGION_RSS_RAW_ETH,
383 MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH,
384 MLX4_QP_REGION_ETH_ADDR,
385 MLX4_QP_REGION_FC_ADDR,
386 MLX4_QP_REGION_FC_EXCH,
390 enum mlx4_port_type {
391 MLX4_PORT_TYPE_NONE = 0,
392 MLX4_PORT_TYPE_IB = 1,
393 MLX4_PORT_TYPE_ETH = 2,
394 MLX4_PORT_TYPE_AUTO = 3
397 enum mlx4_special_vlan_idx {
398 MLX4_NO_VLAN_IDX = 0,
403 enum mlx4_steer_type {
410 MLX4_NUM_FEXCH = 64 * 1024,
414 MLX4_MAX_FAST_REG_PAGES = 511,
418 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
419 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
420 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
423 /* Port mgmt change event handling */
425 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
426 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
427 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
428 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
429 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
433 MLX4_DEVICE_STATE_UP = 1 << 0,
434 MLX4_DEVICE_STATE_INTERNAL_ERROR = 1 << 1,
438 MLX4_INTERFACE_STATE_UP = 1 << 0,
439 MLX4_INTERFACE_STATE_DELETION = 1 << 1,
442 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
443 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
445 enum mlx4_module_id {
446 MLX4_MODULE_ID_SFP = 0x3,
447 MLX4_MODULE_ID_QSFP = 0xC,
448 MLX4_MODULE_ID_QSFP_PLUS = 0xD,
449 MLX4_MODULE_ID_QSFP28 = 0x11,
452 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
454 return (major << 32) | (minor << 16) | subminor;
457 struct mlx4_phys_caps {
458 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
459 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
463 u32 base_tunnel_sqpn;
470 int vl_cap[MLX4_MAX_PORTS + 1];
471 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
472 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
473 u64 def_mac[MLX4_MAX_PORTS + 1];
474 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
475 int gid_table_len[MLX4_MAX_PORTS + 1];
476 int pkey_table_len[MLX4_MAX_PORTS + 1];
477 int trans_type[MLX4_MAX_PORTS + 1];
478 int vendor_oui[MLX4_MAX_PORTS + 1];
479 int wavelength[MLX4_MAX_PORTS + 1];
480 u64 trans_code[MLX4_MAX_PORTS + 1];
481 int local_ca_ack_delay;
485 int bf_regs_per_page;
492 int max_qp_init_rdma;
493 int max_qp_dest_rdma;
509 int num_comp_vectors;
514 int fmr_reserved_mtts;
523 int dmfs_high_steer_mode;
524 int fs_log_max_ucast_qp_range_size;
536 u16 stat_rate_support;
537 u8 port_width_cap[MLX4_MAX_PORTS + 1];
540 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
542 int reserved_qps_base[MLX4_NUM_QP_REGION];
545 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
546 u8 supported_type[MLX4_MAX_PORTS + 1];
547 u8 suggested_type[MLX4_MAX_PORTS + 1];
548 u8 default_sense[MLX4_MAX_PORTS + 1];
549 u32 port_mask[MLX4_MAX_PORTS + 1];
550 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
552 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
557 u32 userspace_caps; /* userspace must be aware of these */
558 u32 function_caps; /* VFs must be aware of these */
560 u64 phys_port_id[MLX4_MAX_PORTS + 1];
561 int tunnel_offload_mode;
562 u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1];
563 u8 alloc_res_qp_mask;
564 u32 dmfs_high_rate_qpn_base;
565 u32 dmfs_high_rate_qpn_range;
569 struct mlx4_buf_list {
575 struct mlx4_buf_list direct;
576 struct mlx4_buf_list *page_list;
589 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
592 struct mlx4_db_pgdir {
593 struct list_head list;
594 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
595 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
596 unsigned long *bits[2];
601 struct mlx4_ib_user_db_page;
606 struct mlx4_db_pgdir *pgdir;
607 struct mlx4_ib_user_db_page *user_page;
614 struct mlx4_hwq_resources {
638 enum mlx4_mw_type type;
644 struct mlx4_mpt_entry *mpt;
646 dma_addr_t dma_handle;
656 struct list_head bf_list;
657 unsigned free_bf_bmap;
659 void __iomem *bf_map;
665 struct mlx4_uar *uar;
670 void (*comp) (struct mlx4_cq *);
671 void (*event) (struct mlx4_cq *, enum mlx4_event);
673 struct mlx4_uar *uar;
686 struct completion free;
688 struct list_head list;
689 void (*comp)(struct mlx4_cq *);
692 int reset_notify_added;
693 struct list_head reset_notify;
697 void (*event) (struct mlx4_qp *, enum mlx4_event);
702 struct completion free;
706 void (*event) (struct mlx4_srq *, enum mlx4_event);
714 struct completion free;
726 __be32 sl_tclass_flowlabel;
739 __be32 sl_tclass_flowlabel;
749 struct mlx4_eth_av eth;
752 struct mlx4_counter {
778 struct mlx4_dev_persistent {
779 struct pci_dev *pdev;
780 struct mlx4_dev *dev;
781 int nvfs[MLX4_MAX_PORTS + 1];
783 enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1];
784 enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1];
785 struct work_struct catas_work;
786 struct workqueue_struct *catas_wq;
787 struct mutex device_state_mutex; /* protect HW state */
789 struct mutex interface_state_mutex; /* protect SW state */
794 struct mlx4_dev_persistent *persist;
796 unsigned long num_slaves;
797 struct mlx4_caps caps;
798 struct mlx4_phys_caps phys_caps;
799 struct mlx4_quotas quotas;
800 struct radix_tree_root qp_table_tree;
802 char board_id[MLX4_BOARD_ID_LEN];
804 int oper_log_mgm_entry_size;
805 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
806 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
807 struct mlx4_vf_dev *dev_vfs;
843 } __packed port_change;
845 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
847 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
848 } __packed comm_channel_arm;
853 } __packed mac_update;
856 } __packed flr_event;
858 __be16 current_temperature;
859 __be16 warning_threshold;
872 } __packed port_info;
875 __be32 tbl_entries_mask;
876 } __packed tbl_change_info;
878 } __packed port_mgmt_change;
883 } __packed bad_cable;
890 struct mlx4_init_port_param {
904 #define MAD_IFC_DATA_SZ 192
905 /* MAD IFC Mailbox */
906 struct mlx4_mad_ifc {
912 __be16 class_specific;
921 u8 data[MAD_IFC_DATA_SZ];
924 #define mlx4_foreach_port(port, dev, type) \
925 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
926 if ((type) == (dev)->caps.port_mask[(port)])
928 #define mlx4_foreach_non_ib_transport_port(port, dev) \
929 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
930 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB))
932 #define mlx4_foreach_ib_transport_port(port, dev) \
933 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
934 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
935 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
937 #define MLX4_INVALID_SLAVE_ID 0xFF
939 void handle_port_mgmt_change_event(struct work_struct *work);
941 static inline int mlx4_master_func_num(struct mlx4_dev *dev)
943 return dev->caps.function;
946 static inline int mlx4_is_master(struct mlx4_dev *dev)
948 return dev->flags & MLX4_FLAG_MASTER;
951 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev)
953 return dev->phys_caps.base_sqpn + 8 +
954 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev);
957 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
959 return (qpn < dev->phys_caps.base_sqpn + 8 +
960 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev) &&
961 qpn >= dev->phys_caps.base_sqpn) ||
962 (qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]);
965 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
967 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
969 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
975 static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
977 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
980 static inline int mlx4_is_slave(struct mlx4_dev *dev)
982 return dev->flags & MLX4_FLAG_SLAVE;
985 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
986 struct mlx4_buf *buf, gfp_t gfp);
987 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
988 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
990 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
991 return buf->direct.buf + offset;
993 return buf->page_list[offset >> PAGE_SHIFT].buf +
994 (offset & (PAGE_SIZE - 1));
997 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
998 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
999 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
1000 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
1002 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
1003 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
1004 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node);
1005 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
1007 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
1008 struct mlx4_mtt *mtt);
1009 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1010 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1012 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
1013 int npages, int page_shift, struct mlx4_mr *mr);
1014 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
1015 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
1016 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
1017 struct mlx4_mw *mw);
1018 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
1019 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
1020 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1021 int start_index, int npages, u64 *page_list);
1022 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1023 struct mlx4_buf *buf, gfp_t gfp);
1025 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order,
1027 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
1029 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
1030 int size, int max_direct);
1031 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
1034 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
1035 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
1036 unsigned vector, int collapsed, int timestamp_en);
1037 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
1038 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
1039 int *base, u8 flags);
1040 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
1042 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp,
1044 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
1046 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
1047 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
1048 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
1049 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
1050 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
1052 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
1053 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
1055 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1056 int block_mcast_loopback, enum mlx4_protocol prot);
1057 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1058 enum mlx4_protocol prot);
1059 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1060 u8 port, int block_mcast_loopback,
1061 enum mlx4_protocol protocol, u64 *reg_id);
1062 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1063 enum mlx4_protocol protocol, u64 reg_id);
1066 MLX4_DOMAIN_UVERBS = 0x1000,
1067 MLX4_DOMAIN_ETHTOOL = 0x2000,
1068 MLX4_DOMAIN_RFS = 0x3000,
1069 MLX4_DOMAIN_NIC = 0x5000,
1072 enum mlx4_net_trans_rule_id {
1073 MLX4_NET_TRANS_RULE_ID_ETH = 0,
1074 MLX4_NET_TRANS_RULE_ID_IB,
1075 MLX4_NET_TRANS_RULE_ID_IPV6,
1076 MLX4_NET_TRANS_RULE_ID_IPV4,
1077 MLX4_NET_TRANS_RULE_ID_TCP,
1078 MLX4_NET_TRANS_RULE_ID_UDP,
1079 MLX4_NET_TRANS_RULE_ID_VXLAN,
1080 MLX4_NET_TRANS_RULE_NUM, /* should be last */
1083 extern const u16 __sw_id_hw[];
1085 static inline int map_hw_to_sw_id(u16 header_id)
1089 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
1090 if (header_id == __sw_id_hw[i])
1096 enum mlx4_net_trans_promisc_mode {
1097 MLX4_FS_REGULAR = 1,
1098 MLX4_FS_ALL_DEFAULT,
1102 MLX4_FS_MODE_NUM, /* should be last */
1105 struct mlx4_spec_eth {
1106 u8 dst_mac[ETH_ALEN];
1107 u8 dst_mac_msk[ETH_ALEN];
1108 u8 src_mac[ETH_ALEN];
1109 u8 src_mac_msk[ETH_ALEN];
1110 u8 ether_type_enable;
1116 struct mlx4_spec_tcp_udp {
1118 __be16 dst_port_msk;
1120 __be16 src_port_msk;
1123 struct mlx4_spec_ipv4 {
1130 struct mlx4_spec_ib {
1137 struct mlx4_spec_vxlan {
1143 struct mlx4_spec_list {
1144 struct list_head list;
1145 enum mlx4_net_trans_rule_id id;
1147 struct mlx4_spec_eth eth;
1148 struct mlx4_spec_ib ib;
1149 struct mlx4_spec_ipv4 ipv4;
1150 struct mlx4_spec_tcp_udp tcp_udp;
1151 struct mlx4_spec_vxlan vxlan;
1155 enum mlx4_net_trans_hw_rule_queue {
1156 MLX4_NET_TRANS_Q_FIFO,
1157 MLX4_NET_TRANS_Q_LIFO,
1160 struct mlx4_net_trans_rule {
1161 struct list_head list;
1162 enum mlx4_net_trans_hw_rule_queue queue_mode;
1164 bool allow_loopback;
1165 enum mlx4_net_trans_promisc_mode promisc_mode;
1171 struct mlx4_net_trans_rule_hw_ctrl {
1183 struct mlx4_net_trans_rule_hw_ib {
1194 struct mlx4_net_trans_rule_hw_eth {
1207 u8 ether_type_enable;
1209 __be16 vlan_tag_msk;
1213 struct mlx4_net_trans_rule_hw_tcp_udp {
1220 __be16 dst_port_msk;
1224 __be16 src_port_msk;
1227 struct mlx4_net_trans_rule_hw_ipv4 {
1238 struct mlx4_net_trans_rule_hw_vxlan {
1254 struct mlx4_net_trans_rule_hw_eth eth;
1255 struct mlx4_net_trans_rule_hw_ib ib;
1256 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
1257 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
1258 struct mlx4_net_trans_rule_hw_vxlan vxlan;
1263 VXLAN_STEER_BY_OUTER_MAC = 1 << 0,
1264 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1,
1265 VXLAN_STEER_BY_VSID_VNI = 1 << 2,
1266 VXLAN_STEER_BY_INNER_MAC = 1 << 3,
1267 VXLAN_STEER_BY_INNER_VLAN = 1 << 4,
1271 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
1272 enum mlx4_net_trans_promisc_mode mode);
1273 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1274 enum mlx4_net_trans_promisc_mode mode);
1275 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1276 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1277 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1278 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1279 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
1281 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1282 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1283 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
1284 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
1285 void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap);
1286 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
1287 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
1288 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
1290 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc);
1291 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
1292 u8 *pg, u16 *ratelimit);
1293 int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable);
1294 int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx);
1295 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
1296 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1297 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1299 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
1300 int npages, u64 iova, u32 *lkey, u32 *rkey);
1301 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
1302 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
1303 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1304 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
1305 u32 *lkey, u32 *rkey);
1306 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1307 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
1308 int mlx4_test_interrupts(struct mlx4_dev *dev);
1309 int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap,
1311 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
1313 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec);
1315 int mlx4_get_phys_port_id(struct mlx4_dev *dev);
1316 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
1317 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
1319 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
1320 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1322 int mlx4_flow_attach(struct mlx4_dev *dev,
1323 struct mlx4_net_trans_rule *rule, u64 *reg_id);
1324 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
1325 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
1326 enum mlx4_net_trans_promisc_mode flow_type);
1327 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
1328 enum mlx4_net_trans_rule_id id);
1329 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id);
1331 int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr,
1332 int port, int qpn, u16 prio, u64 *reg_id);
1334 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
1337 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
1339 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
1340 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
1341 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
1342 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr);
1343 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
1344 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
1345 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
1347 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1348 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1350 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid,
1352 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id,
1355 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
1358 cycle_t mlx4_read_clock(struct mlx4_dev *dev);
1360 struct mlx4_active_ports {
1361 DECLARE_BITMAP(ports, MLX4_MAX_PORTS);
1363 /* Returns a bitmap of the physical ports which are assigned to slave */
1364 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave);
1366 /* Returns the physical port that represents the virtual port of the slave, */
1367 /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */
1368 /* mapping is returned. */
1369 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port);
1371 struct mlx4_slaves_pport {
1372 DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX);
1374 /* Returns a bitmap of all slaves that are assigned to port. */
1375 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
1378 /* Returns a bitmap of all slaves that are assigned exactly to all the */
1379 /* the ports that are set in crit_ports. */
1380 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
1381 struct mlx4_dev *dev,
1382 const struct mlx4_active_ports *crit_ports);
1384 /* Returns the slave's virtual port that represents the physical port. */
1385 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port);
1387 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port);
1389 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port);
1390 int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis);
1391 int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2);
1392 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port);
1393 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port);
1394 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
1396 int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1397 struct mlx4_mpt_entry ***mpt_entry);
1398 int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1399 struct mlx4_mpt_entry **mpt_entry);
1400 int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry,
1402 int mlx4_mr_hw_change_access(struct mlx4_dev *dev,
1403 struct mlx4_mpt_entry *mpt_entry,
1405 void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev,
1406 struct mlx4_mpt_entry **mpt_entry);
1407 void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr);
1408 int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr,
1409 u64 iova, u64 size, int npages,
1410 int page_shift, struct mlx4_mpt_entry *mpt_entry);
1412 int mlx4_get_module_info(struct mlx4_dev *dev, u8 port,
1413 u16 offset, u16 size, u8 *data);
1415 /* Returns true if running in low memory profile (kdump kernel) */
1416 static inline bool mlx4_low_memory_profile(void)
1418 return is_kdump_kernel();
1421 /* ACCESS REG commands */
1422 enum mlx4_access_reg_method {
1423 MLX4_ACCESS_REG_QUERY = 0x1,
1424 MLX4_ACCESS_REG_WRITE = 0x2,
1427 /* ACCESS PTYS Reg command */
1428 enum mlx4_ptys_proto {
1429 MLX4_PTYS_IB = 1<<0,
1430 MLX4_PTYS_EN = 1<<2,
1433 struct mlx4_ptys_reg {
1439 __be32 eth_proto_cap;
1440 __be16 ib_width_cap;
1441 __be16 ib_speed_cap;
1443 __be32 eth_proto_admin;
1444 __be16 ib_width_admin;
1445 __be16 ib_speed_admin;
1447 __be32 eth_proto_oper;
1448 __be16 ib_width_oper;
1449 __be16 ib_speed_oper;
1451 __be32 eth_proto_lp_adv;
1454 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev,
1455 enum mlx4_access_reg_method method,
1456 struct mlx4_ptys_reg *ptys_reg);
1458 #endif /* MLX4_DEVICE_H */