2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/if_ether.h>
37 #include <linux/pci.h>
38 #include <linux/completion.h>
39 #include <linux/radix-tree.h>
40 #include <linux/cpu_rmap.h>
41 #include <linux/crash_dump.h>
43 #include <linux/atomic.h>
45 #include <linux/timecounter.h>
47 #define MAX_MSIX_P_PORT 17
49 #define MIN_MSIX_P_PORT 5
50 #define MLX4_IS_LEGACY_EQ_MODE(dev_cap) ((dev_cap).num_comp_vectors < \
51 (dev_cap).num_ports * MIN_MSIX_P_PORT)
53 #define MLX4_MAX_100M_UNITS_VAL 255 /*
54 * work around: can't set values
55 * greater then this value when
56 * using 100 Mbps units.
58 #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */
59 #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */
60 #define MLX4_RATELIMIT_DEFAULT 0x00ff
62 #define MLX4_ROCE_MAX_GIDS 128
63 #define MLX4_ROCE_PF_GIDS 16
66 MLX4_FLAG_MSI_X = 1 << 0,
67 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
68 MLX4_FLAG_MASTER = 1 << 2,
69 MLX4_FLAG_SLAVE = 1 << 3,
70 MLX4_FLAG_SRIOV = 1 << 4,
71 MLX4_FLAG_OLD_REG_MAC = 1 << 6,
72 MLX4_FLAG_BONDED = 1 << 7
76 MLX4_PORT_CAP_IS_SM = 1 << 1,
77 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
82 MLX4_MAX_PORT_PKEYS = 128,
83 MLX4_MAX_PORT_GIDS = 128
86 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
87 * These qkeys must not be allowed for general use. This is a 64k range,
88 * and to test for violation, we use the mask (protect against future chg).
90 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
91 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
94 MLX4_BOARD_ID_LEN = 64
99 MLX4_MAX_NUM_VF = 126,
100 MLX4_MAX_NUM_VF_P_PORT = 64,
101 MLX4_MFUNC_MAX = 128,
102 MLX4_MAX_EQ_NUM = 1024,
103 MLX4_MFUNC_EQ_NUM = 4,
104 MLX4_MFUNC_MAX_EQES = 8,
105 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
108 /* Driver supports 3 diffrent device methods to manage traffic steering:
109 * -device managed - High level API for ib and eth flow steering. FW is
110 * managing flow steering tables.
111 * - B0 steering mode - Common low level API for ib and (if supported) eth.
112 * - A0 steering mode - Limited low level API for eth. In case of IB,
116 MLX4_STEERING_MODE_A0,
117 MLX4_STEERING_MODE_B0,
118 MLX4_STEERING_MODE_DEVICE_MANAGED
122 MLX4_STEERING_DMFS_A0_DEFAULT,
123 MLX4_STEERING_DMFS_A0_DYNAMIC,
124 MLX4_STEERING_DMFS_A0_STATIC,
125 MLX4_STEERING_DMFS_A0_DISABLE,
126 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED
129 static inline const char *mlx4_steering_mode_str(int steering_mode)
131 switch (steering_mode) {
132 case MLX4_STEERING_MODE_A0:
133 return "A0 steering";
135 case MLX4_STEERING_MODE_B0:
136 return "B0 steering";
138 case MLX4_STEERING_MODE_DEVICE_MANAGED:
139 return "Device managed flow steering";
142 return "Unrecognize steering mode";
147 MLX4_TUNNEL_OFFLOAD_MODE_NONE,
148 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
152 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
153 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
154 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
155 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
156 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
157 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
158 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
159 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
160 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
161 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
162 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
163 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
164 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
165 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
166 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
167 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
168 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
169 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
170 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
171 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
172 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
173 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
174 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
175 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
176 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
177 MLX4_DEV_CAP_FLAG_RSS_IP_FRAG = 1LL << 52,
178 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53,
179 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
180 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
181 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
182 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62
186 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
187 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
188 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
189 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
190 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4,
191 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5,
192 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6,
193 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7,
194 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8,
195 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9,
196 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10,
197 MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11,
198 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12,
199 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13,
200 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14,
201 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 15,
202 MLX4_DEV_CAP_FLAG2_CONFIG_DEV = 1LL << 16,
203 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17,
204 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18,
205 MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19,
206 MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20,
207 MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21,
208 MLX4_DEV_CAP_FLAG2_QCN = 1LL << 22,
209 MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT = 1LL << 23,
210 MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 24,
211 MLX4_DEV_CAP_FLAG2_QOS_VPP = 1LL << 25,
212 MLX4_DEV_CAP_FLAG2_ETS_CFG = 1LL << 26,
213 MLX4_DEV_CAP_FLAG2_PORT_BEACON = 1LL << 27,
214 MLX4_DEV_CAP_FLAG2_IGNORE_FCS = 1LL << 28,
215 MLX4_DEV_CAP_FLAG2_PHV_EN = 1LL << 29,
216 MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN = 1LL << 30,
217 MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB = 1ULL << 31,
218 MLX4_DEV_CAP_FLAG2_LB_SRC_CHK = 1ULL << 32,
222 MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0,
223 MLX4_QUERY_FUNC_FLAGS_A0_RES_QP = 1LL << 1
227 MLX4_VF_CAP_FLAG_RESET = 1 << 0
230 /* bit enums for an 8-bit flags field indicating special use
231 * QPs which require special handling in qp_reserve_range.
232 * Currently, this only includes QPs used by the ETH interface,
233 * where we expect to use blueflame. These QPs must not have
234 * bits 6 and 7 set in their qp number.
236 * This enum may use only bits 0..7.
239 MLX4_RESERVE_A0_QP = 1 << 6,
240 MLX4_RESERVE_ETH_BF_QP = 1 << 7,
244 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
245 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1,
246 MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2,
247 MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3
251 MLX4_USER_DEV_CAP_LARGE_CQE = 1L << 0
255 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0,
256 MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1,
257 MLX4_FUNC_CAP_DMFS_A0_STATIC = 1L << 2
261 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
264 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1,
265 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
266 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
267 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
268 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
269 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
270 MLX4_BMME_FLAG_PORT_REMAP = 1 << 24,
271 MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28,
275 MLX4_FLAG_PORT_REMAP = MLX4_BMME_FLAG_PORT_REMAP
279 MLX4_EVENT_TYPE_COMP = 0x00,
280 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
281 MLX4_EVENT_TYPE_COMM_EST = 0x02,
282 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
283 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
284 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
285 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
286 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
287 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
288 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
289 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
290 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
291 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
292 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
293 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
294 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
295 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
296 MLX4_EVENT_TYPE_CMD = 0x0a,
297 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
298 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
299 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a,
300 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
301 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
302 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
303 MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e,
304 MLX4_EVENT_TYPE_NONE = 0xff,
308 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
309 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
313 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1,
314 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2,
318 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
321 enum slave_port_state {
327 enum slave_port_gen_event {
328 SLAVE_PORT_GEN_EVENT_DOWN = 0,
329 SLAVE_PORT_GEN_EVENT_UP,
330 SLAVE_PORT_GEN_EVENT_NONE,
333 enum slave_port_state_event {
334 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
335 MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
336 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
337 MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
341 MLX4_PERM_LOCAL_READ = 1 << 10,
342 MLX4_PERM_LOCAL_WRITE = 1 << 11,
343 MLX4_PERM_REMOTE_READ = 1 << 12,
344 MLX4_PERM_REMOTE_WRITE = 1 << 13,
345 MLX4_PERM_ATOMIC = 1 << 14,
346 MLX4_PERM_BIND_MW = 1 << 15,
347 MLX4_PERM_MASK = 0xFC00
351 MLX4_OPCODE_NOP = 0x00,
352 MLX4_OPCODE_SEND_INVAL = 0x01,
353 MLX4_OPCODE_RDMA_WRITE = 0x08,
354 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
355 MLX4_OPCODE_SEND = 0x0a,
356 MLX4_OPCODE_SEND_IMM = 0x0b,
357 MLX4_OPCODE_LSO = 0x0e,
358 MLX4_OPCODE_RDMA_READ = 0x10,
359 MLX4_OPCODE_ATOMIC_CS = 0x11,
360 MLX4_OPCODE_ATOMIC_FA = 0x12,
361 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
362 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
363 MLX4_OPCODE_BIND_MW = 0x18,
364 MLX4_OPCODE_FMR = 0x19,
365 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
366 MLX4_OPCODE_CONFIG_CMD = 0x1f,
368 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
369 MLX4_RECV_OPCODE_SEND = 0x01,
370 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
371 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
373 MLX4_CQE_OPCODE_ERROR = 0x1e,
374 MLX4_CQE_OPCODE_RESIZE = 0x16,
378 MLX4_STAT_RATE_OFFSET = 5
382 MLX4_PROT_IB_IPV6 = 0,
389 MLX4_MTT_FLAG_PRESENT = 1
392 enum mlx4_qp_region {
393 MLX4_QP_REGION_FW = 0,
394 MLX4_QP_REGION_RSS_RAW_ETH,
395 MLX4_QP_REGION_BOTTOM = MLX4_QP_REGION_RSS_RAW_ETH,
396 MLX4_QP_REGION_ETH_ADDR,
397 MLX4_QP_REGION_FC_ADDR,
398 MLX4_QP_REGION_FC_EXCH,
402 enum mlx4_port_type {
403 MLX4_PORT_TYPE_NONE = 0,
404 MLX4_PORT_TYPE_IB = 1,
405 MLX4_PORT_TYPE_ETH = 2,
406 MLX4_PORT_TYPE_AUTO = 3
409 enum mlx4_special_vlan_idx {
410 MLX4_NO_VLAN_IDX = 0,
415 enum mlx4_steer_type {
422 MLX4_NUM_FEXCH = 64 * 1024,
426 MLX4_MAX_FAST_REG_PAGES = 511,
430 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
431 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
432 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
435 /* Port mgmt change event handling */
437 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
438 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
439 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
440 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
441 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
445 MLX4_DEVICE_STATE_UP = 1 << 0,
446 MLX4_DEVICE_STATE_INTERNAL_ERROR = 1 << 1,
450 MLX4_INTERFACE_STATE_UP = 1 << 0,
451 MLX4_INTERFACE_STATE_DELETION = 1 << 1,
454 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
455 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
457 enum mlx4_module_id {
458 MLX4_MODULE_ID_SFP = 0x3,
459 MLX4_MODULE_ID_QSFP = 0xC,
460 MLX4_MODULE_ID_QSFP_PLUS = 0xD,
461 MLX4_MODULE_ID_QSFP28 = 0x11,
465 MLX4_QP_RATE_LIMIT_NONE = 0,
466 MLX4_QP_RATE_LIMIT_KBS = 1,
467 MLX4_QP_RATE_LIMIT_MBS = 2,
468 MLX4_QP_RATE_LIMIT_GBS = 3
471 struct mlx4_rate_limit_caps {
472 u16 num_rates; /* Number of different rates */
479 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
481 return (major << 32) | (minor << 16) | subminor;
484 struct mlx4_phys_caps {
485 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
486 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
490 u32 base_tunnel_sqpn;
497 int vl_cap[MLX4_MAX_PORTS + 1];
498 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
499 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
500 u64 def_mac[MLX4_MAX_PORTS + 1];
501 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
502 int gid_table_len[MLX4_MAX_PORTS + 1];
503 int pkey_table_len[MLX4_MAX_PORTS + 1];
504 int trans_type[MLX4_MAX_PORTS + 1];
505 int vendor_oui[MLX4_MAX_PORTS + 1];
506 int wavelength[MLX4_MAX_PORTS + 1];
507 u64 trans_code[MLX4_MAX_PORTS + 1];
508 int local_ca_ack_delay;
512 int bf_regs_per_page;
519 int max_qp_init_rdma;
520 int max_qp_dest_rdma;
536 int num_comp_vectors;
540 int fmr_reserved_mtts;
549 int dmfs_high_steer_mode;
550 int fs_log_max_ucast_qp_range_size;
562 u16 stat_rate_support;
563 u8 port_width_cap[MLX4_MAX_PORTS + 1];
566 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
568 int reserved_qps_base[MLX4_NUM_QP_REGION];
571 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
572 u8 supported_type[MLX4_MAX_PORTS + 1];
573 u8 suggested_type[MLX4_MAX_PORTS + 1];
574 u8 default_sense[MLX4_MAX_PORTS + 1];
575 u32 port_mask[MLX4_MAX_PORTS + 1];
576 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
578 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
583 u32 userspace_caps; /* userspace must be aware of these */
584 u32 function_caps; /* VFs must be aware of these */
586 u64 phys_port_id[MLX4_MAX_PORTS + 1];
587 int tunnel_offload_mode;
588 u8 rx_checksum_flags_port[MLX4_MAX_PORTS + 1];
589 u8 phv_bit[MLX4_MAX_PORTS + 1];
590 u8 alloc_res_qp_mask;
591 u32 dmfs_high_rate_qpn_base;
592 u32 dmfs_high_rate_qpn_range;
594 struct mlx4_rate_limit_caps rl_caps;
597 struct mlx4_buf_list {
603 struct mlx4_buf_list direct;
604 struct mlx4_buf_list *page_list;
617 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
620 struct mlx4_db_pgdir {
621 struct list_head list;
622 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
623 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
624 unsigned long *bits[2];
629 struct mlx4_ib_user_db_page;
634 struct mlx4_db_pgdir *pgdir;
635 struct mlx4_ib_user_db_page *user_page;
642 struct mlx4_hwq_resources {
666 enum mlx4_mw_type type;
672 struct mlx4_mpt_entry *mpt;
674 dma_addr_t dma_handle;
684 struct list_head bf_list;
685 unsigned free_bf_bmap;
687 void __iomem *bf_map;
693 struct mlx4_uar *uar;
698 void (*comp) (struct mlx4_cq *);
699 void (*event) (struct mlx4_cq *, enum mlx4_event);
701 struct mlx4_uar *uar;
714 struct completion free;
716 struct list_head list;
717 void (*comp)(struct mlx4_cq *);
720 int reset_notify_added;
721 struct list_head reset_notify;
725 void (*event) (struct mlx4_qp *, enum mlx4_event);
730 struct completion free;
734 void (*event) (struct mlx4_srq *, enum mlx4_event);
742 struct completion free;
754 __be32 sl_tclass_flowlabel;
767 __be32 sl_tclass_flowlabel;
777 struct mlx4_eth_av eth;
780 /* Counters should be saturate once they reach their maximum value */
781 #define ASSIGN_32BIT_COUNTER(counter, value) do { \
782 if ((value) > U32_MAX) \
783 counter = cpu_to_be32(U32_MAX); \
785 counter = cpu_to_be32(value); \
788 struct mlx4_counter {
814 struct mlx4_dev_persistent {
815 struct pci_dev *pdev;
816 struct mlx4_dev *dev;
817 int nvfs[MLX4_MAX_PORTS + 1];
819 enum mlx4_port_type curr_port_type[MLX4_MAX_PORTS + 1];
820 enum mlx4_port_type curr_port_poss_type[MLX4_MAX_PORTS + 1];
821 struct work_struct catas_work;
822 struct workqueue_struct *catas_wq;
823 struct mutex device_state_mutex; /* protect HW state */
825 struct mutex interface_state_mutex; /* protect SW state */
830 struct mlx4_dev_persistent *persist;
832 unsigned long num_slaves;
833 struct mlx4_caps caps;
834 struct mlx4_phys_caps phys_caps;
835 struct mlx4_quotas quotas;
836 struct radix_tree_root qp_table_tree;
839 char board_id[MLX4_BOARD_ID_LEN];
841 int oper_log_mgm_entry_size;
842 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
843 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
844 struct mlx4_vf_dev *dev_vfs;
847 struct mlx4_clock_params {
886 } __packed port_change;
888 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
890 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
891 } __packed comm_channel_arm;
896 } __packed mac_update;
899 } __packed flr_event;
901 __be16 current_temperature;
902 __be16 warning_threshold;
915 } __packed port_info;
918 __be32 tbl_entries_mask;
919 } __packed tbl_change_info;
921 } __packed port_mgmt_change;
926 } __packed bad_cable;
933 struct mlx4_init_port_param {
947 #define MAD_IFC_DATA_SZ 192
948 /* MAD IFC Mailbox */
949 struct mlx4_mad_ifc {
955 __be16 class_specific;
964 u8 data[MAD_IFC_DATA_SZ];
967 #define mlx4_foreach_port(port, dev, type) \
968 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
969 if ((type) == (dev)->caps.port_mask[(port)])
971 #define mlx4_foreach_non_ib_transport_port(port, dev) \
972 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
973 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB))
975 #define mlx4_foreach_ib_transport_port(port, dev) \
976 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
977 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
978 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
980 #define MLX4_INVALID_SLAVE_ID 0xFF
981 #define MLX4_SINK_COUNTER_INDEX(dev) (dev->caps.max_counters - 1)
983 void handle_port_mgmt_change_event(struct work_struct *work);
985 static inline int mlx4_master_func_num(struct mlx4_dev *dev)
987 return dev->caps.function;
990 static inline int mlx4_is_master(struct mlx4_dev *dev)
992 return dev->flags & MLX4_FLAG_MASTER;
995 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev)
997 return dev->phys_caps.base_sqpn + 8 +
998 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev);
1001 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
1003 return (qpn < dev->phys_caps.base_sqpn + 8 +
1004 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev) &&
1005 qpn >= dev->phys_caps.base_sqpn) ||
1006 (qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW]);
1009 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
1011 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
1013 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
1019 static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
1021 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
1024 static inline int mlx4_is_slave(struct mlx4_dev *dev)
1026 return dev->flags & MLX4_FLAG_SLAVE;
1029 static inline int mlx4_is_eth(struct mlx4_dev *dev, int port)
1031 return dev->caps.port_type[port] == MLX4_PORT_TYPE_IB ? 0 : 1;
1034 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
1035 struct mlx4_buf *buf, gfp_t gfp);
1036 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
1037 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
1039 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
1040 return buf->direct.buf + offset;
1042 return buf->page_list[offset >> PAGE_SHIFT].buf +
1043 (offset & (PAGE_SIZE - 1));
1046 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
1047 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
1048 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
1049 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
1051 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
1052 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
1053 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node);
1054 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
1056 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
1057 struct mlx4_mtt *mtt);
1058 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1059 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1061 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
1062 int npages, int page_shift, struct mlx4_mr *mr);
1063 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
1064 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
1065 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
1066 struct mlx4_mw *mw);
1067 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
1068 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
1069 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1070 int start_index, int npages, u64 *page_list);
1071 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1072 struct mlx4_buf *buf, gfp_t gfp);
1074 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order,
1076 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
1078 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
1079 int size, int max_direct);
1080 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
1083 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
1084 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
1085 unsigned vector, int collapsed, int timestamp_en);
1086 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
1087 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
1088 int *base, u8 flags);
1089 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
1091 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp,
1093 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
1095 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
1096 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
1097 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
1098 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
1099 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
1101 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
1102 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
1104 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1105 int block_mcast_loopback, enum mlx4_protocol prot);
1106 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1107 enum mlx4_protocol prot);
1108 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1109 u8 port, int block_mcast_loopback,
1110 enum mlx4_protocol protocol, u64 *reg_id);
1111 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1112 enum mlx4_protocol protocol, u64 reg_id);
1115 MLX4_DOMAIN_UVERBS = 0x1000,
1116 MLX4_DOMAIN_ETHTOOL = 0x2000,
1117 MLX4_DOMAIN_RFS = 0x3000,
1118 MLX4_DOMAIN_NIC = 0x5000,
1121 enum mlx4_net_trans_rule_id {
1122 MLX4_NET_TRANS_RULE_ID_ETH = 0,
1123 MLX4_NET_TRANS_RULE_ID_IB,
1124 MLX4_NET_TRANS_RULE_ID_IPV6,
1125 MLX4_NET_TRANS_RULE_ID_IPV4,
1126 MLX4_NET_TRANS_RULE_ID_TCP,
1127 MLX4_NET_TRANS_RULE_ID_UDP,
1128 MLX4_NET_TRANS_RULE_ID_VXLAN,
1129 MLX4_NET_TRANS_RULE_NUM, /* should be last */
1132 extern const u16 __sw_id_hw[];
1134 static inline int map_hw_to_sw_id(u16 header_id)
1138 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
1139 if (header_id == __sw_id_hw[i])
1145 enum mlx4_net_trans_promisc_mode {
1146 MLX4_FS_REGULAR = 1,
1147 MLX4_FS_ALL_DEFAULT,
1151 MLX4_FS_MODE_NUM, /* should be last */
1154 struct mlx4_spec_eth {
1155 u8 dst_mac[ETH_ALEN];
1156 u8 dst_mac_msk[ETH_ALEN];
1157 u8 src_mac[ETH_ALEN];
1158 u8 src_mac_msk[ETH_ALEN];
1159 u8 ether_type_enable;
1165 struct mlx4_spec_tcp_udp {
1167 __be16 dst_port_msk;
1169 __be16 src_port_msk;
1172 struct mlx4_spec_ipv4 {
1179 struct mlx4_spec_ib {
1186 struct mlx4_spec_vxlan {
1192 struct mlx4_spec_list {
1193 struct list_head list;
1194 enum mlx4_net_trans_rule_id id;
1196 struct mlx4_spec_eth eth;
1197 struct mlx4_spec_ib ib;
1198 struct mlx4_spec_ipv4 ipv4;
1199 struct mlx4_spec_tcp_udp tcp_udp;
1200 struct mlx4_spec_vxlan vxlan;
1204 enum mlx4_net_trans_hw_rule_queue {
1205 MLX4_NET_TRANS_Q_FIFO,
1206 MLX4_NET_TRANS_Q_LIFO,
1209 struct mlx4_net_trans_rule {
1210 struct list_head list;
1211 enum mlx4_net_trans_hw_rule_queue queue_mode;
1213 bool allow_loopback;
1214 enum mlx4_net_trans_promisc_mode promisc_mode;
1220 struct mlx4_net_trans_rule_hw_ctrl {
1232 struct mlx4_net_trans_rule_hw_ib {
1243 struct mlx4_net_trans_rule_hw_eth {
1256 u8 ether_type_enable;
1258 __be16 vlan_tag_msk;
1262 struct mlx4_net_trans_rule_hw_tcp_udp {
1269 __be16 dst_port_msk;
1273 __be16 src_port_msk;
1276 struct mlx4_net_trans_rule_hw_ipv4 {
1287 struct mlx4_net_trans_rule_hw_vxlan {
1303 struct mlx4_net_trans_rule_hw_eth eth;
1304 struct mlx4_net_trans_rule_hw_ib ib;
1305 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
1306 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
1307 struct mlx4_net_trans_rule_hw_vxlan vxlan;
1312 VXLAN_STEER_BY_OUTER_MAC = 1 << 0,
1313 VXLAN_STEER_BY_OUTER_VLAN = 1 << 1,
1314 VXLAN_STEER_BY_VSID_VNI = 1 << 2,
1315 VXLAN_STEER_BY_INNER_MAC = 1 << 3,
1316 VXLAN_STEER_BY_INNER_VLAN = 1 << 4,
1320 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
1321 enum mlx4_net_trans_promisc_mode mode);
1322 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1323 enum mlx4_net_trans_promisc_mode mode);
1324 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1325 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1326 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1327 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1328 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
1330 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1331 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1332 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
1333 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
1334 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
1335 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
1336 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
1338 int mlx4_SET_PORT_BEACON(struct mlx4_dev *dev, u8 port, u16 time);
1339 int mlx4_SET_PORT_fcs_check(struct mlx4_dev *dev, u8 port,
1340 u8 ignore_fcs_value);
1341 int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable);
1342 int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val);
1343 int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv);
1344 int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx);
1345 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
1346 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1347 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1349 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
1350 int npages, u64 iova, u32 *lkey, u32 *rkey);
1351 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
1352 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
1353 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1354 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
1355 u32 *lkey, u32 *rkey);
1356 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1357 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
1358 int mlx4_test_interrupts(struct mlx4_dev *dev);
1359 u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port);
1360 bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector);
1361 struct cpu_rmap *mlx4_get_cpu_rmap(struct mlx4_dev *dev, int port);
1362 int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector);
1363 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
1365 int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector);
1366 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec);
1368 int mlx4_get_phys_port_id(struct mlx4_dev *dev);
1369 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
1370 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
1372 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
1373 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1374 int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port);
1376 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry,
1378 __be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port);
1379 void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port);
1380 int mlx4_flow_attach(struct mlx4_dev *dev,
1381 struct mlx4_net_trans_rule *rule, u64 *reg_id);
1382 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
1383 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
1384 enum mlx4_net_trans_promisc_mode flow_type);
1385 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
1386 enum mlx4_net_trans_rule_id id);
1387 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id);
1389 int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr,
1390 int port, int qpn, u16 prio, u64 *reg_id);
1392 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
1395 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
1397 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
1398 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
1399 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
1400 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr);
1401 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
1402 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
1403 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
1405 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1406 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1408 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid,
1410 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id,
1413 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
1416 cycle_t mlx4_read_clock(struct mlx4_dev *dev);
1418 struct mlx4_active_ports {
1419 DECLARE_BITMAP(ports, MLX4_MAX_PORTS);
1421 /* Returns a bitmap of the physical ports which are assigned to slave */
1422 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave);
1424 /* Returns the physical port that represents the virtual port of the slave, */
1425 /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */
1426 /* mapping is returned. */
1427 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port);
1429 struct mlx4_slaves_pport {
1430 DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX);
1432 /* Returns a bitmap of all slaves that are assigned to port. */
1433 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
1436 /* Returns a bitmap of all slaves that are assigned exactly to all the */
1437 /* the ports that are set in crit_ports. */
1438 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
1439 struct mlx4_dev *dev,
1440 const struct mlx4_active_ports *crit_ports);
1442 /* Returns the slave's virtual port that represents the physical port. */
1443 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port);
1445 int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port);
1447 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port);
1448 int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis);
1449 int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2);
1450 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port);
1451 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port);
1452 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
1454 int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1455 struct mlx4_mpt_entry ***mpt_entry);
1456 int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr,
1457 struct mlx4_mpt_entry **mpt_entry);
1458 int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry,
1460 int mlx4_mr_hw_change_access(struct mlx4_dev *dev,
1461 struct mlx4_mpt_entry *mpt_entry,
1463 void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev,
1464 struct mlx4_mpt_entry **mpt_entry);
1465 void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr);
1466 int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr,
1467 u64 iova, u64 size, int npages,
1468 int page_shift, struct mlx4_mpt_entry *mpt_entry);
1470 int mlx4_get_module_info(struct mlx4_dev *dev, u8 port,
1471 u16 offset, u16 size, u8 *data);
1473 /* Returns true if running in low memory profile (kdump kernel) */
1474 static inline bool mlx4_low_memory_profile(void)
1476 return is_kdump_kernel();
1479 /* ACCESS REG commands */
1480 enum mlx4_access_reg_method {
1481 MLX4_ACCESS_REG_QUERY = 0x1,
1482 MLX4_ACCESS_REG_WRITE = 0x2,
1485 /* ACCESS PTYS Reg command */
1486 enum mlx4_ptys_proto {
1487 MLX4_PTYS_IB = 1<<0,
1488 MLX4_PTYS_EN = 1<<2,
1491 struct mlx4_ptys_reg {
1497 __be32 eth_proto_cap;
1498 __be16 ib_width_cap;
1499 __be16 ib_speed_cap;
1501 __be32 eth_proto_admin;
1502 __be16 ib_width_admin;
1503 __be16 ib_speed_admin;
1505 __be32 eth_proto_oper;
1506 __be16 ib_width_oper;
1507 __be16 ib_speed_oper;
1509 __be32 eth_proto_lp_adv;
1512 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev,
1513 enum mlx4_access_reg_method method,
1514 struct mlx4_ptys_reg *ptys_reg);
1516 int mlx4_get_internal_clock_params(struct mlx4_dev *dev,
1517 struct mlx4_clock_params *params);
1519 #endif /* MLX4_DEVICE_H */