2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/pci.h>
37 #include <linux/completion.h>
38 #include <linux/radix-tree.h>
39 #include <linux/cpu_rmap.h>
41 #include <linux/atomic.h>
43 #include <linux/clocksource.h>
45 #define MAX_MSIX_P_PORT 17
47 #define MSIX_LEGACY_SZ 4
48 #define MIN_MSIX_P_PORT 5
51 MLX4_FLAG_MSI_X = 1 << 0,
52 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
53 MLX4_FLAG_MASTER = 1 << 2,
54 MLX4_FLAG_SLAVE = 1 << 3,
55 MLX4_FLAG_SRIOV = 1 << 4,
59 MLX4_PORT_CAP_IS_SM = 1 << 1,
60 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
65 MLX4_MAX_PORT_PKEYS = 128
68 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
69 * These qkeys must not be allowed for general use. This is a 64k range,
70 * and to test for violation, we use the mask (protect against future chg).
72 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
73 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
76 MLX4_BOARD_ID_LEN = 64
83 MLX4_MAX_EQ_NUM = 1024,
84 MLX4_MFUNC_EQ_NUM = 4,
85 MLX4_MFUNC_MAX_EQES = 8,
86 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
89 /* Driver supports 3 diffrent device methods to manage traffic steering:
90 * -device managed - High level API for ib and eth flow steering. FW is
91 * managing flow steering tables.
92 * - B0 steering mode - Common low level API for ib and (if supported) eth.
93 * - A0 steering mode - Limited low level API for eth. In case of IB,
97 MLX4_STEERING_MODE_A0,
98 MLX4_STEERING_MODE_B0,
99 MLX4_STEERING_MODE_DEVICE_MANAGED
102 static inline const char *mlx4_steering_mode_str(int steering_mode)
104 switch (steering_mode) {
105 case MLX4_STEERING_MODE_A0:
106 return "A0 steering";
108 case MLX4_STEERING_MODE_B0:
109 return "B0 steering";
111 case MLX4_STEERING_MODE_DEVICE_MANAGED:
112 return "Device managed flow steering";
115 return "Unrecognize steering mode";
120 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
121 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
122 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
123 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
124 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
125 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
126 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
127 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
128 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
129 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
130 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
131 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
132 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
133 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
134 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
135 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
136 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
137 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
138 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
139 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
140 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
141 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
142 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
143 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
144 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
145 MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53,
146 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
147 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
148 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
149 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62
153 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
154 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
155 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
156 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
157 MLX4_DEV_CAP_FLAGS2_REASSIGN_MAC_EN = 1LL << 4,
158 MLX4_DEV_CAP_FLAG2_TS = 1LL << 5,
159 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6,
160 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7,
161 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8
165 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
166 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1
170 MLX4_USER_DEV_CAP_64B_CQE = 1L << 0
174 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0
178 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
181 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1,
182 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
183 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
184 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
185 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
186 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
190 MLX4_EVENT_TYPE_COMP = 0x00,
191 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
192 MLX4_EVENT_TYPE_COMM_EST = 0x02,
193 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
194 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
195 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
196 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
197 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
198 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
199 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
200 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
201 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
202 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
203 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
204 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
205 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
206 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
207 MLX4_EVENT_TYPE_CMD = 0x0a,
208 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
209 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
210 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
211 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
212 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
213 MLX4_EVENT_TYPE_NONE = 0xff,
217 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
218 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
222 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
225 enum slave_port_state {
231 enum slave_port_gen_event {
232 SLAVE_PORT_GEN_EVENT_DOWN = 0,
233 SLAVE_PORT_GEN_EVENT_UP,
234 SLAVE_PORT_GEN_EVENT_NONE,
237 enum slave_port_state_event {
238 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
239 MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
240 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
241 MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
245 MLX4_PERM_LOCAL_READ = 1 << 10,
246 MLX4_PERM_LOCAL_WRITE = 1 << 11,
247 MLX4_PERM_REMOTE_READ = 1 << 12,
248 MLX4_PERM_REMOTE_WRITE = 1 << 13,
249 MLX4_PERM_ATOMIC = 1 << 14,
250 MLX4_PERM_BIND_MW = 1 << 15,
254 MLX4_OPCODE_NOP = 0x00,
255 MLX4_OPCODE_SEND_INVAL = 0x01,
256 MLX4_OPCODE_RDMA_WRITE = 0x08,
257 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
258 MLX4_OPCODE_SEND = 0x0a,
259 MLX4_OPCODE_SEND_IMM = 0x0b,
260 MLX4_OPCODE_LSO = 0x0e,
261 MLX4_OPCODE_RDMA_READ = 0x10,
262 MLX4_OPCODE_ATOMIC_CS = 0x11,
263 MLX4_OPCODE_ATOMIC_FA = 0x12,
264 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
265 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
266 MLX4_OPCODE_BIND_MW = 0x18,
267 MLX4_OPCODE_FMR = 0x19,
268 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
269 MLX4_OPCODE_CONFIG_CMD = 0x1f,
271 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
272 MLX4_RECV_OPCODE_SEND = 0x01,
273 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
274 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
276 MLX4_CQE_OPCODE_ERROR = 0x1e,
277 MLX4_CQE_OPCODE_RESIZE = 0x16,
281 MLX4_STAT_RATE_OFFSET = 5
285 MLX4_PROT_IB_IPV6 = 0,
292 MLX4_MTT_FLAG_PRESENT = 1
295 enum mlx4_qp_region {
296 MLX4_QP_REGION_FW = 0,
297 MLX4_QP_REGION_ETH_ADDR,
298 MLX4_QP_REGION_FC_ADDR,
299 MLX4_QP_REGION_FC_EXCH,
303 enum mlx4_port_type {
304 MLX4_PORT_TYPE_NONE = 0,
305 MLX4_PORT_TYPE_IB = 1,
306 MLX4_PORT_TYPE_ETH = 2,
307 MLX4_PORT_TYPE_AUTO = 3
310 enum mlx4_special_vlan_idx {
311 MLX4_NO_VLAN_IDX = 0,
316 enum mlx4_steer_type {
323 MLX4_NUM_FEXCH = 64 * 1024,
327 MLX4_MAX_FAST_REG_PAGES = 511,
331 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
332 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
333 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
336 /* Port mgmt change event handling */
338 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
339 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
340 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
341 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
342 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
345 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
346 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
348 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
350 return (major << 32) | (minor << 16) | subminor;
353 struct mlx4_phys_caps {
354 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
355 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
359 u32 base_tunnel_sqpn;
366 int vl_cap[MLX4_MAX_PORTS + 1];
367 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
368 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
369 u64 def_mac[MLX4_MAX_PORTS + 1];
370 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
371 int gid_table_len[MLX4_MAX_PORTS + 1];
372 int pkey_table_len[MLX4_MAX_PORTS + 1];
373 int trans_type[MLX4_MAX_PORTS + 1];
374 int vendor_oui[MLX4_MAX_PORTS + 1];
375 int wavelength[MLX4_MAX_PORTS + 1];
376 u64 trans_code[MLX4_MAX_PORTS + 1];
377 int local_ca_ack_delay;
381 int bf_regs_per_page;
388 int max_qp_init_rdma;
389 int max_qp_dest_rdma;
403 int num_comp_vectors;
408 int fmr_reserved_mtts;
417 int fs_log_max_ucast_qp_range_size;
429 u16 stat_rate_support;
430 u8 port_width_cap[MLX4_MAX_PORTS + 1];
433 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
435 int reserved_qps_base[MLX4_NUM_QP_REGION];
439 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
440 u8 supported_type[MLX4_MAX_PORTS + 1];
441 u8 suggested_type[MLX4_MAX_PORTS + 1];
442 u8 default_sense[MLX4_MAX_PORTS + 1];
443 u32 port_mask[MLX4_MAX_PORTS + 1];
444 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
446 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
451 u32 userspace_caps; /* userspace must be aware of these */
452 u32 function_caps; /* VFs must be aware of these */
456 struct mlx4_buf_list {
462 struct mlx4_buf_list direct;
463 struct mlx4_buf_list *page_list;
476 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
479 struct mlx4_db_pgdir {
480 struct list_head list;
481 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
482 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
483 unsigned long *bits[2];
488 struct mlx4_ib_user_db_page;
493 struct mlx4_db_pgdir *pgdir;
494 struct mlx4_ib_user_db_page *user_page;
501 struct mlx4_hwq_resources {
525 enum mlx4_mw_type type;
531 struct mlx4_mpt_entry *mpt;
533 dma_addr_t dma_handle;
543 struct list_head bf_list;
544 unsigned free_bf_bmap;
546 void __iomem *bf_map;
550 unsigned long offset;
552 struct mlx4_uar *uar;
557 void (*comp) (struct mlx4_cq *);
558 void (*event) (struct mlx4_cq *, enum mlx4_event);
560 struct mlx4_uar *uar;
572 struct completion free;
576 void (*event) (struct mlx4_qp *, enum mlx4_event);
581 struct completion free;
585 void (*event) (struct mlx4_srq *, enum mlx4_event);
593 struct completion free;
605 __be32 sl_tclass_flowlabel;
618 __be32 sl_tclass_flowlabel;
627 struct mlx4_eth_av eth;
630 struct mlx4_counter {
642 struct pci_dev *pdev;
644 unsigned long num_slaves;
645 struct mlx4_caps caps;
646 struct mlx4_phys_caps phys_caps;
647 struct radix_tree_root qp_table_tree;
649 char board_id[MLX4_BOARD_ID_LEN];
651 int oper_log_mgm_entry_size;
652 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
653 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
689 } __packed port_change;
691 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
693 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
694 } __packed comm_channel_arm;
699 } __packed mac_update;
702 } __packed flr_event;
704 __be16 current_temperature;
705 __be16 warning_threshold;
718 } __packed port_info;
721 __be32 tbl_entries_mask;
722 } __packed tbl_change_info;
724 } __packed port_mgmt_change;
731 struct mlx4_init_port_param {
745 #define mlx4_foreach_port(port, dev, type) \
746 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
747 if ((type) == (dev)->caps.port_mask[(port)])
749 #define mlx4_foreach_non_ib_transport_port(port, dev) \
750 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
751 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB))
753 #define mlx4_foreach_ib_transport_port(port, dev) \
754 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
755 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
756 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
758 #define MLX4_INVALID_SLAVE_ID 0xFF
760 void handle_port_mgmt_change_event(struct work_struct *work);
762 static inline int mlx4_master_func_num(struct mlx4_dev *dev)
764 return dev->caps.function;
767 static inline int mlx4_is_master(struct mlx4_dev *dev)
769 return dev->flags & MLX4_FLAG_MASTER;
772 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
774 return (qpn < dev->phys_caps.base_sqpn + 8 +
775 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev));
778 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
780 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
782 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
788 static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
790 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
793 static inline int mlx4_is_slave(struct mlx4_dev *dev)
795 return dev->flags & MLX4_FLAG_SLAVE;
798 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
799 struct mlx4_buf *buf);
800 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
801 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
803 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
804 return buf->direct.buf + offset;
806 return buf->page_list[offset >> PAGE_SHIFT].buf +
807 (offset & (PAGE_SIZE - 1));
810 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
811 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
812 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
813 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
815 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
816 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
817 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf);
818 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
820 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
821 struct mlx4_mtt *mtt);
822 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
823 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
825 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
826 int npages, int page_shift, struct mlx4_mr *mr);
827 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
828 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
829 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
831 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
832 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
833 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
834 int start_index, int npages, u64 *page_list);
835 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
836 struct mlx4_buf *buf);
838 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
839 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
841 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
842 int size, int max_direct);
843 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
846 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
847 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
848 unsigned vector, int collapsed, int timestamp_en);
849 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
851 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
852 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
854 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
855 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
857 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
858 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
859 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
860 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
861 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
863 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
864 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
866 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
867 int block_mcast_loopback, enum mlx4_protocol prot);
868 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
869 enum mlx4_protocol prot);
870 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
871 u8 port, int block_mcast_loopback,
872 enum mlx4_protocol protocol, u64 *reg_id);
873 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
874 enum mlx4_protocol protocol, u64 reg_id);
877 MLX4_DOMAIN_UVERBS = 0x1000,
878 MLX4_DOMAIN_ETHTOOL = 0x2000,
879 MLX4_DOMAIN_RFS = 0x3000,
880 MLX4_DOMAIN_NIC = 0x5000,
883 enum mlx4_net_trans_rule_id {
884 MLX4_NET_TRANS_RULE_ID_ETH = 0,
885 MLX4_NET_TRANS_RULE_ID_IB,
886 MLX4_NET_TRANS_RULE_ID_IPV6,
887 MLX4_NET_TRANS_RULE_ID_IPV4,
888 MLX4_NET_TRANS_RULE_ID_TCP,
889 MLX4_NET_TRANS_RULE_ID_UDP,
890 MLX4_NET_TRANS_RULE_NUM, /* should be last */
893 extern const u16 __sw_id_hw[];
895 static inline int map_hw_to_sw_id(u16 header_id)
899 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
900 if (header_id == __sw_id_hw[i])
906 enum mlx4_net_trans_promisc_mode {
912 MLX4_FS_MODE_NUM, /* should be last */
915 struct mlx4_spec_eth {
920 u8 ether_type_enable;
926 struct mlx4_spec_tcp_udp {
933 struct mlx4_spec_ipv4 {
940 struct mlx4_spec_ib {
947 struct mlx4_spec_list {
948 struct list_head list;
949 enum mlx4_net_trans_rule_id id;
951 struct mlx4_spec_eth eth;
952 struct mlx4_spec_ib ib;
953 struct mlx4_spec_ipv4 ipv4;
954 struct mlx4_spec_tcp_udp tcp_udp;
958 enum mlx4_net_trans_hw_rule_queue {
959 MLX4_NET_TRANS_Q_FIFO,
960 MLX4_NET_TRANS_Q_LIFO,
963 struct mlx4_net_trans_rule {
964 struct list_head list;
965 enum mlx4_net_trans_hw_rule_queue queue_mode;
968 enum mlx4_net_trans_promisc_mode promisc_mode;
974 struct mlx4_net_trans_rule_hw_ctrl {
986 struct mlx4_net_trans_rule_hw_ib {
997 struct mlx4_net_trans_rule_hw_eth {
1010 u8 ether_type_enable;
1012 __be16 vlan_tag_msk;
1016 struct mlx4_net_trans_rule_hw_tcp_udp {
1023 __be16 dst_port_msk;
1027 __be16 src_port_msk;
1030 struct mlx4_net_trans_rule_hw_ipv4 {
1048 struct mlx4_net_trans_rule_hw_eth eth;
1049 struct mlx4_net_trans_rule_hw_ib ib;
1050 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
1051 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
1055 /* translating DMFS verbs sniffer rule to the FW API would need two reg IDs */
1056 struct mlx4_flow_handle {
1060 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
1061 enum mlx4_net_trans_promisc_mode mode);
1062 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1063 enum mlx4_net_trans_promisc_mode mode);
1064 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1065 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1066 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1067 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1068 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
1070 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1071 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1072 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
1073 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
1074 void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap);
1075 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
1076 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
1077 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
1079 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc);
1080 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
1081 u8 *pg, u16 *ratelimit);
1082 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
1083 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1084 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);
1086 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
1087 int npages, u64 iova, u32 *lkey, u32 *rkey);
1088 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
1089 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
1090 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1091 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
1092 u32 *lkey, u32 *rkey);
1093 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1094 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
1095 int mlx4_test_interrupts(struct mlx4_dev *dev);
1096 int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap,
1098 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
1100 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
1101 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
1103 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
1104 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1106 int mlx4_flow_attach(struct mlx4_dev *dev,
1107 struct mlx4_net_trans_rule *rule, u64 *reg_id);
1108 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
1109 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
1110 enum mlx4_net_trans_promisc_mode flow_type);
1111 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
1112 enum mlx4_net_trans_rule_id id);
1113 int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id);
1115 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
1118 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
1120 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
1121 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
1122 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
1123 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr);
1124 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
1125 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
1126 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
1128 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1129 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1131 cycle_t mlx4_read_clock(struct mlx4_dev *dev);
1133 #endif /* MLX4_DEVICE_H */