2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/pci.h>
37 #include <linux/completion.h>
38 #include <linux/radix-tree.h>
39 #include <linux/cpu_rmap.h>
41 #include <linux/atomic.h>
43 #define MAX_MSIX_P_PORT 17
45 #define MSIX_LEGACY_SZ 4
46 #define MIN_MSIX_P_PORT 5
49 MLX4_FLAG_MSI_X = 1 << 0,
50 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
51 MLX4_FLAG_MASTER = 1 << 2,
52 MLX4_FLAG_SLAVE = 1 << 3,
53 MLX4_FLAG_SRIOV = 1 << 4,
57 MLX4_PORT_CAP_IS_SM = 1 << 1,
58 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
63 MLX4_MAX_PORT_PKEYS = 128
66 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
67 * These qkeys must not be allowed for general use. This is a 64k range,
68 * and to test for violation, we use the mask (protect against future chg).
70 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
71 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
74 MLX4_BOARD_ID_LEN = 64
81 MLX4_MAX_EQ_NUM = 1024,
82 MLX4_MFUNC_EQ_NUM = 4,
83 MLX4_MFUNC_MAX_EQES = 8,
84 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
87 /* Driver supports 3 diffrent device methods to manage traffic steering:
88 * -device managed - High level API for ib and eth flow steering. FW is
89 * managing flow steering tables.
90 * - B0 steering mode - Common low level API for ib and (if supported) eth.
91 * - A0 steering mode - Limited low level API for eth. In case of IB,
95 MLX4_STEERING_MODE_A0,
96 MLX4_STEERING_MODE_B0,
97 MLX4_STEERING_MODE_DEVICE_MANAGED
100 static inline const char *mlx4_steering_mode_str(int steering_mode)
102 switch (steering_mode) {
103 case MLX4_STEERING_MODE_A0:
104 return "A0 steering";
106 case MLX4_STEERING_MODE_B0:
107 return "B0 steering";
109 case MLX4_STEERING_MODE_DEVICE_MANAGED:
110 return "Device managed flow steering";
113 return "Unrecognize steering mode";
118 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
119 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
120 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
121 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
122 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
123 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
124 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
125 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
126 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
127 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
128 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
129 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
130 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
131 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
132 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
133 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
134 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
135 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
136 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
137 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
138 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
139 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
140 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
141 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
142 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
143 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
144 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
145 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
146 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62
150 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
151 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
152 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
153 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
154 MLX4_DEV_CAP_FLAGS2_REASSIGN_MAC_EN = 1LL << 4
158 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
159 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1
163 MLX4_USER_DEV_CAP_64B_CQE = 1L << 0
167 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0
171 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
174 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1,
175 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
176 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
177 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
178 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
179 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
183 MLX4_EVENT_TYPE_COMP = 0x00,
184 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
185 MLX4_EVENT_TYPE_COMM_EST = 0x02,
186 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
187 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
188 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
189 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
190 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
191 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
192 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
193 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
194 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
195 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
196 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
197 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
198 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
199 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
200 MLX4_EVENT_TYPE_CMD = 0x0a,
201 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
202 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
203 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
204 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
205 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
206 MLX4_EVENT_TYPE_NONE = 0xff,
210 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
211 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
215 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
218 enum slave_port_state {
224 enum slave_port_gen_event {
225 SLAVE_PORT_GEN_EVENT_DOWN = 0,
226 SLAVE_PORT_GEN_EVENT_UP,
227 SLAVE_PORT_GEN_EVENT_NONE,
230 enum slave_port_state_event {
231 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
232 MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
233 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
234 MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
238 MLX4_PERM_LOCAL_READ = 1 << 10,
239 MLX4_PERM_LOCAL_WRITE = 1 << 11,
240 MLX4_PERM_REMOTE_READ = 1 << 12,
241 MLX4_PERM_REMOTE_WRITE = 1 << 13,
242 MLX4_PERM_ATOMIC = 1 << 14,
243 MLX4_PERM_BIND_MW = 1 << 15,
247 MLX4_OPCODE_NOP = 0x00,
248 MLX4_OPCODE_SEND_INVAL = 0x01,
249 MLX4_OPCODE_RDMA_WRITE = 0x08,
250 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
251 MLX4_OPCODE_SEND = 0x0a,
252 MLX4_OPCODE_SEND_IMM = 0x0b,
253 MLX4_OPCODE_LSO = 0x0e,
254 MLX4_OPCODE_RDMA_READ = 0x10,
255 MLX4_OPCODE_ATOMIC_CS = 0x11,
256 MLX4_OPCODE_ATOMIC_FA = 0x12,
257 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
258 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
259 MLX4_OPCODE_BIND_MW = 0x18,
260 MLX4_OPCODE_FMR = 0x19,
261 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
262 MLX4_OPCODE_CONFIG_CMD = 0x1f,
264 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
265 MLX4_RECV_OPCODE_SEND = 0x01,
266 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
267 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
269 MLX4_CQE_OPCODE_ERROR = 0x1e,
270 MLX4_CQE_OPCODE_RESIZE = 0x16,
274 MLX4_STAT_RATE_OFFSET = 5
278 MLX4_PROT_IB_IPV6 = 0,
285 MLX4_MTT_FLAG_PRESENT = 1
288 enum mlx4_qp_region {
289 MLX4_QP_REGION_FW = 0,
290 MLX4_QP_REGION_ETH_ADDR,
291 MLX4_QP_REGION_FC_ADDR,
292 MLX4_QP_REGION_FC_EXCH,
296 enum mlx4_port_type {
297 MLX4_PORT_TYPE_NONE = 0,
298 MLX4_PORT_TYPE_IB = 1,
299 MLX4_PORT_TYPE_ETH = 2,
300 MLX4_PORT_TYPE_AUTO = 3
303 enum mlx4_special_vlan_idx {
304 MLX4_NO_VLAN_IDX = 0,
309 enum mlx4_steer_type {
316 MLX4_NUM_FEXCH = 64 * 1024,
320 MLX4_MAX_FAST_REG_PAGES = 511,
324 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
325 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
326 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
329 /* Port mgmt change event handling */
331 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
332 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
333 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
334 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
335 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
338 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
339 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
341 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
343 return (major << 32) | (minor << 16) | subminor;
346 struct mlx4_phys_caps {
347 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
348 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
352 u32 base_tunnel_sqpn;
359 int vl_cap[MLX4_MAX_PORTS + 1];
360 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
361 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
362 u64 def_mac[MLX4_MAX_PORTS + 1];
363 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
364 int gid_table_len[MLX4_MAX_PORTS + 1];
365 int pkey_table_len[MLX4_MAX_PORTS + 1];
366 int trans_type[MLX4_MAX_PORTS + 1];
367 int vendor_oui[MLX4_MAX_PORTS + 1];
368 int wavelength[MLX4_MAX_PORTS + 1];
369 u64 trans_code[MLX4_MAX_PORTS + 1];
370 int local_ca_ack_delay;
374 int bf_regs_per_page;
381 int max_qp_init_rdma;
382 int max_qp_dest_rdma;
396 int num_comp_vectors;
401 int fmr_reserved_mtts;
410 int fs_log_max_ucast_qp_range_size;
422 u16 stat_rate_support;
423 u8 port_width_cap[MLX4_MAX_PORTS + 1];
426 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
428 int reserved_qps_base[MLX4_NUM_QP_REGION];
432 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
433 u8 supported_type[MLX4_MAX_PORTS + 1];
434 u8 suggested_type[MLX4_MAX_PORTS + 1];
435 u8 default_sense[MLX4_MAX_PORTS + 1];
436 u32 port_mask[MLX4_MAX_PORTS + 1];
437 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
439 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
444 u32 userspace_caps; /* userspace must be aware of these */
445 u32 function_caps; /* VFs must be aware of these */
448 struct mlx4_buf_list {
454 struct mlx4_buf_list direct;
455 struct mlx4_buf_list *page_list;
468 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
471 struct mlx4_db_pgdir {
472 struct list_head list;
473 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
474 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
475 unsigned long *bits[2];
480 struct mlx4_ib_user_db_page;
485 struct mlx4_db_pgdir *pgdir;
486 struct mlx4_ib_user_db_page *user_page;
493 struct mlx4_hwq_resources {
517 enum mlx4_mw_type type;
523 struct mlx4_mpt_entry *mpt;
525 dma_addr_t dma_handle;
535 struct list_head bf_list;
536 unsigned free_bf_bmap;
538 void __iomem *bf_map;
542 unsigned long offset;
544 struct mlx4_uar *uar;
549 void (*comp) (struct mlx4_cq *);
550 void (*event) (struct mlx4_cq *, enum mlx4_event);
552 struct mlx4_uar *uar;
564 struct completion free;
568 void (*event) (struct mlx4_qp *, enum mlx4_event);
573 struct completion free;
577 void (*event) (struct mlx4_srq *, enum mlx4_event);
585 struct completion free;
597 __be32 sl_tclass_flowlabel;
610 __be32 sl_tclass_flowlabel;
619 struct mlx4_eth_av eth;
622 struct mlx4_counter {
634 struct pci_dev *pdev;
636 unsigned long num_slaves;
637 struct mlx4_caps caps;
638 struct mlx4_phys_caps phys_caps;
639 struct radix_tree_root qp_table_tree;
641 char board_id[MLX4_BOARD_ID_LEN];
643 int oper_log_mgm_entry_size;
644 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
645 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
681 } __packed port_change;
683 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
685 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
686 } __packed comm_channel_arm;
691 } __packed mac_update;
694 } __packed flr_event;
696 __be16 current_temperature;
697 __be16 warning_threshold;
710 } __packed port_info;
713 __be32 tbl_entries_mask;
714 } __packed tbl_change_info;
716 } __packed port_mgmt_change;
723 struct mlx4_init_port_param {
737 #define mlx4_foreach_port(port, dev, type) \
738 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
739 if ((type) == (dev)->caps.port_mask[(port)])
741 #define mlx4_foreach_non_ib_transport_port(port, dev) \
742 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
743 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB))
745 #define mlx4_foreach_ib_transport_port(port, dev) \
746 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
747 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
748 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
750 #define MLX4_INVALID_SLAVE_ID 0xFF
752 void handle_port_mgmt_change_event(struct work_struct *work);
754 static inline int mlx4_master_func_num(struct mlx4_dev *dev)
756 return dev->caps.function;
759 static inline int mlx4_is_master(struct mlx4_dev *dev)
761 return dev->flags & MLX4_FLAG_MASTER;
764 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
766 return (qpn < dev->phys_caps.base_sqpn + 8 +
767 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev));
770 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
772 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
774 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
780 static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
782 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
785 static inline int mlx4_is_slave(struct mlx4_dev *dev)
787 return dev->flags & MLX4_FLAG_SLAVE;
790 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
791 struct mlx4_buf *buf);
792 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
793 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
795 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
796 return buf->direct.buf + offset;
798 return buf->page_list[offset >> PAGE_SHIFT].buf +
799 (offset & (PAGE_SIZE - 1));
802 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
803 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
804 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
805 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
807 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
808 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
809 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf);
810 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
812 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
813 struct mlx4_mtt *mtt);
814 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
815 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
817 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
818 int npages, int page_shift, struct mlx4_mr *mr);
819 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
820 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
821 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
823 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
824 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
825 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
826 int start_index, int npages, u64 *page_list);
827 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
828 struct mlx4_buf *buf);
830 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
831 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
833 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
834 int size, int max_direct);
835 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
838 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
839 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
840 unsigned vector, int collapsed);
841 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
843 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
844 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
846 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
847 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
849 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
850 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
851 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
852 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
853 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
855 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
856 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
858 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
859 int block_mcast_loopback, enum mlx4_protocol prot);
860 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
861 enum mlx4_protocol prot);
862 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
863 u8 port, int block_mcast_loopback,
864 enum mlx4_protocol protocol, u64 *reg_id);
865 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
866 enum mlx4_protocol protocol, u64 reg_id);
869 MLX4_DOMAIN_UVERBS = 0x1000,
870 MLX4_DOMAIN_ETHTOOL = 0x2000,
871 MLX4_DOMAIN_RFS = 0x3000,
872 MLX4_DOMAIN_NIC = 0x5000,
875 enum mlx4_net_trans_rule_id {
876 MLX4_NET_TRANS_RULE_ID_ETH = 0,
877 MLX4_NET_TRANS_RULE_ID_IB,
878 MLX4_NET_TRANS_RULE_ID_IPV6,
879 MLX4_NET_TRANS_RULE_ID_IPV4,
880 MLX4_NET_TRANS_RULE_ID_TCP,
881 MLX4_NET_TRANS_RULE_ID_UDP,
882 MLX4_NET_TRANS_RULE_NUM, /* should be last */
885 extern const u16 __sw_id_hw[];
887 static inline int map_hw_to_sw_id(u16 header_id)
891 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
892 if (header_id == __sw_id_hw[i])
898 enum mlx4_net_trans_promisc_mode {
899 MLX4_FS_PROMISC_NONE = 0,
900 MLX4_FS_PROMISC_UPLINK,
901 /* For future use. Not implemented yet */
902 MLX4_FS_PROMISC_FUNCTION_PORT,
903 MLX4_FS_PROMISC_ALL_MULTI,
906 struct mlx4_spec_eth {
911 u8 ether_type_enable;
917 struct mlx4_spec_tcp_udp {
924 struct mlx4_spec_ipv4 {
931 struct mlx4_spec_ib {
938 struct mlx4_spec_list {
939 struct list_head list;
940 enum mlx4_net_trans_rule_id id;
942 struct mlx4_spec_eth eth;
943 struct mlx4_spec_ib ib;
944 struct mlx4_spec_ipv4 ipv4;
945 struct mlx4_spec_tcp_udp tcp_udp;
949 enum mlx4_net_trans_hw_rule_queue {
950 MLX4_NET_TRANS_Q_FIFO,
951 MLX4_NET_TRANS_Q_LIFO,
954 struct mlx4_net_trans_rule {
955 struct list_head list;
956 enum mlx4_net_trans_hw_rule_queue queue_mode;
959 enum mlx4_net_trans_promisc_mode promisc_mode;
965 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
966 enum mlx4_net_trans_promisc_mode mode);
967 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
968 enum mlx4_net_trans_promisc_mode mode);
969 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
970 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
971 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
972 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
973 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
975 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
976 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
977 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
978 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
979 void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap);
980 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
981 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
982 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
984 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc);
985 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
986 u8 *pg, u16 *ratelimit);
987 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
988 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
989 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);
991 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
992 int npages, u64 iova, u32 *lkey, u32 *rkey);
993 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
994 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
995 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
996 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
997 u32 *lkey, u32 *rkey);
998 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
999 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
1000 int mlx4_test_interrupts(struct mlx4_dev *dev);
1001 int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap,
1003 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
1005 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
1006 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
1008 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
1009 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1011 int mlx4_flow_attach(struct mlx4_dev *dev,
1012 struct mlx4_net_trans_rule *rule, u64 *reg_id);
1013 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
1015 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
1018 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
1020 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
1021 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
1022 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
1023 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr);
1024 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
1025 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
1026 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
1028 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1029 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1031 #endif /* MLX4_DEVICE_H */