2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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33 #ifndef MLX5_CORE_CQ_H
34 #define MLX5_CORE_CQ_H
36 #include <rdma/ib_verbs.h>
37 #include <linux/mlx5/driver.h>
46 struct completion free;
49 void (*comp) (struct mlx5_core_cq *);
50 void (*event) (struct mlx5_core_cq *, enum mlx5_event);
54 struct mlx5_rsc_debug *dbg;
60 MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR = 0x01,
61 MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR = 0x02,
62 MLX5_CQE_SYNDROME_LOCAL_PROT_ERR = 0x04,
63 MLX5_CQE_SYNDROME_WR_FLUSH_ERR = 0x05,
64 MLX5_CQE_SYNDROME_MW_BIND_ERR = 0x06,
65 MLX5_CQE_SYNDROME_BAD_RESP_ERR = 0x10,
66 MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR = 0x11,
67 MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR = 0x12,
68 MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR = 0x13,
69 MLX5_CQE_SYNDROME_REMOTE_OP_ERR = 0x14,
70 MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR = 0x15,
71 MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR = 0x16,
72 MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR = 0x22,
76 MLX5_CQE_OWNER_MASK = 1,
78 MLX5_CQE_RESP_WR_IMM = 1,
79 MLX5_CQE_RESP_SEND = 2,
80 MLX5_CQE_RESP_SEND_IMM = 3,
81 MLX5_CQE_RESP_SEND_INV = 4,
82 MLX5_CQE_RESIZE_CQ = 5,
83 MLX5_CQE_SIG_ERR = 12,
84 MLX5_CQE_REQ_ERR = 13,
85 MLX5_CQE_RESP_ERR = 14,
86 MLX5_CQE_INVALID = 15,
90 MLX5_CQ_MODIFY_PERIOD = 1 << 0,
91 MLX5_CQ_MODIFY_COUNT = 1 << 1,
92 MLX5_CQ_MODIFY_OVERRUN = 1 << 2,
96 MLX5_CQ_OPMOD_RESIZE = 1,
97 MLX5_MODIFY_CQ_MASK_LOG_SIZE = 1 << 0,
98 MLX5_MODIFY_CQ_MASK_PG_OFFSET = 1 << 1,
99 MLX5_MODIFY_CQ_MASK_PG_SIZE = 1 << 2,
102 struct mlx5_cq_modify_params {
123 static inline int cqe_sz_to_mlx_sz(u8 size)
125 return size == 64 ? CQE_SIZE_64 : CQE_SIZE_128;
128 static inline void mlx5_cq_set_ci(struct mlx5_core_cq *cq)
130 *cq->set_ci_db = cpu_to_be32(cq->cons_index & 0xffffff);
134 MLX5_CQ_DB_REQ_NOT_SOL = 1 << 24,
135 MLX5_CQ_DB_REQ_NOT = 0 << 24
138 static inline void mlx5_cq_arm(struct mlx5_core_cq *cq, u32 cmd,
139 void __iomem *uar_page,
140 spinlock_t *doorbell_lock)
147 ci = cq->cons_index & 0xffffff;
149 *cq->arm_db = cpu_to_be32(sn << 28 | cmd | ci);
151 /* Make sure that the doorbell record in host memory is
152 * written before ringing the doorbell via PCI MMIO.
156 doorbell[0] = cpu_to_be32(sn << 28 | cmd | ci);
157 doorbell[1] = cpu_to_be32(cq->cqn);
159 mlx5_write64(doorbell, uar_page + MLX5_CQ_DOORBELL, doorbell_lock);
162 int mlx5_init_cq_table(struct mlx5_core_dev *dev);
163 void mlx5_cleanup_cq_table(struct mlx5_core_dev *dev);
164 int mlx5_core_create_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
165 struct mlx5_create_cq_mbox_in *in, int inlen);
166 int mlx5_core_destroy_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq);
167 int mlx5_core_query_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
168 struct mlx5_query_cq_mbox_out *out);
169 int mlx5_core_modify_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
170 struct mlx5_modify_cq_mbox_in *in, int in_sz);
171 int mlx5_debug_cq_add(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq);
172 void mlx5_debug_cq_remove(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq);
174 #endif /* MLX5_CORE_CQ_H */