include/linux/mlx5/device.h

   1 /*
   2  * Copyright (c) 2013, Mellanox Technologies inc.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef MLX5_DEVICE_H
  34 #define MLX5_DEVICE_H
  35
  36 #include <linux/types.h>
  37 #include <rdma/ib_verbs.h>
  38
  39 #if defined(__LITTLE_ENDIAN)
  40 #define MLX5_SET_HOST_ENDIANNESS        0
  41 #elif defined(__BIG_ENDIAN)
  42 #define MLX5_SET_HOST_ENDIANNESS        0x80
  43 #else
  44 #error Host endianness not defined
  45 #endif
  46
  47 /* helper macros */
  48 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
  49 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
  50 #define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld)))
  51 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
  52 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
  53 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
  54 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
  55 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
  56 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
  57
  58 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
  59 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
  60 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
  61 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
  62 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
  63
  64 /* insert a value to a struct */
  65 #define MLX5_SET(typ, p, fld, v) do { \
  66         BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32);             \
  67         *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
  68         cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
  69                      (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
  70                      << __mlx5_dw_bit_off(typ, fld))); \
  71 } while (0)
  72
  73 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
  74 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
  75 __mlx5_mask(typ, fld))
  76
  77 #define MLX5_GET_PR(typ, p, fld) ({ \
  78         u32 ___t = MLX5_GET(typ, p, fld); \
  79         pr_debug(#fld " = 0x%x\n", ___t); \
  80         ___t; \
  81 })
  82
  83 #define MLX5_SET64(typ, p, fld, v) do { \
  84         BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
  85         BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
  86         *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
  87 } while (0)
  88
  89 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
  90
  91 enum {
  92         MLX5_MAX_COMMANDS               = 32,
  93         MLX5_CMD_DATA_BLOCK_SIZE        = 512,
  94         MLX5_PCI_CMD_XPORT              = 7,
  95         MLX5_MKEY_BSF_OCTO_SIZE         = 4,
  96         MLX5_MAX_PSVS                   = 4,
  97 };
  98
  99 enum {
 100         MLX5_EXTENDED_UD_AV             = 0x80000000,
 101 };
 102
 103 enum {
 104         MLX5_CQ_STATE_ARMED             = 9,
 105         MLX5_CQ_STATE_ALWAYS_ARMED      = 0xb,
 106         MLX5_CQ_STATE_FIRED             = 0xa,
 107 };
 108
 109 enum {
 110         MLX5_STAT_RATE_OFFSET   = 5,
 111 };
 112
 113 enum {
 114         MLX5_INLINE_SEG = 0x80000000,
 115 };
 116
 117 enum {
 118         MLX5_MIN_PKEY_TABLE_SIZE = 128,
 119         MLX5_MAX_LOG_PKEY_TABLE  = 5,
 120 };
 121
 122 enum {
 123         MLX5_PERM_LOCAL_READ    = 1 << 2,
 124         MLX5_PERM_LOCAL_WRITE   = 1 << 3,
 125         MLX5_PERM_REMOTE_READ   = 1 << 4,
 126         MLX5_PERM_REMOTE_WRITE  = 1 << 5,
 127         MLX5_PERM_ATOMIC        = 1 << 6,
 128         MLX5_PERM_UMR_EN        = 1 << 7,
 129 };
 130
 131 enum {
 132         MLX5_PCIE_CTRL_SMALL_FENCE      = 1 << 0,
 133         MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
 134         MLX5_PCIE_CTRL_NO_SNOOP         = 1 << 3,
 135         MLX5_PCIE_CTRL_TLP_PROCE_EN     = 1 << 6,
 136         MLX5_PCIE_CTRL_TPH_MASK         = 3 << 4,
 137 };
 138
 139 enum {
 140         MLX5_ACCESS_MODE_PA     = 0,
 141         MLX5_ACCESS_MODE_MTT    = 1,
 142         MLX5_ACCESS_MODE_KLM    = 2
 143 };
 144
 145 enum {
 146         MLX5_MKEY_REMOTE_INVAL  = 1 << 24,
 147         MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
 148         MLX5_MKEY_BSF_EN        = 1 << 30,
 149         MLX5_MKEY_LEN64         = 1 << 31,
 150 };
 151
 152 enum {
 153         MLX5_EN_RD      = (u64)1,
 154         MLX5_EN_WR      = (u64)2
 155 };
 156
 157 enum {
 158         MLX5_BF_REGS_PER_PAGE           = 4,
 159         MLX5_MAX_UAR_PAGES              = 1 << 8,
 160         MLX5_NON_FP_BF_REGS_PER_PAGE    = 2,
 161         MLX5_MAX_UUARS  = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
 162 };
 163
 164 enum {
 165         MLX5_MKEY_MASK_LEN              = 1ull << 0,
 166         MLX5_MKEY_MASK_PAGE_SIZE        = 1ull << 1,
 167         MLX5_MKEY_MASK_START_ADDR       = 1ull << 6,
 168         MLX5_MKEY_MASK_PD               = 1ull << 7,
 169         MLX5_MKEY_MASK_EN_RINVAL        = 1ull << 8,
 170         MLX5_MKEY_MASK_EN_SIGERR        = 1ull << 9,
 171         MLX5_MKEY_MASK_BSF_EN           = 1ull << 12,
 172         MLX5_MKEY_MASK_KEY              = 1ull << 13,
 173         MLX5_MKEY_MASK_QPN              = 1ull << 14,
 174         MLX5_MKEY_MASK_LR               = 1ull << 17,
 175         MLX5_MKEY_MASK_LW               = 1ull << 18,
 176         MLX5_MKEY_MASK_RR               = 1ull << 19,
 177         MLX5_MKEY_MASK_RW               = 1ull << 20,
 178         MLX5_MKEY_MASK_A                = 1ull << 21,
 179         MLX5_MKEY_MASK_SMALL_FENCE      = 1ull << 23,
 180         MLX5_MKEY_MASK_FREE             = 1ull << 29,
 181 };
 182
 183 enum mlx5_event {
 184         MLX5_EVENT_TYPE_COMP               = 0x0,
 185
 186         MLX5_EVENT_TYPE_PATH_MIG           = 0x01,
 187         MLX5_EVENT_TYPE_COMM_EST           = 0x02,
 188         MLX5_EVENT_TYPE_SQ_DRAINED         = 0x03,
 189         MLX5_EVENT_TYPE_SRQ_LAST_WQE       = 0x13,
 190         MLX5_EVENT_TYPE_SRQ_RQ_LIMIT       = 0x14,
 191
 192         MLX5_EVENT_TYPE_CQ_ERROR           = 0x04,
 193         MLX5_EVENT_TYPE_WQ_CATAS_ERROR     = 0x05,
 194         MLX5_EVENT_TYPE_PATH_MIG_FAILED    = 0x07,
 195         MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
 196         MLX5_EVENT_TYPE_WQ_ACCESS_ERROR    = 0x11,
 197         MLX5_EVENT_TYPE_SRQ_CATAS_ERROR    = 0x12,
 198
 199         MLX5_EVENT_TYPE_INTERNAL_ERROR     = 0x08,
 200         MLX5_EVENT_TYPE_PORT_CHANGE        = 0x09,
 201         MLX5_EVENT_TYPE_GPIO_EVENT         = 0x15,
 202         MLX5_EVENT_TYPE_REMOTE_CONFIG      = 0x19,
 203
 204         MLX5_EVENT_TYPE_DB_BF_CONGESTION   = 0x1a,
 205         MLX5_EVENT_TYPE_STALL_EVENT        = 0x1b,
 206
 207         MLX5_EVENT_TYPE_CMD                = 0x0a,
 208         MLX5_EVENT_TYPE_PAGE_REQUEST       = 0xb,
 209 };
 210
 211 enum {
 212         MLX5_PORT_CHANGE_SUBTYPE_DOWN           = 1,
 213         MLX5_PORT_CHANGE_SUBTYPE_ACTIVE         = 4,
 214         MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED    = 5,
 215         MLX5_PORT_CHANGE_SUBTYPE_LID            = 6,
 216         MLX5_PORT_CHANGE_SUBTYPE_PKEY           = 7,
 217         MLX5_PORT_CHANGE_SUBTYPE_GUID           = 8,
 218         MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG   = 9,
 219 };
 220
 221 enum {
 222         MLX5_DEV_CAP_FLAG_RC            = 1LL <<  0,
 223         MLX5_DEV_CAP_FLAG_UC            = 1LL <<  1,
 224         MLX5_DEV_CAP_FLAG_UD            = 1LL <<  2,
 225         MLX5_DEV_CAP_FLAG_XRC           = 1LL <<  3,
 226         MLX5_DEV_CAP_FLAG_SRQ           = 1LL <<  6,
 227         MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL <<  8,
 228         MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL <<  9,
 229         MLX5_DEV_CAP_FLAG_APM           = 1LL << 17,
 230         MLX5_DEV_CAP_FLAG_ATOMIC        = 1LL << 18,
 231         MLX5_DEV_CAP_FLAG_BLOCK_MCAST   = 1LL << 23,
 232         MLX5_DEV_CAP_FLAG_ON_DMND_PG    = 1LL << 24,
 233         MLX5_DEV_CAP_FLAG_CQ_MODER      = 1LL << 29,
 234         MLX5_DEV_CAP_FLAG_RESIZE_CQ     = 1LL << 30,
 235         MLX5_DEV_CAP_FLAG_RESIZE_SRQ    = 1LL << 32,
 236         MLX5_DEV_CAP_FLAG_DCT           = 1LL << 37,
 237         MLX5_DEV_CAP_FLAG_REMOTE_FENCE  = 1LL << 38,
 238         MLX5_DEV_CAP_FLAG_TLP_HINTS     = 1LL << 39,
 239         MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
 240         MLX5_DEV_CAP_FLAG_CMDIF_CSUM    = 3LL << 46,
 241 };
 242
 243 enum {
 244         MLX5_OPCODE_NOP                 = 0x00,
 245         MLX5_OPCODE_SEND_INVAL          = 0x01,
 246         MLX5_OPCODE_RDMA_WRITE          = 0x08,
 247         MLX5_OPCODE_RDMA_WRITE_IMM      = 0x09,
 248         MLX5_OPCODE_SEND                = 0x0a,
 249         MLX5_OPCODE_SEND_IMM            = 0x0b,
 250         MLX5_OPCODE_RDMA_READ           = 0x10,
 251         MLX5_OPCODE_ATOMIC_CS           = 0x11,
 252         MLX5_OPCODE_ATOMIC_FA           = 0x12,
 253         MLX5_OPCODE_ATOMIC_MASKED_CS    = 0x14,
 254         MLX5_OPCODE_ATOMIC_MASKED_FA    = 0x15,
 255         MLX5_OPCODE_BIND_MW             = 0x18,
 256         MLX5_OPCODE_CONFIG_CMD          = 0x1f,
 257
 258         MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
 259         MLX5_RECV_OPCODE_SEND           = 0x01,
 260         MLX5_RECV_OPCODE_SEND_IMM       = 0x02,
 261         MLX5_RECV_OPCODE_SEND_INVAL     = 0x03,
 262
 263         MLX5_CQE_OPCODE_ERROR           = 0x1e,
 264         MLX5_CQE_OPCODE_RESIZE          = 0x16,
 265
 266         MLX5_OPCODE_SET_PSV             = 0x20,
 267         MLX5_OPCODE_GET_PSV             = 0x21,
 268         MLX5_OPCODE_CHECK_PSV           = 0x22,
 269         MLX5_OPCODE_RGET_PSV            = 0x26,
 270         MLX5_OPCODE_RCHECK_PSV          = 0x27,
 271
 272         MLX5_OPCODE_UMR                 = 0x25,
 273
 274 };
 275
 276 enum {
 277         MLX5_SET_PORT_RESET_QKEY        = 0,
 278         MLX5_SET_PORT_GUID0             = 16,
 279         MLX5_SET_PORT_NODE_GUID         = 17,
 280         MLX5_SET_PORT_SYS_GUID          = 18,
 281         MLX5_SET_PORT_GID_TABLE         = 19,
 282         MLX5_SET_PORT_PKEY_TABLE        = 20,
 283 };
 284
 285 enum {
 286         MLX5_MAX_PAGE_SHIFT             = 31
 287 };
 288
 289 enum {
 290         MLX5_ADAPTER_PAGE_SHIFT         = 12,
 291         MLX5_ADAPTER_PAGE_SIZE          = 1 << MLX5_ADAPTER_PAGE_SHIFT,
 292 };
 293
 294 enum {
 295         MLX5_CAP_OFF_CMDIF_CSUM         = 46,
 296 };
 297
 298 enum {
 299         HCA_CAP_OPMOD_GET_MAX   = 0,
 300         HCA_CAP_OPMOD_GET_CUR   = 1,
 301 };
 302
 303 struct mlx5_inbox_hdr {
 304         __be16          opcode;
 305         u8              rsvd[4];
 306         __be16          opmod;
 307 };
 308
 309 struct mlx5_outbox_hdr {
 310         u8              status;
 311         u8              rsvd[3];
 312         __be32          syndrome;
 313 };
 314
 315 struct mlx5_cmd_query_adapter_mbox_in {
 316         struct mlx5_inbox_hdr   hdr;
 317         u8                      rsvd[8];
 318 };
 319
 320 struct mlx5_cmd_query_adapter_mbox_out {
 321         struct mlx5_outbox_hdr  hdr;
 322         u8                      rsvd0[24];
 323         u8                      intapin;
 324         u8                      rsvd1[13];
 325         __be16                  vsd_vendor_id;
 326         u8                      vsd[208];
 327         u8                      vsd_psid[16];
 328 };
 329
 330 struct mlx5_hca_cap {
 331         u8      rsvd1[16];
 332         u8      log_max_srq_sz;
 333         u8      log_max_qp_sz;
 334         u8      rsvd2;
 335         u8      log_max_qp;
 336         u8      log_max_strq_sz;
 337         u8      log_max_srqs;
 338         u8      rsvd4[2];
 339         u8      rsvd5;
 340         u8      log_max_cq_sz;
 341         u8      rsvd6;
 342         u8      log_max_cq;
 343         u8      log_max_eq_sz;
 344         u8      log_max_mkey;
 345         u8      rsvd7;
 346         u8      log_max_eq;
 347         u8      max_indirection;
 348         u8      log_max_mrw_sz;
 349         u8      log_max_bsf_list_sz;
 350         u8      log_max_klm_list_sz;
 351         u8      rsvd_8_0;
 352         u8      log_max_ra_req_dc;
 353         u8      rsvd_8_1;
 354         u8      log_max_ra_res_dc;
 355         u8      rsvd9;
 356         u8      log_max_ra_req_qp;
 357         u8      rsvd10;
 358         u8      log_max_ra_res_qp;
 359         u8      pad_cap;
 360         u8      rsvd11[3];
 361         __be16  max_qp_count;
 362         __be16  pkey_table_size;
 363         u8      rsvd13;
 364         u8      local_ca_ack_delay;
 365         u8      rsvd14;
 366         u8      num_ports;
 367         u8      log_max_msg;
 368         u8      rsvd15[3];
 369         __be16  stat_rate_support;
 370         u8      rsvd16[2];
 371         __be64  flags;
 372         u8      rsvd17;
 373         u8      uar_sz;
 374         u8      rsvd18;
 375         u8      log_pg_sz;
 376         __be16  bf_log_bf_reg_size;
 377         u8      rsvd19[4];
 378         __be16  max_desc_sz_sq;
 379         u8      rsvd20[2];
 380         __be16  max_desc_sz_rq;
 381         u8      rsvd21[2];
 382         __be16  max_desc_sz_sq_dc;
 383         __be32  max_qp_mcg;
 384         u8      rsvd22[3];
 385         u8      log_max_mcg;
 386         u8      rsvd23;
 387         u8      log_max_pd;
 388         u8      rsvd24;
 389         u8      log_max_xrcd;
 390         u8      rsvd25[42];
 391         __be16  log_uar_page_sz;
 392         u8      rsvd26[108];
 393 };
 394
 395
 396 struct mlx5_cmd_query_hca_cap_mbox_in {
 397         struct mlx5_inbox_hdr   hdr;
 398         u8                      rsvd[8];
 399 };
 400
 401
 402 struct mlx5_cmd_query_hca_cap_mbox_out {
 403         struct mlx5_outbox_hdr  hdr;
 404         u8                      rsvd0[8];
 405         struct mlx5_hca_cap     hca_cap;
 406 };
 407
 408
 409 struct mlx5_cmd_set_hca_cap_mbox_in {
 410         struct mlx5_inbox_hdr   hdr;
 411         u8                      rsvd[8];
 412         struct mlx5_hca_cap     hca_cap;
 413 };
 414
 415
 416 struct mlx5_cmd_set_hca_cap_mbox_out {
 417         struct mlx5_outbox_hdr  hdr;
 418         u8                      rsvd0[8];
 419 };
 420
 421
 422 struct mlx5_cmd_init_hca_mbox_in {
 423         struct mlx5_inbox_hdr   hdr;
 424         u8                      rsvd0[2];
 425         __be16                  profile;
 426         u8                      rsvd1[4];
 427 };
 428
 429 struct mlx5_cmd_init_hca_mbox_out {
 430         struct mlx5_outbox_hdr  hdr;
 431         u8                      rsvd[8];
 432 };
 433
 434 struct mlx5_cmd_teardown_hca_mbox_in {
 435         struct mlx5_inbox_hdr   hdr;
 436         u8                      rsvd0[2];
 437         __be16                  profile;
 438         u8                      rsvd1[4];
 439 };
 440
 441 struct mlx5_cmd_teardown_hca_mbox_out {
 442         struct mlx5_outbox_hdr  hdr;
 443         u8                      rsvd[8];
 444 };
 445
 446 struct mlx5_cmd_layout {
 447         u8              type;
 448         u8              rsvd0[3];
 449         __be32          inlen;
 450         __be64          in_ptr;
 451         __be32          in[4];
 452         __be32          out[4];
 453         __be64          out_ptr;
 454         __be32          outlen;
 455         u8              token;
 456         u8              sig;
 457         u8              rsvd1;
 458         u8              status_own;
 459 };
 460
 461
 462 struct health_buffer {
 463         __be32          assert_var[5];
 464         __be32          rsvd0[3];
 465         __be32          assert_exit_ptr;
 466         __be32          assert_callra;
 467         __be32          rsvd1[2];
 468         __be32          fw_ver;
 469         __be32          hw_id;
 470         __be32          rsvd2;
 471         u8              irisc_index;
 472         u8              synd;
 473         __be16          ext_sync;
 474 };
 475
 476 struct mlx5_init_seg {
 477         __be32                  fw_rev;
 478         __be32                  cmdif_rev_fw_sub;
 479         __be32                  rsvd0[2];
 480         __be32                  cmdq_addr_h;
 481         __be32                  cmdq_addr_l_sz;
 482         __be32                  cmd_dbell;
 483         __be32                  rsvd1[121];
 484         struct health_buffer    health;
 485         __be32                  rsvd2[884];
 486         __be32                  health_counter;
 487         __be32                  rsvd3[1019];
 488         __be64                  ieee1588_clk;
 489         __be32                  ieee1588_clk_type;
 490         __be32                  clr_intx;
 491 };
 492
 493 struct mlx5_eqe_comp {
 494         __be32  reserved[6];
 495         __be32  cqn;
 496 };
 497
 498 struct mlx5_eqe_qp_srq {
 499         __be32  reserved[6];
 500         __be32  qp_srq_n;
 501 };
 502
 503 struct mlx5_eqe_cq_err {
 504         __be32  cqn;
 505         u8      reserved1[7];
 506         u8      syndrome;
 507 };
 508
 509 struct mlx5_eqe_port_state {
 510         u8      reserved0[8];
 511         u8      port;
 512 };
 513
 514 struct mlx5_eqe_gpio {
 515         __be32  reserved0[2];
 516         __be64  gpio_event;
 517 };
 518
 519 struct mlx5_eqe_congestion {
 520         u8      type;
 521         u8      rsvd0;
 522         u8      congestion_level;
 523 };
 524
 525 struct mlx5_eqe_stall_vl {
 526         u8      rsvd0[3];
 527         u8      port_vl;
 528 };
 529
 530 struct mlx5_eqe_cmd {
 531         __be32  vector;
 532         __be32  rsvd[6];
 533 };
 534
 535 struct mlx5_eqe_page_req {
 536         u8              rsvd0[2];
 537         __be16          func_id;
 538         __be32          num_pages;
 539         __be32          rsvd1[5];
 540 };
 541
 542 union ev_data {
 543         __be32                          raw[7];
 544         struct mlx5_eqe_cmd             cmd;
 545         struct mlx5_eqe_comp            comp;
 546         struct mlx5_eqe_qp_srq          qp_srq;
 547         struct mlx5_eqe_cq_err          cq_err;
 548         struct mlx5_eqe_port_state      port;
 549         struct mlx5_eqe_gpio            gpio;
 550         struct mlx5_eqe_congestion      cong;
 551         struct mlx5_eqe_stall_vl        stall_vl;
 552         struct mlx5_eqe_page_req        req_pages;
 553 } __packed;
 554
 555 struct mlx5_eqe {
 556         u8              rsvd0;
 557         u8              type;
 558         u8              rsvd1;
 559         u8              sub_type;
 560         __be32          rsvd2[7];
 561         union ev_data   data;
 562         __be16          rsvd3;
 563         u8              signature;
 564         u8              owner;
 565 } __packed;
 566
 567 struct mlx5_cmd_prot_block {
 568         u8              data[MLX5_CMD_DATA_BLOCK_SIZE];
 569         u8              rsvd0[48];
 570         __be64          next;
 571         __be32          block_num;
 572         u8              rsvd1;
 573         u8              token;
 574         u8              ctrl_sig;
 575         u8              sig;
 576 };
 577
 578 struct mlx5_err_cqe {
 579         u8      rsvd0[32];
 580         __be32  srqn;
 581         u8      rsvd1[18];
 582         u8      vendor_err_synd;
 583         u8      syndrome;
 584         __be32  s_wqe_opcode_qpn;
 585         __be16  wqe_counter;
 586         u8      signature;
 587         u8      op_own;
 588 };
 589
 590 struct mlx5_cqe64 {
 591         u8              rsvd0[17];
 592         u8              ml_path;
 593         u8              rsvd20[4];
 594         __be16          slid;
 595         __be32          flags_rqpn;
 596         u8              rsvd28[4];
 597         __be32          srqn;
 598         __be32          imm_inval_pkey;
 599         u8              rsvd40[4];
 600         __be32          byte_cnt;
 601         __be64          timestamp;
 602         __be32          sop_drop_qpn;
 603         __be16          wqe_counter;
 604         u8              signature;
 605         u8              op_own;
 606 };
 607
 608 struct mlx5_sig_err_cqe {
 609         u8              rsvd0[16];
 610         __be32          expected_trans_sig;
 611         __be32          actual_trans_sig;
 612         __be32          expected_reftag;
 613         __be32          actual_reftag;
 614         __be16          syndrome;
 615         u8              rsvd22[2];
 616         __be32          mkey;
 617         __be64          err_offset;
 618         u8              rsvd30[8];
 619         __be32          qpn;
 620         u8              rsvd38[2];
 621         u8              signature;
 622         u8              op_own;
 623 };
 624
 625 struct mlx5_wqe_srq_next_seg {
 626         u8                      rsvd0[2];
 627         __be16                  next_wqe_index;
 628         u8                      signature;
 629         u8                      rsvd1[11];
 630 };
 631
 632 union mlx5_ext_cqe {
 633         struct ib_grh   grh;
 634         u8              inl[64];
 635 };
 636
 637 struct mlx5_cqe128 {
 638         union mlx5_ext_cqe      inl_grh;
 639         struct mlx5_cqe64       cqe64;
 640 };
 641
 642 struct mlx5_srq_ctx {
 643         u8                      state_log_sz;
 644         u8                      rsvd0[3];
 645         __be32                  flags_xrcd;
 646         __be32                  pgoff_cqn;
 647         u8                      rsvd1[4];
 648         u8                      log_pg_sz;
 649         u8                      rsvd2[7];
 650         __be32                  pd;
 651         __be16                  lwm;
 652         __be16                  wqe_cnt;
 653         u8                      rsvd3[8];
 654         __be64                  db_record;
 655 };
 656
 657 struct mlx5_create_srq_mbox_in {
 658         struct mlx5_inbox_hdr   hdr;
 659         __be32                  input_srqn;
 660         u8                      rsvd0[4];
 661         struct mlx5_srq_ctx     ctx;
 662         u8                      rsvd1[208];
 663         __be64                  pas[0];
 664 };
 665
 666 struct mlx5_create_srq_mbox_out {
 667         struct mlx5_outbox_hdr  hdr;
 668         __be32                  srqn;
 669         u8                      rsvd[4];
 670 };
 671
 672 struct mlx5_destroy_srq_mbox_in {
 673         struct mlx5_inbox_hdr   hdr;
 674         __be32                  srqn;
 675         u8                      rsvd[4];
 676 };
 677
 678 struct mlx5_destroy_srq_mbox_out {
 679         struct mlx5_outbox_hdr  hdr;
 680         u8                      rsvd[8];
 681 };
 682
 683 struct mlx5_query_srq_mbox_in {
 684         struct mlx5_inbox_hdr   hdr;
 685         __be32                  srqn;
 686         u8                      rsvd0[4];
 687 };
 688
 689 struct mlx5_query_srq_mbox_out {
 690         struct mlx5_outbox_hdr  hdr;
 691         u8                      rsvd0[8];
 692         struct mlx5_srq_ctx     ctx;
 693         u8                      rsvd1[32];
 694         __be64                  pas[0];
 695 };
 696
 697 struct mlx5_arm_srq_mbox_in {
 698         struct mlx5_inbox_hdr   hdr;
 699         __be32                  srqn;
 700         __be16                  rsvd;
 701         __be16                  lwm;
 702 };
 703
 704 struct mlx5_arm_srq_mbox_out {
 705         struct mlx5_outbox_hdr  hdr;
 706         u8                      rsvd[8];
 707 };
 708
 709 struct mlx5_cq_context {
 710         u8                      status;
 711         u8                      cqe_sz_flags;
 712         u8                      st;
 713         u8                      rsvd3;
 714         u8                      rsvd4[6];
 715         __be16                  page_offset;
 716         __be32                  log_sz_usr_page;
 717         __be16                  cq_period;
 718         __be16                  cq_max_count;
 719         __be16                  rsvd20;
 720         __be16                  c_eqn;
 721         u8                      log_pg_sz;
 722         u8                      rsvd25[7];
 723         __be32                  last_notified_index;
 724         __be32                  solicit_producer_index;
 725         __be32                  consumer_counter;
 726         __be32                  producer_counter;
 727         u8                      rsvd48[8];
 728         __be64                  db_record_addr;
 729 };
 730
 731 struct mlx5_create_cq_mbox_in {
 732         struct mlx5_inbox_hdr   hdr;
 733         __be32                  input_cqn;
 734         u8                      rsvdx[4];
 735         struct mlx5_cq_context  ctx;
 736         u8                      rsvd6[192];
 737         __be64                  pas[0];
 738 };
 739
 740 struct mlx5_create_cq_mbox_out {
 741         struct mlx5_outbox_hdr  hdr;
 742         __be32                  cqn;
 743         u8                      rsvd0[4];
 744 };
 745
 746 struct mlx5_destroy_cq_mbox_in {
 747         struct mlx5_inbox_hdr   hdr;
 748         __be32                  cqn;
 749         u8                      rsvd0[4];
 750 };
 751
 752 struct mlx5_destroy_cq_mbox_out {
 753         struct mlx5_outbox_hdr  hdr;
 754         u8                      rsvd0[8];
 755 };
 756
 757 struct mlx5_query_cq_mbox_in {
 758         struct mlx5_inbox_hdr   hdr;
 759         __be32                  cqn;
 760         u8                      rsvd0[4];
 761 };
 762
 763 struct mlx5_query_cq_mbox_out {
 764         struct mlx5_outbox_hdr  hdr;
 765         u8                      rsvd0[8];
 766         struct mlx5_cq_context  ctx;
 767         u8                      rsvd6[16];
 768         __be64                  pas[0];
 769 };
 770
 771 struct mlx5_modify_cq_mbox_in {
 772         struct mlx5_inbox_hdr   hdr;
 773         __be32                  cqn;
 774         __be32                  field_select;
 775         struct mlx5_cq_context  ctx;
 776         u8                      rsvd[192];
 777         __be64                  pas[0];
 778 };
 779
 780 struct mlx5_modify_cq_mbox_out {
 781         struct mlx5_outbox_hdr  hdr;
 782         u8                      rsvd[8];
 783 };
 784
 785 struct mlx5_enable_hca_mbox_in {
 786         struct mlx5_inbox_hdr   hdr;
 787         u8                      rsvd[8];
 788 };
 789
 790 struct mlx5_enable_hca_mbox_out {
 791         struct mlx5_outbox_hdr  hdr;
 792         u8                      rsvd[8];
 793 };
 794
 795 struct mlx5_disable_hca_mbox_in {
 796         struct mlx5_inbox_hdr   hdr;
 797         u8                      rsvd[8];
 798 };
 799
 800 struct mlx5_disable_hca_mbox_out {
 801         struct mlx5_outbox_hdr  hdr;
 802         u8                      rsvd[8];
 803 };
 804
 805 struct mlx5_eq_context {
 806         u8                      status;
 807         u8                      ec_oi;
 808         u8                      st;
 809         u8                      rsvd2[7];
 810         __be16                  page_pffset;
 811         __be32                  log_sz_usr_page;
 812         u8                      rsvd3[7];
 813         u8                      intr;
 814         u8                      log_page_size;
 815         u8                      rsvd4[15];
 816         __be32                  consumer_counter;
 817         __be32                  produser_counter;
 818         u8                      rsvd5[16];
 819 };
 820
 821 struct mlx5_create_eq_mbox_in {
 822         struct mlx5_inbox_hdr   hdr;
 823         u8                      rsvd0[3];
 824         u8                      input_eqn;
 825         u8                      rsvd1[4];
 826         struct mlx5_eq_context  ctx;
 827         u8                      rsvd2[8];
 828         __be64                  events_mask;
 829         u8                      rsvd3[176];
 830         __be64                  pas[0];
 831 };
 832
 833 struct mlx5_create_eq_mbox_out {
 834         struct mlx5_outbox_hdr  hdr;
 835         u8                      rsvd0[3];
 836         u8                      eq_number;
 837         u8                      rsvd1[4];
 838 };
 839
 840 struct mlx5_destroy_eq_mbox_in {
 841         struct mlx5_inbox_hdr   hdr;
 842         u8                      rsvd0[3];
 843         u8                      eqn;
 844         u8                      rsvd1[4];
 845 };
 846
 847 struct mlx5_destroy_eq_mbox_out {
 848         struct mlx5_outbox_hdr  hdr;
 849         u8                      rsvd[8];
 850 };
 851
 852 struct mlx5_map_eq_mbox_in {
 853         struct mlx5_inbox_hdr   hdr;
 854         __be64                  mask;
 855         u8                      mu;
 856         u8                      rsvd0[2];
 857         u8                      eqn;
 858         u8                      rsvd1[24];
 859 };
 860
 861 struct mlx5_map_eq_mbox_out {
 862         struct mlx5_outbox_hdr  hdr;
 863         u8                      rsvd[8];
 864 };
 865
 866 struct mlx5_query_eq_mbox_in {
 867         struct mlx5_inbox_hdr   hdr;
 868         u8                      rsvd0[3];
 869         u8                      eqn;
 870         u8                      rsvd1[4];
 871 };
 872
 873 struct mlx5_query_eq_mbox_out {
 874         struct mlx5_outbox_hdr  hdr;
 875         u8                      rsvd[8];
 876         struct mlx5_eq_context  ctx;
 877 };
 878
 879 struct mlx5_mkey_seg {
 880         /* This is a two bit field occupying bits 31-30.
 881          * bit 31 is always 0,
 882          * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
 883          */
 884         u8              status;
 885         u8              pcie_control;
 886         u8              flags;
 887         u8              version;
 888         __be32          qpn_mkey7_0;
 889         u8              rsvd1[4];
 890         __be32          flags_pd;
 891         __be64          start_addr;
 892         __be64          len;
 893         __be32          bsfs_octo_size;
 894         u8              rsvd2[16];
 895         __be32          xlt_oct_size;
 896         u8              rsvd3[3];
 897         u8              log2_page_size;
 898         u8              rsvd4[4];
 899 };
 900
 901 struct mlx5_query_special_ctxs_mbox_in {
 902         struct mlx5_inbox_hdr   hdr;
 903         u8                      rsvd[8];
 904 };
 905
 906 struct mlx5_query_special_ctxs_mbox_out {
 907         struct mlx5_outbox_hdr  hdr;
 908         __be32                  dump_fill_mkey;
 909         __be32                  reserved_lkey;
 910 };
 911
 912 struct mlx5_create_mkey_mbox_in {
 913         struct mlx5_inbox_hdr   hdr;
 914         __be32                  input_mkey_index;
 915         u8                      rsvd0[4];
 916         struct mlx5_mkey_seg    seg;
 917         u8                      rsvd1[16];
 918         __be32                  xlat_oct_act_size;
 919         __be32                  rsvd2;
 920         u8                      rsvd3[168];
 921         __be64                  pas[0];
 922 };
 923
 924 struct mlx5_create_mkey_mbox_out {
 925         struct mlx5_outbox_hdr  hdr;
 926         __be32                  mkey;
 927         u8                      rsvd[4];
 928 };
 929
 930 struct mlx5_destroy_mkey_mbox_in {
 931         struct mlx5_inbox_hdr   hdr;
 932         __be32                  mkey;
 933         u8                      rsvd[4];
 934 };
 935
 936 struct mlx5_destroy_mkey_mbox_out {
 937         struct mlx5_outbox_hdr  hdr;
 938         u8                      rsvd[8];
 939 };
 940
 941 struct mlx5_query_mkey_mbox_in {
 942         struct mlx5_inbox_hdr   hdr;
 943         __be32                  mkey;
 944 };
 945
 946 struct mlx5_query_mkey_mbox_out {
 947         struct mlx5_outbox_hdr  hdr;
 948         __be64                  pas[0];
 949 };
 950
 951 struct mlx5_modify_mkey_mbox_in {
 952         struct mlx5_inbox_hdr   hdr;
 953         __be32                  mkey;
 954         __be64                  pas[0];
 955 };
 956
 957 struct mlx5_modify_mkey_mbox_out {
 958         struct mlx5_outbox_hdr  hdr;
 959         u8                      rsvd[8];
 960 };
 961
 962 struct mlx5_dump_mkey_mbox_in {
 963         struct mlx5_inbox_hdr   hdr;
 964 };
 965
 966 struct mlx5_dump_mkey_mbox_out {
 967         struct mlx5_outbox_hdr  hdr;
 968         __be32                  mkey;
 969 };
 970
 971 struct mlx5_mad_ifc_mbox_in {
 972         struct mlx5_inbox_hdr   hdr;
 973         __be16                  remote_lid;
 974         u8                      rsvd0;
 975         u8                      port;
 976         u8                      rsvd1[4];
 977         u8                      data[256];
 978 };
 979
 980 struct mlx5_mad_ifc_mbox_out {
 981         struct mlx5_outbox_hdr  hdr;
 982         u8                      rsvd[8];
 983         u8                      data[256];
 984 };
 985
 986 struct mlx5_access_reg_mbox_in {
 987         struct mlx5_inbox_hdr           hdr;
 988         u8                              rsvd0[2];
 989         __be16                          register_id;
 990         __be32                          arg;
 991         __be32                          data[0];
 992 };
 993
 994 struct mlx5_access_reg_mbox_out {
 995         struct mlx5_outbox_hdr          hdr;
 996         u8                              rsvd[8];
 997         __be32                          data[0];
 998 };
 999
1000 #define MLX5_ATTR_EXTENDED_PORT_INFO    cpu_to_be16(0xff90)
1001
1002 enum {
1003         MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO        = 1 <<  0
1004 };
1005
1006 struct mlx5_allocate_psv_in {
1007         struct mlx5_inbox_hdr   hdr;
1008         __be32                  npsv_pd;
1009         __be32                  rsvd_psv0;
1010 };
1011
1012 struct mlx5_allocate_psv_out {
1013         struct mlx5_outbox_hdr  hdr;
1014         u8                      rsvd[8];
1015         __be32                  psv_idx[4];
1016 };
1017
1018 struct mlx5_destroy_psv_in {
1019         struct mlx5_inbox_hdr   hdr;
1020         __be32                  psv_number;
1021         u8                      rsvd[4];
1022 };
1023
1024 struct mlx5_destroy_psv_out {
1025         struct mlx5_outbox_hdr  hdr;
1026         u8                      rsvd[8];
1027 };
1028
1029 #endif /* MLX5_DEVICE_H */