2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/types.h>
37 #include <rdma/ib_verbs.h>
39 #if defined(__LITTLE_ENDIAN)
40 #define MLX5_SET_HOST_ENDIANNESS 0
41 #elif defined(__BIG_ENDIAN)
42 #define MLX5_SET_HOST_ENDIANNESS 0x80
44 #error Host endianness not defined
48 MLX5_MAX_COMMANDS = 32,
49 MLX5_CMD_DATA_BLOCK_SIZE = 512,
50 MLX5_PCI_CMD_XPORT = 7,
51 MLX5_MKEY_BSF_OCTO_SIZE = 4,
56 MLX5_EXTENDED_UD_AV = 0x80000000,
60 MLX5_CQ_STATE_ARMED = 9,
61 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
62 MLX5_CQ_STATE_FIRED = 0xa,
66 MLX5_STAT_RATE_OFFSET = 5,
70 MLX5_INLINE_SEG = 0x80000000,
74 MLX5_PERM_LOCAL_READ = 1 << 2,
75 MLX5_PERM_LOCAL_WRITE = 1 << 3,
76 MLX5_PERM_REMOTE_READ = 1 << 4,
77 MLX5_PERM_REMOTE_WRITE = 1 << 5,
78 MLX5_PERM_ATOMIC = 1 << 6,
79 MLX5_PERM_UMR_EN = 1 << 7,
83 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
84 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
85 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
86 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
87 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
91 MLX5_ACCESS_MODE_PA = 0,
92 MLX5_ACCESS_MODE_MTT = 1,
93 MLX5_ACCESS_MODE_KLM = 2
97 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
98 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
99 MLX5_MKEY_BSF_EN = 1 << 30,
100 MLX5_MKEY_LEN64 = 1 << 31,
109 MLX5_BF_REGS_PER_PAGE = 4,
110 MLX5_MAX_UAR_PAGES = 1 << 8,
111 MLX5_NON_FP_BF_REGS_PER_PAGE = 2,
112 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
116 MLX5_MKEY_MASK_LEN = 1ull << 0,
117 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
118 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
119 MLX5_MKEY_MASK_PD = 1ull << 7,
120 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
121 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
122 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
123 MLX5_MKEY_MASK_KEY = 1ull << 13,
124 MLX5_MKEY_MASK_QPN = 1ull << 14,
125 MLX5_MKEY_MASK_LR = 1ull << 17,
126 MLX5_MKEY_MASK_LW = 1ull << 18,
127 MLX5_MKEY_MASK_RR = 1ull << 19,
128 MLX5_MKEY_MASK_RW = 1ull << 20,
129 MLX5_MKEY_MASK_A = 1ull << 21,
130 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
131 MLX5_MKEY_MASK_FREE = 1ull << 29,
135 MLX5_EVENT_TYPE_COMP = 0x0,
137 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
138 MLX5_EVENT_TYPE_COMM_EST = 0x02,
139 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
140 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
141 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
143 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
144 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
145 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
146 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
147 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
148 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
150 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
151 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
152 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
153 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
155 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
156 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
158 MLX5_EVENT_TYPE_CMD = 0x0a,
159 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
163 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
164 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
165 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
166 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
167 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
168 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
169 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
173 MLX5_DEV_CAP_FLAG_RC = 1LL << 0,
174 MLX5_DEV_CAP_FLAG_UC = 1LL << 1,
175 MLX5_DEV_CAP_FLAG_UD = 1LL << 2,
176 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
177 MLX5_DEV_CAP_FLAG_SRQ = 1LL << 6,
178 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
179 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
180 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
181 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
182 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
183 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
184 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
185 MLX5_DEV_CAP_FLAG_RESIZE_SRQ = 1LL << 32,
186 MLX5_DEV_CAP_FLAG_REMOTE_FENCE = 1LL << 38,
187 MLX5_DEV_CAP_FLAG_TLP_HINTS = 1LL << 39,
188 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
189 MLX5_DEV_CAP_FLAG_DCT = 1LL << 41,
190 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
194 MLX5_OPCODE_NOP = 0x00,
195 MLX5_OPCODE_SEND_INVAL = 0x01,
196 MLX5_OPCODE_RDMA_WRITE = 0x08,
197 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
198 MLX5_OPCODE_SEND = 0x0a,
199 MLX5_OPCODE_SEND_IMM = 0x0b,
200 MLX5_OPCODE_RDMA_READ = 0x10,
201 MLX5_OPCODE_ATOMIC_CS = 0x11,
202 MLX5_OPCODE_ATOMIC_FA = 0x12,
203 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
204 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
205 MLX5_OPCODE_BIND_MW = 0x18,
206 MLX5_OPCODE_CONFIG_CMD = 0x1f,
208 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
209 MLX5_RECV_OPCODE_SEND = 0x01,
210 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
211 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
213 MLX5_CQE_OPCODE_ERROR = 0x1e,
214 MLX5_CQE_OPCODE_RESIZE = 0x16,
216 MLX5_OPCODE_SET_PSV = 0x20,
217 MLX5_OPCODE_GET_PSV = 0x21,
218 MLX5_OPCODE_CHECK_PSV = 0x22,
219 MLX5_OPCODE_RGET_PSV = 0x26,
220 MLX5_OPCODE_RCHECK_PSV = 0x27,
222 MLX5_OPCODE_UMR = 0x25,
227 MLX5_SET_PORT_RESET_QKEY = 0,
228 MLX5_SET_PORT_GUID0 = 16,
229 MLX5_SET_PORT_NODE_GUID = 17,
230 MLX5_SET_PORT_SYS_GUID = 18,
231 MLX5_SET_PORT_GID_TABLE = 19,
232 MLX5_SET_PORT_PKEY_TABLE = 20,
236 MLX5_MAX_PAGE_SHIFT = 31
240 MLX5_ADAPTER_PAGE_SHIFT = 12,
241 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
245 MLX5_CAP_OFF_DCT = 41,
246 MLX5_CAP_OFF_CMDIF_CSUM = 46,
249 struct mlx5_inbox_hdr {
255 struct mlx5_outbox_hdr {
261 struct mlx5_cmd_query_adapter_mbox_in {
262 struct mlx5_inbox_hdr hdr;
266 struct mlx5_cmd_query_adapter_mbox_out {
267 struct mlx5_outbox_hdr hdr;
271 __be16 vsd_vendor_id;
276 struct mlx5_hca_cap {
295 u8 log_max_bsf_list_sz;
296 u8 log_max_klm_list_sz;
298 u8 log_max_ra_req_dc;
300 u8 log_max_ra_res_dc;
302 u8 log_max_ra_req_qp;
304 u8 log_max_ra_res_qp;
309 u8 local_ca_ack_delay;
314 __be16 stat_rate_support;
321 __be16 bf_log_bf_reg_size;
323 __be16 max_desc_sz_sq;
325 __be16 max_desc_sz_rq;
327 __be16 max_desc_sz_sq_dc;
336 __be16 log_uar_page_sz;
338 u8 log_max_atomic_size_qp;
340 u8 log_max_atomic_size_dc;
345 struct mlx5_cmd_query_hca_cap_mbox_in {
346 struct mlx5_inbox_hdr hdr;
351 struct mlx5_cmd_query_hca_cap_mbox_out {
352 struct mlx5_outbox_hdr hdr;
354 struct mlx5_hca_cap hca_cap;
358 struct mlx5_cmd_set_hca_cap_mbox_in {
359 struct mlx5_inbox_hdr hdr;
361 struct mlx5_hca_cap hca_cap;
365 struct mlx5_cmd_set_hca_cap_mbox_out {
366 struct mlx5_outbox_hdr hdr;
371 struct mlx5_cmd_init_hca_mbox_in {
372 struct mlx5_inbox_hdr hdr;
378 struct mlx5_cmd_init_hca_mbox_out {
379 struct mlx5_outbox_hdr hdr;
383 struct mlx5_cmd_teardown_hca_mbox_in {
384 struct mlx5_inbox_hdr hdr;
390 struct mlx5_cmd_teardown_hca_mbox_out {
391 struct mlx5_outbox_hdr hdr;
395 struct mlx5_cmd_layout {
411 struct health_buffer {
412 __be32 assert_var[5];
414 __be32 assert_exit_ptr;
415 __be32 assert_callra;
425 struct mlx5_init_seg {
427 __be32 cmdif_rev_fw_sub;
430 __be32 cmdq_addr_l_sz;
433 struct health_buffer health;
435 __be32 health_counter;
438 __be32 ieee1588_clk_type;
442 struct mlx5_eqe_comp {
447 struct mlx5_eqe_qp_srq {
452 struct mlx5_eqe_cq_err {
458 struct mlx5_eqe_dropped_packet {
461 struct mlx5_eqe_port_state {
466 struct mlx5_eqe_gpio {
471 struct mlx5_eqe_congestion {
477 struct mlx5_eqe_stall_vl {
482 struct mlx5_eqe_cmd {
487 struct mlx5_eqe_page_req {
496 struct mlx5_eqe_cmd cmd;
497 struct mlx5_eqe_comp comp;
498 struct mlx5_eqe_qp_srq qp_srq;
499 struct mlx5_eqe_cq_err cq_err;
500 struct mlx5_eqe_dropped_packet dp;
501 struct mlx5_eqe_port_state port;
502 struct mlx5_eqe_gpio gpio;
503 struct mlx5_eqe_congestion cong;
504 struct mlx5_eqe_stall_vl stall_vl;
505 struct mlx5_eqe_page_req req_pages;
520 struct mlx5_cmd_prot_block {
521 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
531 struct mlx5_err_cqe {
537 __be32 s_wqe_opcode_qpn;
551 __be32 imm_inval_pkey;
561 struct mlx5_sig_err_cqe {
563 __be32 expected_trans_sig;
564 __be32 actual_trans_sig;
565 __be32 expected_reftag;
566 __be32 actual_reftag;
578 struct mlx5_wqe_srq_next_seg {
580 __be16 next_wqe_index;
591 union mlx5_ext_cqe inl_grh;
592 struct mlx5_cqe64 cqe64;
595 struct mlx5_srq_ctx {
610 struct mlx5_create_srq_mbox_in {
611 struct mlx5_inbox_hdr hdr;
614 struct mlx5_srq_ctx ctx;
619 struct mlx5_create_srq_mbox_out {
620 struct mlx5_outbox_hdr hdr;
625 struct mlx5_destroy_srq_mbox_in {
626 struct mlx5_inbox_hdr hdr;
631 struct mlx5_destroy_srq_mbox_out {
632 struct mlx5_outbox_hdr hdr;
636 struct mlx5_query_srq_mbox_in {
637 struct mlx5_inbox_hdr hdr;
642 struct mlx5_query_srq_mbox_out {
643 struct mlx5_outbox_hdr hdr;
645 struct mlx5_srq_ctx ctx;
650 struct mlx5_arm_srq_mbox_in {
651 struct mlx5_inbox_hdr hdr;
657 struct mlx5_arm_srq_mbox_out {
658 struct mlx5_outbox_hdr hdr;
662 struct mlx5_cq_context {
669 __be32 log_sz_usr_page;
676 __be32 last_notified_index;
677 __be32 solicit_producer_index;
678 __be32 consumer_counter;
679 __be32 producer_counter;
681 __be64 db_record_addr;
684 struct mlx5_create_cq_mbox_in {
685 struct mlx5_inbox_hdr hdr;
688 struct mlx5_cq_context ctx;
693 struct mlx5_create_cq_mbox_out {
694 struct mlx5_outbox_hdr hdr;
699 struct mlx5_destroy_cq_mbox_in {
700 struct mlx5_inbox_hdr hdr;
705 struct mlx5_destroy_cq_mbox_out {
706 struct mlx5_outbox_hdr hdr;
710 struct mlx5_query_cq_mbox_in {
711 struct mlx5_inbox_hdr hdr;
716 struct mlx5_query_cq_mbox_out {
717 struct mlx5_outbox_hdr hdr;
719 struct mlx5_cq_context ctx;
724 struct mlx5_modify_cq_mbox_in {
725 struct mlx5_inbox_hdr hdr;
728 struct mlx5_cq_context ctx;
733 struct mlx5_modify_cq_mbox_out {
734 struct mlx5_outbox_hdr hdr;
738 struct mlx5_enable_hca_mbox_in {
739 struct mlx5_inbox_hdr hdr;
743 struct mlx5_enable_hca_mbox_out {
744 struct mlx5_outbox_hdr hdr;
748 struct mlx5_disable_hca_mbox_in {
749 struct mlx5_inbox_hdr hdr;
753 struct mlx5_disable_hca_mbox_out {
754 struct mlx5_outbox_hdr hdr;
758 struct mlx5_eq_context {
764 __be32 log_sz_usr_page;
769 __be32 consumer_counter;
770 __be32 produser_counter;
774 struct mlx5_create_eq_mbox_in {
775 struct mlx5_inbox_hdr hdr;
779 struct mlx5_eq_context ctx;
786 struct mlx5_create_eq_mbox_out {
787 struct mlx5_outbox_hdr hdr;
793 struct mlx5_destroy_eq_mbox_in {
794 struct mlx5_inbox_hdr hdr;
800 struct mlx5_destroy_eq_mbox_out {
801 struct mlx5_outbox_hdr hdr;
805 struct mlx5_map_eq_mbox_in {
806 struct mlx5_inbox_hdr hdr;
814 struct mlx5_map_eq_mbox_out {
815 struct mlx5_outbox_hdr hdr;
819 struct mlx5_query_eq_mbox_in {
820 struct mlx5_inbox_hdr hdr;
826 struct mlx5_query_eq_mbox_out {
827 struct mlx5_outbox_hdr hdr;
829 struct mlx5_eq_context ctx;
832 struct mlx5_mkey_seg {
833 /* This is a two bit field occupying bits 31-30.
834 * bit 31 is always 0,
835 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
846 __be32 bsfs_octo_size;
854 struct mlx5_query_special_ctxs_mbox_in {
855 struct mlx5_inbox_hdr hdr;
859 struct mlx5_query_special_ctxs_mbox_out {
860 struct mlx5_outbox_hdr hdr;
861 __be32 dump_fill_mkey;
862 __be32 reserved_lkey;
865 struct mlx5_create_mkey_mbox_in {
866 struct mlx5_inbox_hdr hdr;
867 __be32 input_mkey_index;
869 struct mlx5_mkey_seg seg;
871 __be32 xlat_oct_act_size;
877 struct mlx5_create_mkey_mbox_out {
878 struct mlx5_outbox_hdr hdr;
883 struct mlx5_destroy_mkey_mbox_in {
884 struct mlx5_inbox_hdr hdr;
889 struct mlx5_destroy_mkey_mbox_out {
890 struct mlx5_outbox_hdr hdr;
894 struct mlx5_query_mkey_mbox_in {
895 struct mlx5_inbox_hdr hdr;
899 struct mlx5_query_mkey_mbox_out {
900 struct mlx5_outbox_hdr hdr;
904 struct mlx5_modify_mkey_mbox_in {
905 struct mlx5_inbox_hdr hdr;
910 struct mlx5_modify_mkey_mbox_out {
911 struct mlx5_outbox_hdr hdr;
915 struct mlx5_dump_mkey_mbox_in {
916 struct mlx5_inbox_hdr hdr;
919 struct mlx5_dump_mkey_mbox_out {
920 struct mlx5_outbox_hdr hdr;
924 struct mlx5_mad_ifc_mbox_in {
925 struct mlx5_inbox_hdr hdr;
933 struct mlx5_mad_ifc_mbox_out {
934 struct mlx5_outbox_hdr hdr;
939 struct mlx5_access_reg_mbox_in {
940 struct mlx5_inbox_hdr hdr;
947 struct mlx5_access_reg_mbox_out {
948 struct mlx5_outbox_hdr hdr;
953 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
956 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
959 struct mlx5_allocate_psv_in {
960 struct mlx5_inbox_hdr hdr;
965 struct mlx5_allocate_psv_out {
966 struct mlx5_outbox_hdr hdr;
971 struct mlx5_destroy_psv_in {
972 struct mlx5_inbox_hdr hdr;
977 struct mlx5_destroy_psv_out {
978 struct mlx5_outbox_hdr hdr;
982 #endif /* MLX5_DEVICE_H */