2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/mlx5/device.h>
37 #include <linux/mlx5/driver.h>
39 #define MLX5_INVALID_LKEY 0x100
40 #define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 5)
41 #define MLX5_DIF_SIZE 8
42 #define MLX5_STRIDE_BLOCK_OP 0x400
43 #define MLX5_CPY_GRD_MASK 0xc0
44 #define MLX5_CPY_APP_MASK 0x30
45 #define MLX5_CPY_REF_MASK 0x0f
46 #define MLX5_BSF_INC_REFTAG (1 << 6)
47 #define MLX5_BSF_INL_VALID (1 << 15)
48 #define MLX5_BSF_REFRESH_DIF (1 << 14)
49 #define MLX5_BSF_REPEAT_BLOCK (1 << 7)
50 #define MLX5_BSF_APPTAG_ESCAPE 0x1
51 #define MLX5_BSF_APPREF_ESCAPE 0x2
54 MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
55 MLX5_QP_OPTPAR_RRE = 1 << 1,
56 MLX5_QP_OPTPAR_RAE = 1 << 2,
57 MLX5_QP_OPTPAR_RWE = 1 << 3,
58 MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4,
59 MLX5_QP_OPTPAR_Q_KEY = 1 << 5,
60 MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
61 MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
62 MLX5_QP_OPTPAR_SRA_MAX = 1 << 8,
63 MLX5_QP_OPTPAR_RRA_MAX = 1 << 9,
64 MLX5_QP_OPTPAR_PM_STATE = 1 << 10,
65 MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12,
66 MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13,
67 MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
68 MLX5_QP_OPTPAR_PRI_PORT = 1 << 16,
69 MLX5_QP_OPTPAR_SRQN = 1 << 18,
70 MLX5_QP_OPTPAR_CQN_RCV = 1 << 19,
71 MLX5_QP_OPTPAR_DC_HS = 1 << 20,
72 MLX5_QP_OPTPAR_DC_KEY = 1 << 21,
76 MLX5_QP_STATE_RST = 0,
77 MLX5_QP_STATE_INIT = 1,
78 MLX5_QP_STATE_RTR = 2,
79 MLX5_QP_STATE_RTS = 3,
80 MLX5_QP_STATE_SQER = 4,
81 MLX5_QP_STATE_SQD = 5,
82 MLX5_QP_STATE_ERR = 6,
83 MLX5_QP_STATE_SQ_DRAINING = 7,
84 MLX5_QP_STATE_SUSPENDED = 9,
98 MLX5_QP_ST_RAW_ETHERTYPE = 0x9,
99 MLX5_QP_ST_RAW_IPV6 = 0xa,
100 MLX5_QP_ST_SNIFFER = 0xb,
101 MLX5_QP_ST_SYNC_UMR = 0xe,
102 MLX5_QP_ST_PTP_1588 = 0xd,
103 MLX5_QP_ST_REG_UMR = 0xc,
108 MLX5_QP_PM_MIGRATED = 0x3,
109 MLX5_QP_PM_ARMED = 0x0,
110 MLX5_QP_PM_REARM = 0x1
114 MLX5_NON_ZERO_RQ = 0 << 24,
115 MLX5_SRQ_RQ = 1 << 24,
116 MLX5_CRQ_RQ = 2 << 24,
117 MLX5_ZERO_LEN_RQ = 3 << 24
122 MLX5_QP_BIT_SRE = 1 << 15,
123 MLX5_QP_BIT_SWE = 1 << 14,
124 MLX5_QP_BIT_SAE = 1 << 13,
126 MLX5_QP_BIT_RRE = 1 << 15,
127 MLX5_QP_BIT_RWE = 1 << 14,
128 MLX5_QP_BIT_RAE = 1 << 13,
129 MLX5_QP_BIT_RIC = 1 << 4,
133 MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2,
134 MLX5_WQE_CTRL_SOLICITED = 1 << 1,
138 MLX5_SEND_WQE_BB = 64,
142 MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27,
143 MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28,
144 MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29,
145 MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30,
146 MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31
150 MLX5_FENCE_MODE_NONE = 0 << 5,
151 MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5,
152 MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5,
153 MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5,
157 MLX5_QP_LAT_SENSITIVE = 1 << 28,
158 MLX5_QP_BLOCK_MCAST = 1 << 30,
159 MLX5_QP_ENABLE_SIG = 1 << 31,
168 MLX5_FLAGS_INLINE = 1<<7,
169 MLX5_FLAGS_CHECK_FREE = 1<<5,
172 struct mlx5_wqe_fmr_seg {
183 struct mlx5_wqe_ctrl_seg {
184 __be32 opmod_idx_opcode;
192 struct mlx5_wqe_xrc_seg {
197 struct mlx5_wqe_masked_atomic_seg {
200 __be64 swap_add_mask;
223 struct mlx5_wqe_datagram_seg {
227 struct mlx5_wqe_raddr_seg {
233 struct mlx5_wqe_atomic_seg {
238 struct mlx5_wqe_data_seg {
244 struct mlx5_wqe_umr_ctrl_seg {
247 __be16 klm_octowords;
248 __be16 bsf_octowords;
253 struct mlx5_seg_set_psv {
257 __be32 transient_sig;
261 struct mlx5_seg_get_psv {
269 struct mlx5_seg_check_psv {
271 __be16 err_coalescing_op;
275 __be16 xport_err_mask;
283 struct mlx5_rwqe_sig {
289 struct mlx5_wqe_signature_seg {
295 struct mlx5_wqe_inline_seg {
304 struct mlx5_bsf_inl {
311 u8 dif_inc_ref_guard_check;
312 __be16 dif_app_bitmask_check;
316 struct mlx5_bsf_basic {
328 __be32 raw_data_size;
332 struct mlx5_bsf_ext {
333 __be32 t_init_gen_pro_size;
334 __be32 rsvd_epi_size;
338 struct mlx5_bsf_inl w_inl;
339 struct mlx5_bsf_inl m_inl;
348 struct mlx5_stride_block_entry {
355 struct mlx5_stride_block_ctrl_seg {
356 __be32 bcount_per_cycle;
363 struct mlx5_core_qp {
364 struct mlx5_core_rsc_common common; /* must be first */
365 void (*event) (struct mlx5_core_qp *, int);
367 struct mlx5_rsc_debug *dbg;
371 struct mlx5_qp_path {
383 __be32 tclass_flowlabel;
391 struct mlx5_qp_context {
397 __be32 qp_counter_set_usr_page;
399 __be32 log_pg_sz_remote_qpn;
400 struct mlx5_qp_path pri_path;
401 struct mlx5_qp_path alt_path;
404 __be32 next_send_psn;
407 __be32 last_acked_psn;
410 __be32 rnr_nextrecvpsn;
417 __be16 hw_sq_wqe_counter;
418 __be16 sw_sq_wqe_counter;
419 __be16 hw_rcyclic_byte_counter;
420 __be16 hw_rq_counter;
421 __be16 sw_rcyclic_byte_counter;
422 __be16 sw_rq_counter;
427 __be64 dc_access_key;
431 struct mlx5_create_qp_mbox_in {
432 struct mlx5_inbox_hdr hdr;
435 __be32 opt_param_mask;
437 struct mlx5_qp_context ctx;
442 struct mlx5_create_qp_mbox_out {
443 struct mlx5_outbox_hdr hdr;
448 struct mlx5_destroy_qp_mbox_in {
449 struct mlx5_inbox_hdr hdr;
454 struct mlx5_destroy_qp_mbox_out {
455 struct mlx5_outbox_hdr hdr;
459 struct mlx5_modify_qp_mbox_in {
460 struct mlx5_inbox_hdr hdr;
465 struct mlx5_qp_context ctx;
468 struct mlx5_modify_qp_mbox_out {
469 struct mlx5_outbox_hdr hdr;
473 struct mlx5_query_qp_mbox_in {
474 struct mlx5_inbox_hdr hdr;
479 struct mlx5_query_qp_mbox_out {
480 struct mlx5_outbox_hdr hdr;
484 struct mlx5_qp_context ctx;
489 struct mlx5_conf_sqp_mbox_in {
490 struct mlx5_inbox_hdr hdr;
496 struct mlx5_conf_sqp_mbox_out {
497 struct mlx5_outbox_hdr hdr;
501 struct mlx5_alloc_xrcd_mbox_in {
502 struct mlx5_inbox_hdr hdr;
506 struct mlx5_alloc_xrcd_mbox_out {
507 struct mlx5_outbox_hdr hdr;
512 struct mlx5_dealloc_xrcd_mbox_in {
513 struct mlx5_inbox_hdr hdr;
518 struct mlx5_dealloc_xrcd_mbox_out {
519 struct mlx5_outbox_hdr hdr;
523 static inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn)
525 return radix_tree_lookup(&dev->priv.qp_table.tree, qpn);
528 static inline struct mlx5_core_mr *__mlx5_mr_lookup(struct mlx5_core_dev *dev, u32 key)
530 return radix_tree_lookup(&dev->priv.mr_table.tree, key);
533 int mlx5_core_create_qp(struct mlx5_core_dev *dev,
534 struct mlx5_core_qp *qp,
535 struct mlx5_create_qp_mbox_in *in,
537 int mlx5_core_qp_modify(struct mlx5_core_dev *dev, enum mlx5_qp_state cur_state,
538 enum mlx5_qp_state new_state,
539 struct mlx5_modify_qp_mbox_in *in, int sqd_event,
540 struct mlx5_core_qp *qp);
541 int mlx5_core_destroy_qp(struct mlx5_core_dev *dev,
542 struct mlx5_core_qp *qp);
543 int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp,
544 struct mlx5_query_qp_mbox_out *out, int outlen);
546 int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn);
547 int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn);
548 void mlx5_init_qp_table(struct mlx5_core_dev *dev);
549 void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev);
550 int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
551 void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
553 static inline const char *mlx5_qp_type_str(int type)
556 case MLX5_QP_ST_RC: return "RC";
557 case MLX5_QP_ST_UC: return "C";
558 case MLX5_QP_ST_UD: return "UD";
559 case MLX5_QP_ST_XRC: return "XRC";
560 case MLX5_QP_ST_MLX: return "MLX";
561 case MLX5_QP_ST_QP0: return "QP0";
562 case MLX5_QP_ST_QP1: return "QP1";
563 case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE";
564 case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6";
565 case MLX5_QP_ST_SNIFFER: return "SNIFFER";
566 case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR";
567 case MLX5_QP_ST_PTP_1588: return "PTP_1588";
568 case MLX5_QP_ST_REG_UMR: return "REG_UMR";
569 default: return "Invalid transport type";
573 static inline const char *mlx5_qp_state_str(int state)
576 case MLX5_QP_STATE_RST:
578 case MLX5_QP_STATE_INIT:
580 case MLX5_QP_STATE_RTR:
582 case MLX5_QP_STATE_RTS:
584 case MLX5_QP_STATE_SQER:
586 case MLX5_QP_STATE_SQD:
588 case MLX5_QP_STATE_ERR:
590 case MLX5_QP_STATE_SQ_DRAINING:
591 return "SQ_DRAINING";
592 case MLX5_QP_STATE_SUSPENDED:
594 default: return "Invalid QP state";
598 #endif /* MLX5_QP_H */