2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/mlx5/device.h>
37 #include <linux/mlx5/driver.h>
39 #define MLX5_INVALID_LKEY 0x100
40 #define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 5)
41 #define MLX5_DIF_SIZE 8
42 #define MLX5_STRIDE_BLOCK_OP 0x400
43 #define MLX5_CPY_GRD_MASK 0xc0
44 #define MLX5_CPY_APP_MASK 0x30
45 #define MLX5_CPY_REF_MASK 0x0f
46 #define MLX5_BSF_INC_REFTAG (1 << 6)
47 #define MLX5_BSF_INL_VALID (1 << 15)
48 #define MLX5_BSF_REFRESH_DIF (1 << 14)
49 #define MLX5_BSF_REPEAT_BLOCK (1 << 7)
50 #define MLX5_BSF_APPTAG_ESCAPE 0x1
51 #define MLX5_BSF_APPREF_ESCAPE 0x2
53 #define MLX5_QPN_BITS 24
54 #define MLX5_QPN_MASK ((1 << MLX5_QPN_BITS) - 1)
57 MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
58 MLX5_QP_OPTPAR_RRE = 1 << 1,
59 MLX5_QP_OPTPAR_RAE = 1 << 2,
60 MLX5_QP_OPTPAR_RWE = 1 << 3,
61 MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4,
62 MLX5_QP_OPTPAR_Q_KEY = 1 << 5,
63 MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
64 MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
65 MLX5_QP_OPTPAR_SRA_MAX = 1 << 8,
66 MLX5_QP_OPTPAR_RRA_MAX = 1 << 9,
67 MLX5_QP_OPTPAR_PM_STATE = 1 << 10,
68 MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12,
69 MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13,
70 MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
71 MLX5_QP_OPTPAR_PRI_PORT = 1 << 16,
72 MLX5_QP_OPTPAR_SRQN = 1 << 18,
73 MLX5_QP_OPTPAR_CQN_RCV = 1 << 19,
74 MLX5_QP_OPTPAR_DC_HS = 1 << 20,
75 MLX5_QP_OPTPAR_DC_KEY = 1 << 21,
79 MLX5_QP_STATE_RST = 0,
80 MLX5_QP_STATE_INIT = 1,
81 MLX5_QP_STATE_RTR = 2,
82 MLX5_QP_STATE_RTS = 3,
83 MLX5_QP_STATE_SQER = 4,
84 MLX5_QP_STATE_SQD = 5,
85 MLX5_QP_STATE_ERR = 6,
86 MLX5_QP_STATE_SQ_DRAINING = 7,
87 MLX5_QP_STATE_SUSPENDED = 9,
100 MLX5_QP_ST_QP1 = 0x8,
101 MLX5_QP_ST_RAW_ETHERTYPE = 0x9,
102 MLX5_QP_ST_RAW_IPV6 = 0xa,
103 MLX5_QP_ST_SNIFFER = 0xb,
104 MLX5_QP_ST_SYNC_UMR = 0xe,
105 MLX5_QP_ST_PTP_1588 = 0xd,
106 MLX5_QP_ST_REG_UMR = 0xc,
111 MLX5_QP_PM_MIGRATED = 0x3,
112 MLX5_QP_PM_ARMED = 0x0,
113 MLX5_QP_PM_REARM = 0x1
117 MLX5_NON_ZERO_RQ = 0 << 24,
118 MLX5_SRQ_RQ = 1 << 24,
119 MLX5_CRQ_RQ = 2 << 24,
120 MLX5_ZERO_LEN_RQ = 3 << 24
125 MLX5_QP_BIT_SRE = 1 << 15,
126 MLX5_QP_BIT_SWE = 1 << 14,
127 MLX5_QP_BIT_SAE = 1 << 13,
129 MLX5_QP_BIT_RRE = 1 << 15,
130 MLX5_QP_BIT_RWE = 1 << 14,
131 MLX5_QP_BIT_RAE = 1 << 13,
132 MLX5_QP_BIT_RIC = 1 << 4,
136 MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2,
137 MLX5_WQE_CTRL_SOLICITED = 1 << 1,
141 MLX5_SEND_WQE_BB = 64,
145 MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27,
146 MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28,
147 MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29,
148 MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30,
149 MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31
153 MLX5_FENCE_MODE_NONE = 0 << 5,
154 MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5,
155 MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5,
156 MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5,
160 MLX5_QP_LAT_SENSITIVE = 1 << 28,
161 MLX5_QP_BLOCK_MCAST = 1 << 30,
162 MLX5_QP_ENABLE_SIG = 1 << 31,
171 MLX5_FLAGS_INLINE = 1<<7,
172 MLX5_FLAGS_CHECK_FREE = 1<<5,
175 struct mlx5_wqe_fmr_seg {
186 struct mlx5_wqe_ctrl_seg {
187 __be32 opmod_idx_opcode;
195 #define MLX5_WQE_CTRL_DS_MASK 0x3f
196 #define MLX5_WQE_CTRL_QPN_MASK 0xffffff00
197 #define MLX5_WQE_CTRL_QPN_SHIFT 8
198 #define MLX5_WQE_DS_UNITS 16
199 #define MLX5_WQE_CTRL_OPCODE_MASK 0xff
200 #define MLX5_WQE_CTRL_WQE_INDEX_MASK 0x00ffff00
201 #define MLX5_WQE_CTRL_WQE_INDEX_SHIFT 8
203 struct mlx5_wqe_xrc_seg {
208 struct mlx5_wqe_masked_atomic_seg {
211 __be64 swap_add_mask;
234 struct mlx5_wqe_datagram_seg {
238 struct mlx5_wqe_raddr_seg {
244 struct mlx5_wqe_atomic_seg {
249 struct mlx5_wqe_data_seg {
255 struct mlx5_wqe_umr_ctrl_seg {
258 __be16 klm_octowords;
259 __be16 bsf_octowords;
264 struct mlx5_seg_set_psv {
268 __be32 transient_sig;
272 struct mlx5_seg_get_psv {
280 struct mlx5_seg_check_psv {
282 __be16 err_coalescing_op;
286 __be16 xport_err_mask;
294 struct mlx5_rwqe_sig {
300 struct mlx5_wqe_signature_seg {
306 #define MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK 0x3ff
308 struct mlx5_wqe_inline_seg {
317 struct mlx5_bsf_inl {
324 u8 dif_inc_ref_guard_check;
325 __be16 dif_app_bitmask_check;
329 struct mlx5_bsf_basic {
341 __be32 raw_data_size;
345 struct mlx5_bsf_ext {
346 __be32 t_init_gen_pro_size;
347 __be32 rsvd_epi_size;
351 struct mlx5_bsf_inl w_inl;
352 struct mlx5_bsf_inl m_inl;
361 struct mlx5_stride_block_entry {
368 struct mlx5_stride_block_ctrl_seg {
369 __be32 bcount_per_cycle;
376 enum mlx5_pagefault_flags {
377 MLX5_PFAULT_REQUESTOR = 1 << 0,
378 MLX5_PFAULT_WRITE = 1 << 1,
379 MLX5_PFAULT_RDMA = 1 << 2,
382 /* Contains the details of a pagefault. */
383 struct mlx5_pagefault {
386 enum mlx5_pagefault_flags flags;
388 /* Initiator or send message responder pagefault details. */
390 /* Received packet size, only valid for responders. */
393 * WQE index. Refers to either the send queue or
394 * receive queue, according to event_subtype.
398 /* RDMA responder pagefault details */
402 * Received packet size, minimal size page fault
403 * resolution required for forward progress.
412 struct mlx5_core_qp {
413 struct mlx5_core_rsc_common common; /* must be first */
414 void (*event) (struct mlx5_core_qp *, int);
415 void (*pfault_handler)(struct mlx5_core_qp *, struct mlx5_pagefault *);
417 struct mlx5_rsc_debug *dbg;
421 struct mlx5_qp_path {
433 __be32 tclass_flowlabel;
441 struct mlx5_qp_context {
447 __be32 qp_counter_set_usr_page;
449 __be32 log_pg_sz_remote_qpn;
450 struct mlx5_qp_path pri_path;
451 struct mlx5_qp_path alt_path;
454 __be32 next_send_psn;
457 __be32 last_acked_psn;
460 __be32 rnr_nextrecvpsn;
467 __be16 hw_sq_wqe_counter;
468 __be16 sw_sq_wqe_counter;
469 __be16 hw_rcyclic_byte_counter;
470 __be16 hw_rq_counter;
471 __be16 sw_rcyclic_byte_counter;
472 __be16 sw_rq_counter;
477 __be64 dc_access_key;
481 struct mlx5_create_qp_mbox_in {
482 struct mlx5_inbox_hdr hdr;
485 __be32 opt_param_mask;
487 struct mlx5_qp_context ctx;
492 struct mlx5_create_qp_mbox_out {
493 struct mlx5_outbox_hdr hdr;
498 struct mlx5_destroy_qp_mbox_in {
499 struct mlx5_inbox_hdr hdr;
504 struct mlx5_destroy_qp_mbox_out {
505 struct mlx5_outbox_hdr hdr;
509 struct mlx5_modify_qp_mbox_in {
510 struct mlx5_inbox_hdr hdr;
515 struct mlx5_qp_context ctx;
518 struct mlx5_modify_qp_mbox_out {
519 struct mlx5_outbox_hdr hdr;
523 struct mlx5_query_qp_mbox_in {
524 struct mlx5_inbox_hdr hdr;
529 struct mlx5_query_qp_mbox_out {
530 struct mlx5_outbox_hdr hdr;
534 struct mlx5_qp_context ctx;
539 struct mlx5_conf_sqp_mbox_in {
540 struct mlx5_inbox_hdr hdr;
546 struct mlx5_conf_sqp_mbox_out {
547 struct mlx5_outbox_hdr hdr;
551 struct mlx5_alloc_xrcd_mbox_in {
552 struct mlx5_inbox_hdr hdr;
556 struct mlx5_alloc_xrcd_mbox_out {
557 struct mlx5_outbox_hdr hdr;
562 struct mlx5_dealloc_xrcd_mbox_in {
563 struct mlx5_inbox_hdr hdr;
568 struct mlx5_dealloc_xrcd_mbox_out {
569 struct mlx5_outbox_hdr hdr;
573 static inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn)
575 return radix_tree_lookup(&dev->priv.qp_table.tree, qpn);
578 static inline struct mlx5_core_mr *__mlx5_mr_lookup(struct mlx5_core_dev *dev, u32 key)
580 return radix_tree_lookup(&dev->priv.mr_table.tree, key);
583 struct mlx5_page_fault_resume_mbox_in {
584 struct mlx5_inbox_hdr hdr;
589 struct mlx5_page_fault_resume_mbox_out {
590 struct mlx5_outbox_hdr hdr;
594 int mlx5_core_create_qp(struct mlx5_core_dev *dev,
595 struct mlx5_core_qp *qp,
596 struct mlx5_create_qp_mbox_in *in,
598 int mlx5_core_qp_modify(struct mlx5_core_dev *dev, enum mlx5_qp_state cur_state,
599 enum mlx5_qp_state new_state,
600 struct mlx5_modify_qp_mbox_in *in, int sqd_event,
601 struct mlx5_core_qp *qp);
602 int mlx5_core_destroy_qp(struct mlx5_core_dev *dev,
603 struct mlx5_core_qp *qp);
604 int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp,
605 struct mlx5_query_qp_mbox_out *out, int outlen);
607 int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn);
608 int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn);
609 void mlx5_init_qp_table(struct mlx5_core_dev *dev);
610 void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev);
611 int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
612 void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
613 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
614 int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 qpn,
615 u8 context, int error);
618 static inline const char *mlx5_qp_type_str(int type)
621 case MLX5_QP_ST_RC: return "RC";
622 case MLX5_QP_ST_UC: return "C";
623 case MLX5_QP_ST_UD: return "UD";
624 case MLX5_QP_ST_XRC: return "XRC";
625 case MLX5_QP_ST_MLX: return "MLX";
626 case MLX5_QP_ST_QP0: return "QP0";
627 case MLX5_QP_ST_QP1: return "QP1";
628 case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE";
629 case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6";
630 case MLX5_QP_ST_SNIFFER: return "SNIFFER";
631 case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR";
632 case MLX5_QP_ST_PTP_1588: return "PTP_1588";
633 case MLX5_QP_ST_REG_UMR: return "REG_UMR";
634 default: return "Invalid transport type";
638 static inline const char *mlx5_qp_state_str(int state)
641 case MLX5_QP_STATE_RST:
643 case MLX5_QP_STATE_INIT:
645 case MLX5_QP_STATE_RTR:
647 case MLX5_QP_STATE_RTS:
649 case MLX5_QP_STATE_SQER:
651 case MLX5_QP_STATE_SQD:
653 case MLX5_QP_STATE_ERR:
655 case MLX5_QP_STATE_SQ_DRAINING:
656 return "SQ_DRAINING";
657 case MLX5_QP_STATE_SUSPENDED:
659 default: return "Invalid QP state";
663 #endif /* MLX5_QP_H */