2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/mlx5/device.h>
37 #include <linux/mlx5/driver.h>
39 #define MLX5_INVALID_LKEY 0x100
42 MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
43 MLX5_QP_OPTPAR_RRE = 1 << 1,
44 MLX5_QP_OPTPAR_RAE = 1 << 2,
45 MLX5_QP_OPTPAR_RWE = 1 << 3,
46 MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4,
47 MLX5_QP_OPTPAR_Q_KEY = 1 << 5,
48 MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
49 MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
50 MLX5_QP_OPTPAR_SRA_MAX = 1 << 8,
51 MLX5_QP_OPTPAR_RRA_MAX = 1 << 9,
52 MLX5_QP_OPTPAR_PM_STATE = 1 << 10,
53 MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12,
54 MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13,
55 MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
56 MLX5_QP_OPTPAR_PRI_PORT = 1 << 16,
57 MLX5_QP_OPTPAR_SRQN = 1 << 18,
58 MLX5_QP_OPTPAR_CQN_RCV = 1 << 19,
59 MLX5_QP_OPTPAR_DC_HS = 1 << 20,
60 MLX5_QP_OPTPAR_DC_KEY = 1 << 21,
64 MLX5_QP_STATE_RST = 0,
65 MLX5_QP_STATE_INIT = 1,
66 MLX5_QP_STATE_RTR = 2,
67 MLX5_QP_STATE_RTS = 3,
68 MLX5_QP_STATE_SQER = 4,
69 MLX5_QP_STATE_SQD = 5,
70 MLX5_QP_STATE_ERR = 6,
71 MLX5_QP_STATE_SQ_DRAINING = 7,
72 MLX5_QP_STATE_SUSPENDED = 9,
86 MLX5_QP_ST_RAW_ETHERTYPE = 0x9,
87 MLX5_QP_ST_RAW_IPV6 = 0xa,
88 MLX5_QP_ST_SNIFFER = 0xb,
89 MLX5_QP_ST_SYNC_UMR = 0xe,
90 MLX5_QP_ST_PTP_1588 = 0xd,
91 MLX5_QP_ST_REG_UMR = 0xc,
96 MLX5_QP_PM_MIGRATED = 0x3,
97 MLX5_QP_PM_ARMED = 0x0,
98 MLX5_QP_PM_REARM = 0x1
102 MLX5_NON_ZERO_RQ = 0 << 24,
103 MLX5_SRQ_RQ = 1 << 24,
104 MLX5_CRQ_RQ = 2 << 24,
105 MLX5_ZERO_LEN_RQ = 3 << 24
110 MLX5_QP_BIT_SRE = 1 << 15,
111 MLX5_QP_BIT_SWE = 1 << 14,
112 MLX5_QP_BIT_SAE = 1 << 13,
114 MLX5_QP_BIT_RRE = 1 << 15,
115 MLX5_QP_BIT_RWE = 1 << 14,
116 MLX5_QP_BIT_RAE = 1 << 13,
117 MLX5_QP_BIT_RIC = 1 << 4,
121 MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2,
122 MLX5_WQE_CTRL_SOLICITED = 1 << 1,
126 MLX5_SEND_WQE_BB = 64,
130 MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27,
131 MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28,
132 MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29,
133 MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30,
134 MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31
138 MLX5_FENCE_MODE_NONE = 0 << 5,
139 MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5,
140 MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5,
141 MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5,
145 MLX5_QP_LAT_SENSITIVE = 1 << 28,
146 MLX5_QP_ENABLE_SIG = 1 << 31,
154 struct mlx5_wqe_fmr_seg {
165 struct mlx5_wqe_ctrl_seg {
166 __be32 opmod_idx_opcode;
174 struct mlx5_wqe_xrc_seg {
179 struct mlx5_wqe_masked_atomic_seg {
182 __be64 swap_add_mask;
205 struct mlx5_wqe_datagram_seg {
209 struct mlx5_wqe_raddr_seg {
215 struct mlx5_wqe_atomic_seg {
220 struct mlx5_wqe_data_seg {
226 struct mlx5_wqe_umr_ctrl_seg {
229 __be16 klm_octowords;
230 __be16 bsf_octowords;
235 struct mlx5_seg_set_psv {
239 __be32 transient_sig;
243 struct mlx5_seg_get_psv {
251 struct mlx5_seg_check_psv {
253 __be16 err_coalescing_op;
257 __be16 xport_err_mask;
265 struct mlx5_rwqe_sig {
271 struct mlx5_wqe_signature_seg {
277 struct mlx5_wqe_inline_seg {
281 struct mlx5_core_qp {
282 void (*event) (struct mlx5_core_qp *, int);
285 struct completion free;
286 struct mlx5_rsc_debug *dbg;
290 struct mlx5_qp_path {
302 __be32 tclass_flowlabel;
310 struct mlx5_qp_context {
316 __be32 qp_counter_set_usr_page;
318 __be32 log_pg_sz_remote_qpn;
319 struct mlx5_qp_path pri_path;
320 struct mlx5_qp_path alt_path;
323 __be32 next_send_psn;
326 __be32 last_acked_psn;
329 __be32 rnr_nextrecvpsn;
336 __be16 hw_sq_wqe_counter;
337 __be16 sw_sq_wqe_counter;
338 __be16 hw_rcyclic_byte_counter;
339 __be16 hw_rq_counter;
340 __be16 sw_rcyclic_byte_counter;
341 __be16 sw_rq_counter;
346 __be64 dc_access_key;
350 struct mlx5_create_qp_mbox_in {
351 struct mlx5_inbox_hdr hdr;
354 __be32 opt_param_mask;
356 struct mlx5_qp_context ctx;
361 struct mlx5_create_qp_mbox_out {
362 struct mlx5_outbox_hdr hdr;
367 struct mlx5_destroy_qp_mbox_in {
368 struct mlx5_inbox_hdr hdr;
373 struct mlx5_destroy_qp_mbox_out {
374 struct mlx5_outbox_hdr hdr;
378 struct mlx5_modify_qp_mbox_in {
379 struct mlx5_inbox_hdr hdr;
384 struct mlx5_qp_context ctx;
387 struct mlx5_modify_qp_mbox_out {
388 struct mlx5_outbox_hdr hdr;
392 struct mlx5_query_qp_mbox_in {
393 struct mlx5_inbox_hdr hdr;
398 struct mlx5_query_qp_mbox_out {
399 struct mlx5_outbox_hdr hdr;
403 struct mlx5_qp_context ctx;
408 struct mlx5_conf_sqp_mbox_in {
409 struct mlx5_inbox_hdr hdr;
415 struct mlx5_conf_sqp_mbox_out {
416 struct mlx5_outbox_hdr hdr;
420 struct mlx5_alloc_xrcd_mbox_in {
421 struct mlx5_inbox_hdr hdr;
425 struct mlx5_alloc_xrcd_mbox_out {
426 struct mlx5_outbox_hdr hdr;
431 struct mlx5_dealloc_xrcd_mbox_in {
432 struct mlx5_inbox_hdr hdr;
437 struct mlx5_dealloc_xrcd_mbox_out {
438 struct mlx5_outbox_hdr hdr;
442 static inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn)
444 return radix_tree_lookup(&dev->priv.qp_table.tree, qpn);
447 int mlx5_core_create_qp(struct mlx5_core_dev *dev,
448 struct mlx5_core_qp *qp,
449 struct mlx5_create_qp_mbox_in *in,
451 int mlx5_core_qp_modify(struct mlx5_core_dev *dev, enum mlx5_qp_state cur_state,
452 enum mlx5_qp_state new_state,
453 struct mlx5_modify_qp_mbox_in *in, int sqd_event,
454 struct mlx5_core_qp *qp);
455 int mlx5_core_destroy_qp(struct mlx5_core_dev *dev,
456 struct mlx5_core_qp *qp);
457 int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp,
458 struct mlx5_query_qp_mbox_out *out, int outlen);
460 int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn);
461 int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn);
462 void mlx5_init_qp_table(struct mlx5_core_dev *dev);
463 void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev);
464 int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
465 void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
467 #endif /* MLX5_QP_H */