2 * linux/include/linux/mmc/sdhci.h - Secure Digital Host Controller Interface
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
11 #ifndef LINUX_MMC_SDHCI_H
12 #define LINUX_MMC_SDHCI_H
14 #include <linux/scatterlist.h>
15 #include <linux/compiler.h>
16 #include <linux/types.h>
18 #include <linux/mmc/host.h>
20 struct sdhci_host_next {
21 unsigned int sg_count;
26 /* Data set by hardware interface driver */
27 const char *hw_name; /* Hardware bus name */
29 unsigned int quirks; /* Deviations from spec. */
31 /* Controller doesn't honor resets unless we touch the clock register */
32 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
33 /* Controller has bad caps bits, but really supports DMA */
34 #define SDHCI_QUIRK_FORCE_DMA (1<<1)
35 /* Controller doesn't like to be reset when there is no card inserted. */
36 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
37 /* Controller doesn't like clearing the power reg before a change */
38 #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
39 /* Controller has flaky internal state so reset it on each ios change */
40 #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
41 /* Controller has an unusable DMA engine */
42 #define SDHCI_QUIRK_BROKEN_DMA (1<<5)
43 /* Controller has an unusable ADMA engine */
44 #define SDHCI_QUIRK_BROKEN_ADMA (1<<6)
45 /* Controller can only DMA from 32-bit aligned addresses */
46 #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7)
47 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */
48 #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8)
49 /* Controller can only ADMA chunks that are a multiple of 32 bits */
50 #define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9)
51 /* Controller needs to be reset after each request to stay stable */
52 #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10)
53 /* Controller needs voltage and power writes to happen separately */
54 #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11)
55 /* Controller provides an incorrect timeout value for transfers */
56 #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12)
57 /* Controller has an issue with buffer bits for small transfers */
58 #define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13)
59 /* Controller does not provide transfer-complete interrupt when not busy */
60 #define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14)
61 /* Controller has unreliable card detection */
62 #define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15)
63 /* Controller reports inverted write-protect state */
64 #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16)
65 /* Controller does not like fast PIO transfers */
66 #define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18)
67 /* Controller has to be forced to use block size of 2048 bytes */
68 #define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20)
69 /* Controller cannot do multi-block transfers */
70 #define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21)
71 /* Controller can only handle 1-bit data transfers */
72 #define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22)
73 /* Controller needs 10ms delay between applying power and clock */
74 #define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23)
75 /* Controller uses SDCLK instead of TMCLK for data timeouts */
76 #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24)
77 /* Controller reports wrong base clock capability */
78 #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25)
79 /* Controller cannot support End Attribute in NOP ADMA descriptor */
80 #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26)
81 /* Controller is missing device caps. Use caps provided by host */
82 #define SDHCI_QUIRK_MISSING_CAPS (1<<27)
83 /* Controller uses Auto CMD12 command to stop the transfer */
84 #define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28)
85 /* Controller doesn't have HISPD bit field in HI-SPEED SD card */
86 #define SDHCI_QUIRK_NO_HISPD_BIT (1<<29)
87 /* Controller treats ADMA descriptors with length 0000h incorrectly */
88 #define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30)
89 /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */
90 #define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31)
92 unsigned int quirks2; /* More deviations from spec. */
94 #define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0)
95 #define SDHCI_QUIRK2_HOST_NO_CMD23 (1<<1)
96 /* The system physically doesn't support 1.8v, even if the host does */
97 #define SDHCI_QUIRK2_NO_1_8_V (1<<2)
98 #define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3)
99 #define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4)
100 /* Controller has a non-standard host control register */
101 #define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5)
102 /* Controller does not support HS200 */
103 #define SDHCI_QUIRK2_BROKEN_HS200 (1<<6)
104 /* Controller does not support DDR50 */
105 #define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7)
106 /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */
107 #define SDHCI_QUIRK2_STOP_WITH_TC (1<<8)
108 /* Controller does not support 64-bit DMA */
109 #define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9)
110 /* need clear transfer mode register before send cmd */
111 #define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10)
112 /* Capability register bit-63 indicates HS400 support */
113 #define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1<<11)
114 /* forced tuned clock */
115 #define SDHCI_QUIRK2_TUNING_WORK_AROUND (1<<12)
116 /* disable the block count for single block transactions */
117 #define SDHCI_QUIRK2_SUPPORT_SINGLE (1<<13)
119 int irq; /* Device IRQ */
120 void __iomem *ioaddr; /* Mapped address */
122 const struct sdhci_ops *ops; /* Low level hw interface */
125 struct mmc_host *mmc; /* MMC structure */
126 u64 dma_mask; /* custom DMA mask */
128 #if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE)
129 struct led_classdev led; /* LED control */
133 spinlock_t lock; /* Mutex */
135 int flags; /* Host attributes */
136 #define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */
137 #define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */
138 #define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */
139 #define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */
140 #define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */
141 #define SDHCI_NEEDS_RETUNING (1<<5) /* Host needs retuning */
142 #define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */
143 #define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */
144 #define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */
145 #define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */
146 #define SDHCI_SDR104_NEEDS_TUNING (1<<10) /* SDR104/HS200 needs tuning */
147 #define SDHCI_USING_RETUNING_TIMER (1<<11) /* Host is using a retuning timer for the card */
148 #define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */
149 #define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */
151 unsigned int version; /* SDHCI spec. version */
153 unsigned int max_clk; /* Max possible freq (MHz) */
154 unsigned int timeout_clk; /* Timeout freq (KHz) */
155 unsigned int clk_mul; /* Clock Muliplier value */
157 unsigned int clock; /* Current clock (MHz) */
158 u8 pwr; /* Current voltage */
160 bool runtime_suspended; /* Host is runtime suspended */
161 bool bus_on; /* Bus power prevents runtime suspend */
162 bool preset_enabled; /* Preset is enabled */
164 struct mmc_request *mrq; /* Current request */
165 struct mmc_command *cmd; /* Current command */
166 struct mmc_data *data; /* Current data request */
167 unsigned int data_early:1; /* Data finished before cmd */
168 unsigned int busy_handle:1; /* Handling the order of Busy-end */
170 struct sg_mapping_iter sg_miter; /* SG state for PIO */
171 unsigned int blocks; /* remaining PIO blocks */
173 int sg_count; /* Mapped sg entries */
175 void *adma_table; /* ADMA descriptor table */
176 void *align_buffer; /* Bounce buffer */
178 size_t adma_table_sz; /* ADMA descriptor table size */
179 size_t align_buffer_sz; /* Bounce buffer size */
181 dma_addr_t adma_addr; /* Mapped ADMA descr. table */
182 dma_addr_t align_addr; /* Mapped bounce buffer */
184 unsigned int desc_sz; /* ADMA descriptor size */
185 unsigned int align_sz; /* ADMA alignment */
186 unsigned int align_mask; /* ADMA alignment mask */
188 struct tasklet_struct finish_tasklet; /* Tasklet structures */
190 struct timer_list timer; /* Timer for timeouts */
192 u32 caps; /* Alternative CAPABILITY_0 */
193 u32 caps1; /* Alternative CAPABILITY_1 */
195 unsigned int ocr_avail_sdio; /* OCR bit masks */
196 unsigned int ocr_avail_sd;
197 unsigned int ocr_avail_mmc;
198 u32 ocr_mask; /* available voltages */
200 unsigned timing; /* Current timing */
204 /* cached registers */
207 wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */
208 unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */
210 unsigned int tuning_count; /* Timer count for re-tuning */
211 unsigned int tuning_mode; /* Re-tuning mode supported by host */
212 #define SDHCI_TUNING_MODE_1 0
213 struct timer_list tuning_timer; /* Timer for tuning */
215 struct sdhci_host_next next_data;
216 unsigned long private[0] ____cacheline_aligned;
218 #endif /* LINUX_MMC_SDHCI_H */