3 Copyright (C) 2010 InvenSense Corporation, All Rights Reserved.
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program. If not, see <http://www.gnu.org/licenses/>.
24 #include <linux/types.h>
28 #error MPU6000 build including MPU3050 header
31 #define MPU_NAME "mpu3050"
32 #define DEFAULT_MPU_SLAVEADDR 0x68
34 /*==== MPU REGISTER SET ====*/
36 MPUREG_WHO_AM_I = 0, /* 00 0x00 */
37 MPUREG_PRODUCT_ID, /* 01 0x01 */
38 MPUREG_02_RSVD, /* 02 0x02 */
39 MPUREG_03_RSVD, /* 03 0x03 */
40 MPUREG_04_RSVD, /* 04 0x04 */
41 MPUREG_XG_OFFS_TC, /* 05 0x05 */
42 MPUREG_06_RSVD, /* 06 0x06 */
43 MPUREG_07_RSVD, /* 07 0x07 */
44 MPUREG_YG_OFFS_TC, /* 08 0x08 */
45 MPUREG_09_RSVD, /* 09 0x09 */
46 MPUREG_0A_RSVD, /* 10 0x0a */
47 MPUREG_ZG_OFFS_TC, /* 11 0x0b */
48 MPUREG_X_OFFS_USRH, /* 12 0x0c */
49 MPUREG_X_OFFS_USRL, /* 13 0x0d */
50 MPUREG_Y_OFFS_USRH, /* 14 0x0e */
51 MPUREG_Y_OFFS_USRL, /* 15 0x0f */
52 MPUREG_Z_OFFS_USRH, /* 16 0x10 */
53 MPUREG_Z_OFFS_USRL, /* 17 0x11 */
54 MPUREG_FIFO_EN1, /* 18 0x12 */
55 MPUREG_FIFO_EN2, /* 19 0x13 */
56 MPUREG_AUX_SLV_ADDR, /* 20 0x14 */
57 MPUREG_SMPLRT_DIV, /* 21 0x15 */
58 MPUREG_DLPF_FS_SYNC, /* 22 0x16 */
59 MPUREG_INT_CFG, /* 23 0x17 */
60 MPUREG_ACCEL_BURST_ADDR,/* 24 0x18 */
61 MPUREG_19_RSVD, /* 25 0x19 */
62 MPUREG_INT_STATUS, /* 26 0x1a */
63 MPUREG_TEMP_OUT_H, /* 27 0x1b */
64 MPUREG_TEMP_OUT_L, /* 28 0x1c */
65 MPUREG_GYRO_XOUT_H, /* 29 0x1d */
66 MPUREG_GYRO_XOUT_L, /* 30 0x1e */
67 MPUREG_GYRO_YOUT_H, /* 31 0x1f */
68 MPUREG_GYRO_YOUT_L, /* 32 0x20 */
69 MPUREG_GYRO_ZOUT_H, /* 33 0x21 */
70 MPUREG_GYRO_ZOUT_L, /* 34 0x22 */
71 MPUREG_23_RSVD, /* 35 0x23 */
72 MPUREG_24_RSVD, /* 36 0x24 */
73 MPUREG_25_RSVD, /* 37 0x25 */
74 MPUREG_26_RSVD, /* 38 0x26 */
75 MPUREG_27_RSVD, /* 39 0x27 */
76 MPUREG_28_RSVD, /* 40 0x28 */
77 MPUREG_29_RSVD, /* 41 0x29 */
78 MPUREG_2A_RSVD, /* 42 0x2a */
79 MPUREG_2B_RSVD, /* 43 0x2b */
80 MPUREG_2C_RSVD, /* 44 0x2c */
81 MPUREG_2D_RSVD, /* 45 0x2d */
82 MPUREG_2E_RSVD, /* 46 0x2e */
83 MPUREG_2F_RSVD, /* 47 0x2f */
84 MPUREG_30_RSVD, /* 48 0x30 */
85 MPUREG_31_RSVD, /* 49 0x31 */
86 MPUREG_32_RSVD, /* 50 0x32 */
87 MPUREG_33_RSVD, /* 51 0x33 */
88 MPUREG_34_RSVD, /* 52 0x34 */
89 MPUREG_DMP_CFG_1, /* 53 0x35 */
90 MPUREG_DMP_CFG_2, /* 54 0x36 */
91 MPUREG_BANK_SEL, /* 55 0x37 */
92 MPUREG_MEM_START_ADDR, /* 56 0x38 */
93 MPUREG_MEM_R_W, /* 57 0x39 */
94 MPUREG_FIFO_COUNTH, /* 58 0x3a */
95 MPUREG_FIFO_COUNTL, /* 59 0x3b */
96 MPUREG_FIFO_R_W, /* 60 0x3c */
97 MPUREG_USER_CTRL, /* 61 0x3d */
98 MPUREG_PWR_MGM, /* 62 0x3e */
99 MPUREG_3F_RSVD, /* 63 0x3f */
100 NUM_OF_MPU_REGISTERS /* 64 0x40 */
103 /*==== BITS FOR MPU ====*/
105 /*---- MPU 'FIFO_EN1' register (12) ----*/
106 #define BIT_TEMP_OUT 0x80
107 #define BIT_GYRO_XOUT 0x40
108 #define BIT_GYRO_YOUT 0x20
109 #define BIT_GYRO_ZOUT 0x10
110 #define BIT_ACCEL_XOUT 0x08
111 #define BIT_ACCEL_YOUT 0x04
112 #define BIT_ACCEL_ZOUT 0x02
113 #define BIT_AUX_1OUT 0x01
114 /*---- MPU 'FIFO_EN2' register (13) ----*/
115 #define BIT_AUX_2OUT 0x02
116 #define BIT_AUX_3OUT 0x01
117 /*---- MPU 'DLPF_FS_SYNC' register (16) ----*/
118 #define BITS_EXT_SYNC_NONE 0x00
119 #define BITS_EXT_SYNC_TEMP 0x20
120 #define BITS_EXT_SYNC_GYROX 0x40
121 #define BITS_EXT_SYNC_GYROY 0x60
122 #define BITS_EXT_SYNC_GYROZ 0x80
123 #define BITS_EXT_SYNC_ACCELX 0xA0
124 #define BITS_EXT_SYNC_ACCELY 0xC0
125 #define BITS_EXT_SYNC_ACCELZ 0xE0
126 #define BITS_EXT_SYNC_MASK 0xE0
127 #define BITS_FS_250DPS 0x00
128 #define BITS_FS_500DPS 0x08
129 #define BITS_FS_1000DPS 0x10
130 #define BITS_FS_2000DPS 0x18
131 #define BITS_FS_MASK 0x18
132 #define BITS_DLPF_CFG_256HZ_NOLPF2 0x00
133 #define BITS_DLPF_CFG_188HZ 0x01
134 #define BITS_DLPF_CFG_98HZ 0x02
135 #define BITS_DLPF_CFG_42HZ 0x03
136 #define BITS_DLPF_CFG_20HZ 0x04
137 #define BITS_DLPF_CFG_10HZ 0x05
138 #define BITS_DLPF_CFG_5HZ 0x06
139 #define BITS_DLPF_CFG_2100HZ_NOLPF 0x07
140 #define BITS_DLPF_CFG_MASK 0x07
141 /*---- MPU 'INT_CFG' register (17) ----*/
142 #define BIT_ACTL 0x80
143 #define BIT_ACTL_LOW 0x80
144 #define BIT_ACTL_HIGH 0x00
145 #define BIT_OPEN 0x40
146 #define BIT_OPEN_DRAIN 0x40
147 #define BIT_PUSH_PULL 0x00
148 #define BIT_LATCH_INT_EN 0x20
149 #define BIT_LATCH_INT_EN 0x20
150 #define BIT_INT_PULSE_WIDTH_50US 0x00
151 #define BIT_INT_ANYRD_2CLEAR 0x10
152 #define BIT_INT_STAT_READ_2CLEAR 0x00
153 #define BIT_MPU_RDY_EN 0x04
154 #define BIT_DMP_INT_EN 0x02
155 #define BIT_RAW_RDY_EN 0x01
156 /*---- MPU 'INT_STATUS' register (1A) ----*/
157 #define BIT_INT_STATUS_FIFO_OVERLOW 0x80
158 #define BIT_MPU_RDY 0x04
159 #define BIT_DMP_INT 0x02
160 #define BIT_RAW_RDY 0x01
161 /*---- MPU 'BANK_SEL' register (37) ----*/
162 #define BIT_PRFTCH_EN 0x20
163 #define BIT_CFG_USER_BANK 0x10
164 #define BITS_MEM_SEL 0x0f
165 /*---- MPU 'USER_CTRL' register (3D) ----*/
166 #define BIT_DMP_EN 0x80
167 #define BIT_FIFO_EN 0x40
168 #define BIT_AUX_IF_EN 0x20
169 #define BIT_AUX_RD_LENG 0x10
170 #define BIT_AUX_IF_RST 0x08
171 #define BIT_DMP_RST 0x04
172 #define BIT_FIFO_RST 0x02
173 #define BIT_GYRO_RST 0x01
174 /*---- MPU 'PWR_MGM' register (3E) ----*/
175 #define BIT_H_RESET 0x80
176 #define BIT_SLEEP 0x40
177 #define BIT_STBY_XG 0x20
178 #define BIT_STBY_YG 0x10
179 #define BIT_STBY_ZG 0x08
180 #define BITS_CLKSEL 0x07
182 /*---- MPU Silicon Revision ----*/
183 #define MPU_SILICON_REV_A4 1 /* MPU A4 Device */
184 #define MPU_SILICON_REV_B1 2 /* MPU B1 Device */
185 #define MPU_SILICON_REV_B4 3 /* MPU B4 Device */
186 #define MPU_SILICON_REV_B6 4 /* MPU B6 Device */
188 /*---- MPU Memory ----*/
189 #define MPU_MEM_BANK_SIZE (256)
190 #define FIFO_HW_SIZE (512)
192 enum MPU_MEMORY_BANKS {
193 MPU_MEM_RAM_BANK_0 = 0,
197 MPU_MEM_NUM_RAM_BANKS,
198 MPU_MEM_OTP_BANK_0 = MPU_MEM_NUM_RAM_BANKS,
199 /* This one is always last */
203 #define MPU_NUM_AXES (3)
205 /*---- structure containing control variables used by MLDL ----*/
206 /*---- MPU clock source settings ----*/
207 /*---- MPU filter selections ----*/
209 MPU_FILTER_256HZ_NOLPF2 = 0,
216 MPU_FILTER_2100HZ_NOLPF,
229 MPU_CLK_SEL_INTERNAL = 0,
230 MPU_CLK_SEL_PLLGYROX,
231 MPU_CLK_SEL_PLLGYROY,
232 MPU_CLK_SEL_PLLGYROZ,
233 MPU_CLK_SEL_PLLEXT32K,
234 MPU_CLK_SEL_PLLEXT19M,
235 MPU_CLK_SEL_RESERVED,
241 MPU_EXT_SYNC_NONE = 0,
252 #define DLPF_FS_SYNC_VALUE(ext_sync, full_scale, lpf) \
253 ((ext_sync << 5) | (full_scale << 3) | lpf)
255 #endif /* __MPU3050_H_ */