3 Copyright (C) 2010 InvenSense Corporation, All Rights Reserved.
11 #include <linux/types.h>
15 #error MPU6000 build including MPU3050 header
18 #define MPU_NAME "mpu3050"
19 #define DEFAULT_MPU_SLAVEADDR 0x68
21 /*==== MPU REGISTER SET ====*/
23 MPUREG_WHO_AM_I = 0, /* 00 0x00 */
24 MPUREG_PRODUCT_ID, /* 01 0x01 */
25 MPUREG_02_RSVD, /* 02 0x02 */
26 MPUREG_03_RSVD, /* 03 0x03 */
27 MPUREG_04_RSVD, /* 04 0x04 */
28 MPUREG_XG_OFFS_TC, /* 05 0x05 */
29 MPUREG_06_RSVD, /* 06 0x06 */
30 MPUREG_07_RSVD, /* 07 0x07 */
31 MPUREG_YG_OFFS_TC, /* 08 0x08 */
32 MPUREG_09_RSVD, /* 09 0x09 */
33 MPUREG_0A_RSVD, /* 10 0x0a */
34 MPUREG_ZG_OFFS_TC, /* 11 0x0b */
35 MPUREG_X_OFFS_USRH, /* 12 0x0c */
36 MPUREG_X_OFFS_USRL, /* 13 0x0d */
37 MPUREG_Y_OFFS_USRH, /* 14 0x0e */
38 MPUREG_Y_OFFS_USRL, /* 15 0x0f */
39 MPUREG_Z_OFFS_USRH, /* 16 0x10 */
40 MPUREG_Z_OFFS_USRL, /* 17 0x11 */
41 MPUREG_FIFO_EN1, /* 18 0x12 */
42 MPUREG_FIFO_EN2, /* 19 0x13 */
43 MPUREG_AUX_SLV_ADDR, /* 20 0x14 */
44 MPUREG_SMPLRT_DIV, /* 21 0x15 */
45 MPUREG_DLPF_FS_SYNC, /* 22 0x16 */
46 MPUREG_INT_CFG, /* 23 0x17 */
47 MPUREG_ACCEL_BURST_ADDR,/* 24 0x18 */
48 MPUREG_19_RSVD, /* 25 0x19 */
49 MPUREG_INT_STATUS, /* 26 0x1a */
50 MPUREG_TEMP_OUT_H, /* 27 0x1b */
51 MPUREG_TEMP_OUT_L, /* 28 0x1c */
52 MPUREG_GYRO_XOUT_H, /* 29 0x1d */
53 MPUREG_GYRO_XOUT_L, /* 30 0x1e */
54 MPUREG_GYRO_YOUT_H, /* 31 0x1f */
55 MPUREG_GYRO_YOUT_L, /* 32 0x20 */
56 MPUREG_GYRO_ZOUT_H, /* 33 0x21 */
57 MPUREG_GYRO_ZOUT_L, /* 34 0x22 */
58 MPUREG_23_RSVD, /* 35 0x23 */
59 MPUREG_24_RSVD, /* 36 0x24 */
60 MPUREG_25_RSVD, /* 37 0x25 */
61 MPUREG_26_RSVD, /* 38 0x26 */
62 MPUREG_27_RSVD, /* 39 0x27 */
63 MPUREG_28_RSVD, /* 40 0x28 */
64 MPUREG_29_RSVD, /* 41 0x29 */
65 MPUREG_2A_RSVD, /* 42 0x2a */
66 MPUREG_2B_RSVD, /* 43 0x2b */
67 MPUREG_2C_RSVD, /* 44 0x2c */
68 MPUREG_2D_RSVD, /* 45 0x2d */
69 MPUREG_2E_RSVD, /* 46 0x2e */
70 MPUREG_2F_RSVD, /* 47 0x2f */
71 MPUREG_30_RSVD, /* 48 0x30 */
72 MPUREG_31_RSVD, /* 49 0x31 */
73 MPUREG_32_RSVD, /* 50 0x32 */
74 MPUREG_33_RSVD, /* 51 0x33 */
75 MPUREG_34_RSVD, /* 52 0x34 */
76 MPUREG_DMP_CFG_1, /* 53 0x35 */
77 MPUREG_DMP_CFG_2, /* 54 0x36 */
78 MPUREG_BANK_SEL, /* 55 0x37 */
79 MPUREG_MEM_START_ADDR, /* 56 0x38 */
80 MPUREG_MEM_R_W, /* 57 0x39 */
81 MPUREG_FIFO_COUNTH, /* 58 0x3a */
82 MPUREG_FIFO_COUNTL, /* 59 0x3b */
83 MPUREG_FIFO_R_W, /* 60 0x3c */
84 MPUREG_USER_CTRL, /* 61 0x3d */
85 MPUREG_PWR_MGM, /* 62 0x3e */
86 MPUREG_3F_RSVD, /* 63 0x3f */
87 NUM_OF_MPU_REGISTERS /* 64 0x40 */
90 /*==== BITS FOR MPU ====*/
92 /*---- MPU 'FIFO_EN1' register (12) ----*/
93 #define BIT_TEMP_OUT 0x80
94 #define BIT_GYRO_XOUT 0x40
95 #define BIT_GYRO_YOUT 0x20
96 #define BIT_GYRO_ZOUT 0x10
97 #define BIT_ACCEL_XOUT 0x08
98 #define BIT_ACCEL_YOUT 0x04
99 #define BIT_ACCEL_ZOUT 0x02
100 #define BIT_AUX_1OUT 0x01
101 /*---- MPU 'FIFO_EN2' register (13) ----*/
102 #define BIT_AUX_2OUT 0x02
103 #define BIT_AUX_3OUT 0x01
104 /*---- MPU 'DLPF_FS_SYNC' register (16) ----*/
105 #define BITS_EXT_SYNC_NONE 0x00
106 #define BITS_EXT_SYNC_TEMP 0x20
107 #define BITS_EXT_SYNC_GYROX 0x40
108 #define BITS_EXT_SYNC_GYROY 0x60
109 #define BITS_EXT_SYNC_GYROZ 0x80
110 #define BITS_EXT_SYNC_ACCELX 0xA0
111 #define BITS_EXT_SYNC_ACCELY 0xC0
112 #define BITS_EXT_SYNC_ACCELZ 0xE0
113 #define BITS_EXT_SYNC_MASK 0xE0
114 #define BITS_FS_250DPS 0x00
115 #define BITS_FS_500DPS 0x08
116 #define BITS_FS_1000DPS 0x10
117 #define BITS_FS_2000DPS 0x18
118 #define BITS_FS_MASK 0x18
119 #define BITS_DLPF_CFG_256HZ_NOLPF2 0x00
120 #define BITS_DLPF_CFG_188HZ 0x01
121 #define BITS_DLPF_CFG_98HZ 0x02
122 #define BITS_DLPF_CFG_42HZ 0x03
123 #define BITS_DLPF_CFG_20HZ 0x04
124 #define BITS_DLPF_CFG_10HZ 0x05
125 #define BITS_DLPF_CFG_5HZ 0x06
126 #define BITS_DLPF_CFG_2100HZ_NOLPF 0x07
127 #define BITS_DLPF_CFG_MASK 0x07
128 /*---- MPU 'INT_CFG' register (17) ----*/
129 #define BIT_ACTL 0x80
130 #define BIT_ACTL_LOW 0x80
131 #define BIT_ACTL_HIGH 0x00
132 #define BIT_OPEN 0x40
133 #define BIT_OPEN_DRAIN 0x40
134 #define BIT_PUSH_PULL 0x00
135 #define BIT_LATCH_INT_EN 0x20
136 #define BIT_LATCH_INT_EN 0x20
137 #define BIT_INT_PULSE_WIDTH_50US 0x00
138 #define BIT_INT_ANYRD_2CLEAR 0x10
139 #define BIT_INT_STAT_READ_2CLEAR 0x00
140 #define BIT_MPU_RDY_EN 0x04
141 #define BIT_DMP_INT_EN 0x02
142 #define BIT_RAW_RDY_EN 0x01
143 /*---- MPU 'INT_STATUS' register (1A) ----*/
144 #define BIT_INT_STATUS_FIFO_OVERLOW 0x80
145 #define BIT_MPU_RDY 0x04
146 #define BIT_DMP_INT 0x02
147 #define BIT_RAW_RDY 0x01
148 /*---- MPU 'BANK_SEL' register (37) ----*/
149 #define BIT_PRFTCH_EN 0x20
150 #define BIT_CFG_USER_BANK 0x10
151 #define BITS_MEM_SEL 0x0f
152 /*---- MPU 'USER_CTRL' register (3D) ----*/
153 #define BIT_DMP_EN 0x80
154 #define BIT_FIFO_EN 0x40
155 #define BIT_AUX_IF_EN 0x20
156 #define BIT_AUX_RD_LENG 0x10
157 #define BIT_AUX_IF_RST 0x08
158 #define BIT_DMP_RST 0x04
159 #define BIT_FIFO_RST 0x02
160 #define BIT_GYRO_RST 0x01
161 /*---- MPU 'PWR_MGM' register (3E) ----*/
162 #define BIT_H_RESET 0x80
163 #define BIT_SLEEP 0x40
164 #define BIT_STBY_XG 0x20
165 #define BIT_STBY_YG 0x10
166 #define BIT_STBY_ZG 0x08
167 #define BITS_CLKSEL 0x07
169 /*---- MPU Silicon Revision ----*/
170 #define MPU_SILICON_REV_A4 1 /* MPU A4 Device */
171 #define MPU_SILICON_REV_B1 2 /* MPU B1 Device */
172 #define MPU_SILICON_REV_B4 3 /* MPU B4 Device */
173 #define MPU_SILICON_REV_B6 4 /* MPU B6 Device */
175 /*---- MPU Memory ----*/
176 #define MPU_MEM_BANK_SIZE (256)
177 #define FIFO_HW_SIZE (512)
179 enum MPU_MEMORY_BANKS {
180 MPU_MEM_RAM_BANK_0 = 0,
184 MPU_MEM_NUM_RAM_BANKS,
185 MPU_MEM_OTP_BANK_0 = MPU_MEM_NUM_RAM_BANKS,
186 /* This one is always last */
190 #define MPU_NUM_AXES (3)
192 /*---- structure containing control variables used by MLDL ----*/
193 /*---- MPU clock source settings ----*/
194 /*---- MPU filter selections ----*/
196 MPU_FILTER_256HZ_NOLPF2 = 0,
203 MPU_FILTER_2100HZ_NOLPF,
216 MPU_CLK_SEL_INTERNAL = 0,
217 MPU_CLK_SEL_PLLGYROX,
218 MPU_CLK_SEL_PLLGYROY,
219 MPU_CLK_SEL_PLLGYROZ,
220 MPU_CLK_SEL_PLLEXT32K,
221 MPU_CLK_SEL_PLLEXT19M,
222 MPU_CLK_SEL_RESERVED,
228 MPU_EXT_SYNC_NONE = 0,
239 #define DLPF_FS_SYNC_VALUE(ext_sync, full_scale, lpf) \
240 ((ext_sync << 5) | (full_scale << 3) | lpf)
242 #endif /* __MPU3050_H_ */