3 Copyright (C) 2010 InvenSense Corporation, All Rights Reserved.
19 #define MPU_NAME "mpu6000"
20 #define DEFAULT_MPU_SLAVEADDR 0x68
22 /*==== M_HW REGISTER SET ====*/
24 MPUREG_XG_OFFS_TC = 0,
35 MPUREG_ZA_OFFS_L_TC, /* 0xB */
49 MPUREG_SMPLRT_DIV, /* 0x19 */
50 MPUREG_CONFIG, /* 0x1A ==> DLPF_FS_SYNC */
57 MPUREG_ACCEL_ZRMOT_THR,
58 MPUREG_ACCEL_ZRMOT_DUR,
59 MPUREG_FIFO_EN, /* 0x23 */
61 MPUREG_I2C_SLV0_ADDR, /* 0x25 */
64 MPUREG_I2C_SLV1_ADDR, /* 0x28 */
65 MPUREG_I2C_SLV1_REG_PASSWORD,
67 MPUREG_I2C_SLV2_ADDR, /* 0x2B */
70 MPUREG_I2C_SLV3_ADDR, /* 0x2E */
73 MPUREG_I2C_SLV4_ADDR, /* 0x31 */
78 MPUREG_I2C_MST_STATUS, /* 0x36 */
79 MPUREG_INT_PIN_CFG, /* 0x37 ==> -* INT_CFG */
80 MPUREG_INT_ENABLE, /* 0x38 ==> / */
81 MPUREG_DMP_INT_STATUS, /* 0x39 */
82 MPUREG_INT_STATUS, /* 0x3A */
83 MPUREG_ACCEL_XOUT_H, /* 0x3B */
89 MPUREG_TEMP_OUT_H, /* 0x41 */
91 MPUREG_GYRO_XOUT_H, /* 0x43 */
97 MPUREG_EXT_SLV_SENS_DATA_00, /* 0x49 */
98 MPUREG_EXT_SLV_SENS_DATA_01,
99 MPUREG_EXT_SLV_SENS_DATA_02,
100 MPUREG_EXT_SLV_SENS_DATA_03,
101 MPUREG_EXT_SLV_SENS_DATA_04,
102 MPUREG_EXT_SLV_SENS_DATA_05,
103 MPUREG_EXT_SLV_SENS_DATA_06, /* 0x4F */
104 MPUREG_EXT_SLV_SENS_DATA_07,
105 MPUREG_EXT_SLV_SENS_DATA_08,
106 MPUREG_EXT_SLV_SENS_DATA_09,
107 MPUREG_EXT_SLV_SENS_DATA_10,
108 MPUREG_EXT_SLV_SENS_DATA_11,
109 MPUREG_EXT_SLV_SENS_DATA_12, /* 0x55 */
110 MPUREG_EXT_SLV_SENS_DATA_13,
111 MPUREG_EXT_SLV_SENS_DATA_14,
112 MPUREG_EXT_SLV_SENS_DATA_15,
113 MPUREG_EXT_SLV_SENS_DATA_16,
114 MPUREG_EXT_SLV_SENS_DATA_17,
115 MPUREG_EXT_SLV_SENS_DATA_18, /* 0x5B */
116 MPUREG_EXT_SLV_SENS_DATA_19,
117 MPUREG_EXT_SLV_SENS_DATA_20,
118 MPUREG_EXT_SLV_SENS_DATA_21,
119 MPUREG_EXT_SLV_SENS_DATA_22,
120 MPUREG_EXT_SLV_SENS_DATA_23,
121 ACCEL_INTEL_STATUS, /* 0x61 */
128 SIGNAL_PATH_RESET, /* 0x68 */
129 ACCEL_INTEL_CTRL, /* 0x69 */
130 MPUREG_USER_CTRL, /* 0x6A */
131 MPUREG_PWR_MGMT_1, /* 0x6B */
133 MPUREG_BANK_SEL, /* 0x6D */
134 MPUREG_MEM_START_ADDR, /* 0x6E */
135 MPUREG_MEM_R_W, /* 0x6F */
136 MPUREG_PRGM_STRT_ADDRH,
137 MPUREG_PRGM_STRT_ADDRL,
138 MPUREG_FIFO_COUNTH, /* 0x72 */
140 MPUREG_FIFO_R_W, /* 0x74 */
141 MPUREG_WHOAMI, /* 0x75,117 */
143 NUM_OF_MPU_REGISTERS /* = 0x76,118 */
146 /*==== M_HW MEMORY ====*/
147 enum MPU_MEMORY_BANKS {
160 MPU_MEM_NUM_RAM_BANKS,
161 MPU_MEM_OTP_BANK_0 = 16
165 /*==== M_HW parameters ====*/
167 #define NUM_REGS (NUM_OF_MPU_REGISTERS)
168 #define START_SENS_REGS (0x3B)
169 #define NUM_SENS_REGS (0x60-START_SENS_REGS+1)
171 /*---- MPU Memory ----*/
172 #define NUM_BANKS (MPU_MEM_NUM_RAM_BANKS)
173 #define BANK_SIZE (256)
174 #define MEM_SIZE (NUM_BANKS*BANK_SIZE)
175 #define MPU_MEM_BANK_SIZE (BANK_SIZE) /*alternative name */
177 #define FIFO_HW_SIZE (1024)
179 #define NUM_EXT_SLAVES (4)
182 /*==== BITS FOR M_HW ====*/
184 /*---- M_HW 'FIFO_EN' register (23) ----*/
185 #define BIT_TEMP_OUT 0x80
186 #define BIT_GYRO_XOUT 0x40
187 #define BIT_GYRO_YOUT 0x20
188 #define BIT_GYRO_ZOUT 0x10
189 #define BIT_ACCEL 0x08
190 #define BIT_SLV_2 0x04
191 #define BIT_SLV_1 0x02
192 #define BIT_SLV_0 0x01
193 /*---- M_HW 'CONFIG' register (1A) ----*/
195 #define BITS_EXT_SYNC_SET 0x38
196 #define BITS_DLPF_CFG 0x07
197 /*---- M_HW 'GYRO_CONFIG' register (1B) ----*/
198 /* voluntarily modified label from BITS_FS_SEL to
199 * BITS_GYRO_FS_SEL to avoid confusion with MPU
201 #define BITS_GYRO_FS_SEL 0x18
203 /*---- M_HW 'ACCEL_CONFIG' register (1C) ----*/
204 #define BITS_ACCEL_FS_SEL 0x18
205 #define BITS_ACCEL_HPF 0x07
206 /*---- M_HW 'I2C_MST_CTRL' register (24) ----*/
207 #define BIT_MULT_MST_DIS 0x80
208 #define BIT_WAIT_FOR_ES 0x40
209 #define BIT_I2C_MST_VDDIO 0x20
211 #define BITS_I2C_MST_CLK 0x0F
212 /*---- M_HW 'I2C_SLV?_CTRL' register (27,2A,2D,30) ----*/
213 #define BIT_SLV_ENABLE 0x80
214 #define BIT_SLV_BYTE_SW 0x40
216 #define BIT_SLV_GRP 0x10
217 #define BITS_SLV_LENG 0x0F
218 /*---- M_HW 'I2C_SLV4_ADDR' register (31) ----*/
219 #define BIT_I2C_SLV4_RNW 0x80
220 /*---- M_HW 'I2C_SLV4_CTRL' register (34) ----*/
221 #define BIT_I2C_SLV4_EN 0x80
222 #define BIT_SLV4_DONE_INT_EN 0x40
224 /*---- M_HW 'I2C_MST_STATUS' register (36) ----*/
225 #define BIT_PASSTHROUGH 0x80
226 #define BIT_I2C_SLV4_DONE 0x40
227 #define BIT_I2C_LOST_ARB 0x20
228 #define BIT_I2C_SLV4_NACK 0x10
229 #define BIT_I2C_SLV3_NACK 0x08
230 #define BIT_I2C_SLV2_NACK 0x04
231 #define BIT_I2C_SLV1_NACK 0x02
232 #define BIT_I2C_SLV0_NACK 0x01
233 /*---- M_HW 'INT_PIN_CFG' register (37) ----*/
234 #define BIT_ACTL 0x80
235 #define BIT_ACTL_LOW 0x80
236 #define BIT_ACTL_HIGH 0x00
237 #define BIT_OPEN 0x40
238 #define BIT_LATCH_INT_EN 0x20
239 #define BIT_INT_ANYRD_2CLEAR 0x10
240 #define BIT_ACTL_FSYNC 0x08
241 #define BIT_FSYNC_INT_EN 0x04
242 #define BIT_BYPASS_EN 0x02
243 #define BIT_CLKOUT_EN 0x01
244 /*---- M_HW 'INT_ENABLE' register (38) ----*/
245 #define BIT_FF_EN 0x80
246 #define BIT_MOT_EN 0x40
247 #define BIT_ZMOT_EN 0x20
248 #define BIT_FIFO_OVERFLOW_EN 0x10
249 #define BIT_I2C_MST_INT_EN 0x08
250 #define BIT_PLL_RDY_EN 0x04
251 #define BIT_DMP_INT_EN 0x02
252 #define BIT_RAW_RDY_EN 0x01
253 /*---- M_HW 'DMP_INT_STATUS' register (39) ----*/
256 #define BIT_DMP_INT_5 0x20
257 #define BIT_DMP_INT_4 0x10
258 #define BIT_DMP_INT_3 0x08
259 #define BIT_DMP_INT_2 0x04
260 #define BIT_DMP_INT_1 0x02
261 #define BIT_DMP_INT_0 0x01
262 /*---- M_HW 'INT_STATUS' register (3A) ----*/
263 #define BIT_FF_INT 0x80
264 #define BIT_MOT_INT 0x40
265 #define BIT_ZMOT_INT 0x20
266 #define BIT_FIFO_OVERFLOW_INT 0x10
267 #define BIT_I2C_MST_INT 0x08
268 #define BIT_PLL_RDY_INT 0x04
269 #define BIT_DMP_INT 0x02
270 #define BIT_RAW_DATA_RDY_INT 0x01
271 /*---- M_HW 'BANK_SEL' register (6D) ----*/
272 #define BIT_PRFTCH_EN 0x40
273 #define BIT_CFG_USER_BANK 0x20
274 #define BITS_MEM_SEL 0x1f
275 /*---- M_HW 'USER_CTRL' register (6A) ----*/
276 #define BIT_DMP_EN 0x80
277 #define BIT_FIFO_EN 0x40
278 #define BIT_I2C_MST_EN 0x20
279 #define BIT_I2C_IF_DIS 0x10
280 #define BIT_DMP_RST 0x08
281 #define BIT_FIFO_RST 0x04
282 #define BIT_I2C_MST_RST 0x02
283 #define BIT_SIG_COND_RST 0x01
284 /*---- M_HW 'PWR_MGMT_1' register (6B) ----*/
285 #define BIT_H_RESET 0x80
286 #define BITS_PWRSEL 0x70
287 #define BIT_WKUP_INT 0x08
288 #define BITS_CLKSEL 0x07
289 /*---- M_HW 'PWR_MGMT_2' register (6C) ----*/
290 #define BITS_LPA_WAKE_CTRL 0xC0
291 #define BIT_STBY_XA 0x20
292 #define BIT_STBY_YA 0x10
293 #define BIT_STBY_ZA 0x08
294 #define BIT_STBY_XG 0x04
295 #define BIT_STBY_YG 0x02
296 #define BIT_STBY_ZG 0x01
298 /* although it has 6, this refers to the gyros */
299 #define MPU_NUM_AXES (3)
301 /*----------------------------------------------------------------------------*/
302 /*---- Alternative names to take care of conflicts with current mpu3050.h ----*/
303 /*----------------------------------------------------------------------------*/
306 #define MPUREG_DLPF_FS_SYNC MPUREG_CONFIG /* 0x1A */
308 #define MPUREG_PRODUCT_ID MPUREG_WHOAMI /* 0x75 HACK!*/
309 #define MPUREG_PWR_MGM MPUREG_PWR_MGMT_1 /* 0x6B */
310 #define MPUREG_FIFO_EN1 MPUREG_FIFO_EN /* 0x23 */
311 #define MPUREG_DMP_CFG_1 MPUREG_PRGM_STRT_ADDRH /* 0x70 */
312 #define MPUREG_DMP_CFG_2 MPUREG_PRGM_STRT_ADDRL /* 0x71 */
313 #define MPUREG_INT_CFG MPUREG_INT_ENABLE /* 0x38 */
314 #define MPUREG_X_OFFS_USRH MPUREG_XG_OFFS_USRH /* 0x13 */
315 #define MPUREG_WHO_AM_I MPUREG_WHOAMI /* 0x75 */
316 #define MPUREG_23_RSVD MPUREG_EXT_SLV_SENS_DATA_00 /* 0x49 */
317 #define MPUREG_AUX_SLV_ADDR MPUREG_I2C_SLV0_ADDR /* 0x25 */
318 #define MPUREG_ACCEL_BURST_ADDR MPUREG_I2C_SLV0_REG /* 0x26 */
321 /* 'USER_CTRL' register */
322 #define BIT_AUX_IF_EN BIT_I2C_MST_EN
323 #define BIT_AUX_RD_LENG BIT_I2C_MST_EN
324 #define BIT_IME_IF_RST BIT_I2C_MST_RST
325 #define BIT_GYRO_RST BIT_SIG_COND_RST
326 /* 'INT_ENABLE' register */
327 #define BIT_RAW_RDY BIT_RAW_DATA_RDY_INT
328 #define BIT_MPU_RDY_EN BIT_PLL_RDY_EN
329 /* 'INT_STATUS' register */
330 #define BIT_INT_STATUS_FIFO_OVERLOW BIT_FIFO_OVERFLOW_INT
334 /*---- M_HW Silicon Revisions ----*/
335 #define MPU_SILICON_REV_A1 1 /* M_HW A1 Device */
336 #define MPU_SILICON_REV_B1 2 /* M_HW B1 Device */
338 /*---- structure containing control variables used by MLDL ----*/
339 /*---- MPU clock source settings ----*/
340 /*---- MPU filter selections ----*/
342 MPU_FILTER_256HZ_NOLPF2 = 0,
349 MPU_FILTER_2100HZ_NOLPF,
362 MPU_CLK_SEL_INTERNAL = 0,
363 MPU_CLK_SEL_PLLGYROX,
364 MPU_CLK_SEL_PLLGYROY,
365 MPU_CLK_SEL_PLLGYROZ,
366 MPU_CLK_SEL_PLLEXT32K,
367 MPU_CLK_SEL_PLLEXT19M,
368 MPU_CLK_SEL_RESERVED,
374 MPU_EXT_SYNC_NONE = 0,
385 #define DLPF_FS_SYNC_VALUE(ext_sync, full_scale, lpf) \
386 ((ext_sync << 5) | (full_scale << 3) | lpf)
388 #endif /* __IMU6000_H_ */