2 * Definitions for mma8452 compass chip.
7 #include <linux/ioctl.h>
9 #define MPU6500_PRECISION 16
10 #define MPU6500_RANGE 2000000
12 #define MPU6500_SMPLRT_DIV 0x19
13 #define MPU6500_CONFIG 0x1A
14 #define MPU6500_GYRO_CONFIG 0x1B
15 #define MPU6500_ACCEL_CONFIG 0x1C
16 #define MPU6500_ACCEL_CONFIG2 0x1D
17 #define MPU6500_LP_ACCEL_ODR 0x1E
18 #define MPU6500_WOM_THRESH 0x1F
19 #define MPU6500_FIFO_EN 0x23
20 #define MPU6500_INT_PIN_CFG 0x37
21 #define MPU6500_INT_ENABLE 0x38
22 #define MPU6500_DMP_INT_STATUS 0x39
23 #define MPU6500_INT_STATUS 0x3A
24 #define MPU6500_ACCEL_XOUT_H 0x3B
25 #define MPU6500_TEMP_OUT_H 0x41
26 #define MPU6500_GYRO_XOUT_H 0x43
27 #define MPU6500_ACCEL_INTEL_CTRL 0x69
28 #define MPU6500_USER_CTRL 0x6A
29 #define MPU6500_PWR_MGMT_1 0x6B
30 #define MPU6500_PWR_MGMT_2 0x6C
31 #define MPU6500_PRGM_STRT_ADDRH 0x70
32 #define MPU6500_FIFO_COUNTH 0x72
33 #define MPU6500_FIFO_R_W 0x74
34 #define MPU6500_WHOAMI 0x75
36 #define MPU6500_DEVICE_ID 0x70
37 /*------------------------------
39 --------------------------------*/
40 #define DLPF_CFG_250HZ 0x00
41 #define DLPF_CFG_184HZ 0x01
42 #define DLPF_CFG_98HZ 0x02
43 #define DLPF_CFG_41HZ 0x03
44 #define DLPF_CFG_20HZ 0x04
45 #define DLPF_CFG_10HZ 0x05
46 #define DLPF_CFG_5HZ 0x06
47 #define DLPF_CFG_3600HZ 0x07
48 #define EXT_SYNC_SET_TEMP 0x08
49 #define EXT_SYNC_SET_GYRO_X 0x10
50 #define EXT_SYNC_SET_GYRO_Y 0x18
51 #define EXT_SYNC_SET_GYRO_Z 0x20
52 #define EXT_SYNC_SET_ACCEL_X 0x28
53 #define EXT_SYNC_SET_ACCEL_Y 0x30
54 #define EXT_SYNC_SET_ACCEL_Z 0x38
57 /*------------------------------
59 --------------------------------*/
60 #define GFSR_250DPS (0 <<3)
61 #define GFSR_500DPS (1 <<3)
62 #define GFSR_1000DPS (2 <<3)
63 #define GFSR_2000DPS (3 <<3)
65 /*------------------------------
67 --------------------------------*/
68 #define AFSR_2G (0 <<3)
69 #define AFSR_4G (1 <<3)
70 #define AFSR_8G (2 <<3)
71 #define AFSR_16G (3 <<3)
74 /*------------------------------
76 --------------------------------*/
77 #define A_DLPF_CFG_460HZ 0x00
78 #define A_DLPF_CFG_184HZ 0x01
79 #define A_DLPF_CFG_92HZ 0x02
80 #define A_DLPF_CFG_41HZ 0x03
81 #define A_DLPF_CFG_20HZ 0x04
82 #define A_DLPF_CFG_10HZ 0x05
83 #define A_DLPF_CFG_5HZ 0x06
84 //#define A_DLPF_CFG_460HZ 0x07
85 #define BIT_FIFO_SIZE_1K 0x40
86 #define BIT_ACCEL_FCHOICE_B 0x08
89 /*------------------------------
91 --------------------------------*/
92 #define LPA_CLK_P24HZ 0x0
93 #define LPA_CLK_P49HZ 0x1
94 #define LPA_CLK_P98HZ 0x2
95 #define LPA_CLK_1P95HZ 0x3
96 #define LPA_CLK_3P91HZ 0x4
97 #define LPA_CLK_7P81HZ 0x5
98 #define LPA_CLK_15P63HZ 0x6
99 #define LPA_CLK_31P25HZ 0x7
100 #define LPA_CLK_62P50HZ 0x8
101 #define LPA_CLK_125HZ 0x9
102 #define LPA_CLK_250HZ 0xa
103 #define LPA_CLK_500HZ 0xb
106 /*------------------------------
108 --------------------------------*/
109 #define BIT_H_RESET (1<<7)
110 #define BIT_SLEEP (1<<6)
111 #define BIT_CYCLE (1<<5)
112 #define BIT_GYRO_STANDBY (1<<4)
113 #define BIT_PD_PTAT (1<<3)
114 #define BIT_CLKSEL (1<<0)
116 #define CLKSEL_INTERNAL 0
119 /*------------------------------
121 --------------------------------*/
122 #define BIT_ACCEL_STBY 0x38
123 #define BIT_GYRO_STBY 0x07
124 #define BITS_LPA_WAKE_CTRL 0xC0
125 #define BITS_LPA_WAKE_1HZ 0x00
126 #define BITS_LPA_WAKE_2HZ 0x40
127 #define BITS_LPA_WAKE_20HZ 0x80
129 #define MPU6500_PWRM1_SLEEP 0x40
130 #define MPU6500_PWRM1_GYRO_STANDBY 0x10
131 #define MPU6500_PWRM2_ACCEL_DISABLE 0x38
132 #define MPU6500_PWRM2_GYRO_DISABLE 0x07
134 /*------------------------------
135 MPU6500_ACCEL_INTEL_CTRL
136 --------------------------------*/
137 #define BIT_ACCEL_INTEL_EN 0x80
138 #define BIT_ACCEL_INTEL_MODE 0x40
141 /*------------------------------
143 --------------------------------*/
144 #define BIT_FIFO_RST 0x04
145 #define BIT_DMP_RST 0x08
146 #define BIT_I2C_MST_EN 0x20
147 #define BIT_FIFO_EN 0x40
148 #define BIT_DMP_EN 0x80
151 /*------------------------------
153 --------------------------------*/
154 #define BIT_ACCEL_OUT 0x08
155 #define BITS_GYRO_OUT 0x70
158 /*------------------------------
160 --------------------------------*/
161 #define BIT_BYPASS_EN 0x2
163 /*------------------------------
164 MPU6500_INT_EN/INT_STATUS
165 --------------------------------*/
166 #define BIT_FIFO_OVERLOW 0x80
167 #define BIT_MOT_INT 0x40
168 #define BIT_MPU_RDY 0x04
169 #define BIT_DMP_INT 0x02
170 #define BIT_RAW_RDY 0x01
173 #define DMP_START_ADDR 0x400
178 #define AXIS_ADC_BYTE 2
179 #define SENSOR_PACKET (AXIS_NUM * AXIS_ADC_BYTE)
189 #define DEF_ST_PRECISION 1000
190 #define DEF_ST_MPU6500_ACCEL_LPF 2
191 #define DEF_STABLE_TIME_ST 50
192 #define DEF_SELFTEST_GYRO_FS (0 << 3)
193 #define DEF_SELFTEST_ACCEL_FS (2 << 3)
194 #define DEF_SELFTEST_6500_ACCEL_FS (0 << 3)
195 #define DEF_SW_SELFTEST_GYRO_FS GFSR_2000DPS
196 #define DEF_SW_SELFTEST_SENSITIVITY \
197 (2000*DEF_ST_PRECISION)/32768
199 #define DEF_SW_SELFTEST_SAMPLE_COUNT 75
200 #define DEF_SW_SELFTEST_SAMPLE_TIME 75
201 #define DEF_SW_ACCEL_CAL_SAMPLE_TIME 50
202 #define DEF_SW_SKIP_COUNT 10
204 #define DEF_ST_6500_STABLE_TIME 20
205 #define BYTES_PER_SENSOR (6)
206 #define DEF_SELFTEST_SAMPLE_RATE 0
207 #define DEF_GYRO_WAIT_TIME 50
208 #define THREE_AXIS (3)
209 #define INIT_ST_SAMPLES 200
210 #define FIFO_COUNT_BYTE (2)
211 #define DEF_ST_TRY_TIMES 2
212 #define REG_6500_XG_ST_DATA 0x0
213 #define REG_6500_XA_ST_DATA 0xD
214 #define BITS_SELF_TEST_EN 0xE0
216 #define DEF_ST_SCALE (1L << 15)
218 /*---- MPU6500 Self Test Pass/Fail Criteria ----*/
219 /* Gyro Offset Max Value (dps) */
220 #define DEF_GYRO_OFFSET_MAX 20
221 /* Gyro Self Test Absolute Limits ST_AL (dps) */
222 #define DEF_GYRO_ST_AL 60
223 /* Accel Self Test Absolute Limits ST_AL (mg) */
224 #define DEF_ACCEL_ST_AL_MIN 225
225 #define DEF_ACCEL_ST_AL_MAX 675
226 #define DEF_6500_ACCEL_ST_SHIFT_DELTA 500
227 #define DEF_6500_GYRO_CT_SHIFT_DELTA 500
228 #define DEF_ST_MPU6500_ACCEL_LPF 2
229 #define DEF_ST_6500_ACCEL_FS_MG 2000UL
230 #define DEF_SELFTEST_6500_ACCEL_FS (0 << 3)
232 #define DEF_SELFTEST_GYRO_SENS (32768 / 250)
235 #define GSENSOR_DEV_PATH "/dev/mma8452_daemon"