2 * Copyright (C) 2014 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #ifndef __LINUX_MTD_SPI_NOR_H
11 #define __LINUX_MTD_SPI_NOR_H
13 #include <linux/bitops.h>
16 * Note on opcode nomenclature: some opcodes have a format like
17 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
18 * of I/O lines used for the opcode, address, and data (respectively). The
19 * FUNCTION has an optional suffix of '4', to represent an opcode which
20 * requires a 4-byte (32-bit) address.
24 #define SPINOR_OP_WREN 0x06 /* Write enable */
25 #define SPINOR_OP_RDSR 0x05 /* Read status register */
26 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
27 #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
28 #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
29 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual SPI) */
30 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad SPI) */
31 #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
32 #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
33 #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
34 #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
35 #define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
36 #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
37 #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
38 #define SPINOR_OP_RDCR 0x35 /* Read configuration register */
39 #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
41 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
42 #define SPINOR_OP_READ4 0x13 /* Read data bytes (low frequency) */
43 #define SPINOR_OP_READ4_FAST 0x0c /* Read data bytes (high frequency) */
44 #define SPINOR_OP_READ4_1_1_2 0x3c /* Read data bytes (Dual SPI) */
45 #define SPINOR_OP_READ4_1_1_4 0x6c /* Read data bytes (Quad SPI) */
46 #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
47 #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
49 /* Used for SST flashes only. */
50 #define SPINOR_OP_BP 0x02 /* Byte program */
51 #define SPINOR_OP_WRDI 0x04 /* Write disable */
52 #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
54 /* Used for Macronix and Winbond flashes. */
55 #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
56 #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
58 /* Used for Spansion flashes only. */
59 #define SPINOR_OP_BRWR 0x17 /* Bank register write */
61 /* Used for Micron flashes only. */
62 #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
63 #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
65 /* Status Register bits. */
66 #define SR_WIP BIT(0) /* Write in progress */
67 #define SR_WEL BIT(1) /* Write enable latch */
68 /* meaning of other SR_* bits may differ between vendors */
69 #define SR_BP0 BIT(2) /* Block protect 0 */
70 #define SR_BP1 BIT(3) /* Block protect 1 */
71 #define SR_BP2 BIT(4) /* Block protect 2 */
72 #define SR_SRWD BIT(7) /* SR write protect */
74 #define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
76 /* Enhanced Volatile Configuration Register bits */
77 #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
79 /* Flag Status Register bits */
80 #define FSR_READY BIT(7)
82 /* Configuration Register bits. */
83 #define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
92 #define SPI_NOR_MAX_CMD_SIZE 8
101 enum spi_nor_option_flags {
102 SNOR_F_USE_FSR = BIT(0),
108 * struct spi_nor - Structure for defining a the SPI NOR layer
109 * @mtd: point to a mtd_info structure
110 * @lock: the lock for the read/write/erase/lock/unlock operations
111 * @dev: point to a spi device, or a spi nor controller device.
112 * @flash_node: point to a device node describing this flash instance.
113 * @page_size: the page size of the SPI NOR
114 * @addr_width: number of address bytes
115 * @erase_opcode: the opcode for erasing a sector
116 * @read_opcode: the read opcode
117 * @read_dummy: the dummy needed by the read operation
118 * @program_opcode: the program opcode
119 * @flash_read: the mode of the read
120 * @sst_write_second: used by the SST write operation
121 * @flags: flag options for the current SPI-NOR (SNOR_F_*)
122 * @cmd_buf: used by the write_reg
123 * @prepare: [OPTIONAL] do some preparations for the
124 * read/write/erase/lock/unlock operations
125 * @unprepare: [OPTIONAL] do some post work after the
126 * read/write/erase/lock/unlock operations
127 * @read_reg: [DRIVER-SPECIFIC] read out the register
128 * @write_reg: [DRIVER-SPECIFIC] write data to the register
129 * @read: [DRIVER-SPECIFIC] read data from the SPI NOR
130 * @write: [DRIVER-SPECIFIC] write data to the SPI NOR
131 * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
132 * at the offset @offs
133 * @lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
134 * @unlock: [FLASH-SPECIFIC] unlock a region of the SPI NOR
135 * @priv: the private data
141 struct device_node *flash_node;
148 enum read_mode flash_read;
149 bool sst_write_second;
151 u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
153 int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
154 void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
155 int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
156 int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
158 int (*read)(struct spi_nor *nor, loff_t from,
159 size_t len, size_t *retlen, u_char *read_buf);
160 void (*write)(struct spi_nor *nor, loff_t to,
161 size_t len, size_t *retlen, const u_char *write_buf);
162 int (*erase)(struct spi_nor *nor, loff_t offs);
164 int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
165 int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
171 * spi_nor_scan() - scan the SPI NOR
172 * @nor: the spi_nor structure
173 * @name: the chip type name
174 * @mode: the read mode supported by the driver
176 * The drivers can use this fuction to scan the SPI NOR.
177 * In the scanning, it will try to get all the necessary information to
178 * fill the mtd_info{} and the spi_nor{}.
180 * The chip type name can be provided through the @name parameter.
182 * Return: 0 for success, others for failure.
184 int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode);