2 * Copyright (C) 2014 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #ifndef __LINUX_MTD_SPI_NOR_H
11 #define __LINUX_MTD_SPI_NOR_H
14 * Note on opcode nomenclature: some opcodes have a format like
15 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
16 * of I/O lines used for the opcode, address, and data (respectively). The
17 * FUNCTION has an optional suffix of '4', to represent an opcode which
18 * requires a 4-byte (32-bit) address.
22 #define SPINOR_OP_WREN 0x06 /* Write enable */
23 #define SPINOR_OP_RDSR 0x05 /* Read status register */
24 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
25 #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
26 #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
27 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual SPI) */
28 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad SPI) */
29 #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
30 #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
31 #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
32 #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
33 #define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
34 #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
35 #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
36 #define SPINOR_OP_RDCR 0x35 /* Read configuration register */
37 #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
39 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
40 #define SPINOR_OP_READ4 0x13 /* Read data bytes (low frequency) */
41 #define SPINOR_OP_READ4_FAST 0x0c /* Read data bytes (high frequency) */
42 #define SPINOR_OP_READ4_1_1_2 0x3c /* Read data bytes (Dual SPI) */
43 #define SPINOR_OP_READ4_1_1_4 0x6c /* Read data bytes (Quad SPI) */
44 #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
45 #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
47 /* Used for SST flashes only. */
48 #define SPINOR_OP_BP 0x02 /* Byte program */
49 #define SPINOR_OP_WRDI 0x04 /* Write disable */
50 #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
52 /* Used for Macronix and Winbond flashes. */
53 #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
54 #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
56 /* Used for Spansion flashes only. */
57 #define SPINOR_OP_BRWR 0x17 /* Bank register write */
59 /* Status Register bits. */
60 #define SR_WIP 1 /* Write in progress */
61 #define SR_WEL 2 /* Write enable latch */
62 /* meaning of other SR_* bits may differ between vendors */
63 #define SR_BP0 4 /* Block protect 0 */
64 #define SR_BP1 8 /* Block protect 1 */
65 #define SR_BP2 0x10 /* Block protect 2 */
66 #define SR_SRWD 0x80 /* SR write protect */
68 #define SR_QUAD_EN_MX 0x40 /* Macronix Quad I/O */
70 /* Flag Status Register bits */
71 #define FSR_READY 0x80
73 /* Configuration Register bits. */
74 #define CR_QUAD_EN_SPAN 0x2 /* Spansion Quad I/O */
84 * struct spi_nor_xfer_cfg - Structure for defining a Serial Flash transfer
85 * @wren: command for "Write Enable", or 0x00 for not required
86 * @cmd: command for operation
87 * @cmd_pins: number of pins to send @cmd (1, 2, 4)
88 * @addr: address for operation
89 * @addr_pins: number of pins to send @addr (1, 2, 4)
90 * @addr_width: number of address bytes
91 * (3,4, or 0 for address not required)
93 * @mode_pins: number of pins to send @mode (1, 2, 4)
94 * @mode_cycles: number of mode cycles (0 for mode not required)
95 * @dummy_cycles: number of dummy cycles (0 for dummy not required)
97 struct spi_nor_xfer_cfg {
110 #define SPI_NOR_MAX_CMD_SIZE 8
112 SPI_NOR_OPS_READ = 0,
120 * struct spi_nor - Structure for defining a the SPI NOR layer
121 * @mtd: point to a mtd_info structure
122 * @lock: the lock for the read/write/erase/lock/unlock operations
123 * @dev: point to a spi device, or a spi nor controller device.
124 * @page_size: the page size of the SPI NOR
125 * @addr_width: number of address bytes
126 * @erase_opcode: the opcode for erasing a sector
127 * @read_opcode: the read opcode
128 * @read_dummy: the dummy needed by the read operation
129 * @program_opcode: the program opcode
130 * @flash_read: the mode of the read
131 * @sst_write_second: used by the SST write operation
132 * @cfg: used by the read_xfer/write_xfer
133 * @cmd_buf: used by the write_reg
134 * @prepare: [OPTIONAL] do some preparations for the
135 * read/write/erase/lock/unlock operations
136 * @unprepare: [OPTIONAL] do some post work after the
137 * read/write/erase/lock/unlock operations
138 * @read_xfer: [OPTIONAL] the read fundamental primitive
139 * @write_xfer: [OPTIONAL] the writefundamental primitive
140 * @read_reg: [DRIVER-SPECIFIC] read out the register
141 * @write_reg: [DRIVER-SPECIFIC] write data to the register
142 * @read_id: [REPLACEABLE] read out the ID data, and find
143 * the proper spi_device_id
144 * @wait_till_ready: [REPLACEABLE] wait till the NOR becomes ready
145 * @read: [DRIVER-SPECIFIC] read data from the SPI NOR
146 * @write: [DRIVER-SPECIFIC] write data to the SPI NOR
147 * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
148 * at the offset @offs
149 * @priv: the private data
152 struct mtd_info *mtd;
161 enum read_mode flash_read;
162 bool sst_write_second;
163 struct spi_nor_xfer_cfg cfg;
164 u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
166 int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
167 void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
168 int (*read_xfer)(struct spi_nor *nor, struct spi_nor_xfer_cfg *cfg,
169 u8 *buf, size_t len);
170 int (*write_xfer)(struct spi_nor *nor, struct spi_nor_xfer_cfg *cfg,
171 u8 *buf, size_t len);
172 int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
173 int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len,
175 const struct spi_device_id *(*read_id)(struct spi_nor *nor);
176 int (*wait_till_ready)(struct spi_nor *nor);
178 int (*read)(struct spi_nor *nor, loff_t from,
179 size_t len, size_t *retlen, u_char *read_buf);
180 void (*write)(struct spi_nor *nor, loff_t to,
181 size_t len, size_t *retlen, const u_char *write_buf);
182 int (*erase)(struct spi_nor *nor, loff_t offs);
188 * spi_nor_scan() - scan the SPI NOR
189 * @nor: the spi_nor structure
190 * @name: the chip type name
191 * @mode: the read mode supported by the driver
193 * The drivers can use this fuction to scan the SPI NOR.
194 * In the scanning, it will try to get all the necessary information to
195 * fill the mtd_info{} and the spi_nor{}.
197 * The chip type name can be provided through the @name parameter.
199 * Return: 0 for success, others for failure.
201 int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode);