4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
20 #include <linux/mod_devicetable.h>
22 #include <linux/types.h>
23 #include <linux/init.h>
24 #include <linux/ioport.h>
25 #include <linux/list.h>
26 #include <linux/compiler.h>
27 #include <linux/errno.h>
28 #include <linux/kobject.h>
29 #include <linux/atomic.h>
30 #include <linux/device.h>
32 #include <linux/irqreturn.h>
33 #include <uapi/linux/pci.h>
35 /* Include the ID list */
36 #include <linux/pci_ids.h>
38 /* pci_slot represents a physical slot */
40 struct pci_bus *bus; /* The bus this slot is on */
41 struct list_head list; /* node in list of slots on this bus */
42 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
43 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
47 static inline const char *pci_slot_name(const struct pci_slot *slot)
49 return kobject_name(&slot->kobj);
52 /* File state for mmap()s on /proc/bus/pci/X/Y */
58 /* This defines the direction arg to the DMA mapping routines. */
59 #define PCI_DMA_BIDIRECTIONAL 0
60 #define PCI_DMA_TODEVICE 1
61 #define PCI_DMA_FROMDEVICE 2
62 #define PCI_DMA_NONE 3
65 * For PCI devices, the region numbers are assigned this way:
68 /* #0-5: standard PCI resources */
70 PCI_STD_RESOURCE_END = 5,
72 /* #6: expansion ROM resource */
75 /* device specific resources */
78 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
81 /* resources assigned to buses behind the bridge */
82 #define PCI_BRIDGE_RESOURCE_NUM 4
85 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
86 PCI_BRIDGE_RESOURCE_NUM - 1,
88 /* total resources associated with a PCI device */
91 /* preserve this for compatibility */
92 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
95 typedef int __bitwise pci_power_t;
97 #define PCI_D0 ((pci_power_t __force) 0)
98 #define PCI_D1 ((pci_power_t __force) 1)
99 #define PCI_D2 ((pci_power_t __force) 2)
100 #define PCI_D3hot ((pci_power_t __force) 3)
101 #define PCI_D3cold ((pci_power_t __force) 4)
102 #define PCI_UNKNOWN ((pci_power_t __force) 5)
103 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
105 /* Remember to update this when the list above changes! */
106 extern const char *pci_power_names[];
108 static inline const char *pci_power_name(pci_power_t state)
110 return pci_power_names[1 + (int) state];
113 #define PCI_PM_D2_DELAY 200
114 #define PCI_PM_D3_WAIT 10
115 #define PCI_PM_D3COLD_WAIT 100
116 #define PCI_PM_BUS_WAIT 50
118 /** The pci_channel state describes connectivity between the CPU and
119 * the pci device. If some PCI bus between here and the pci device
120 * has crashed or locked up, this info is reflected here.
122 typedef unsigned int __bitwise pci_channel_state_t;
124 enum pci_channel_state {
125 /* I/O channel is in normal state */
126 pci_channel_io_normal = (__force pci_channel_state_t) 1,
128 /* I/O to channel is blocked */
129 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
131 /* PCI card is dead */
132 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
135 typedef unsigned int __bitwise pcie_reset_state_t;
137 enum pcie_reset_state {
138 /* Reset is NOT asserted (Use to deassert reset) */
139 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
141 /* Use #PERST to reset PCI-E device */
142 pcie_warm_reset = (__force pcie_reset_state_t) 2,
144 /* Use PCI-E Hot Reset to reset device */
145 pcie_hot_reset = (__force pcie_reset_state_t) 3
148 typedef unsigned short __bitwise pci_dev_flags_t;
150 /* INTX_DISABLE in PCI_COMMAND register disables MSI
153 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
154 /* Device configuration is irrevocably lost if disabled into D3 */
155 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
156 /* Provide indication device is assigned by a Virtual Machine Manager */
157 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4,
160 enum pci_irq_reroute_variant {
161 INTEL_IRQ_REROUTE_VARIANT = 1,
162 MAX_IRQ_REROUTE_VARIANTS = 3
165 typedef unsigned short __bitwise pci_bus_flags_t;
167 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
168 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
171 /* Based on the PCI Hotplug Spec, but some values are made up by us */
173 PCI_SPEED_33MHz = 0x00,
174 PCI_SPEED_66MHz = 0x01,
175 PCI_SPEED_66MHz_PCIX = 0x02,
176 PCI_SPEED_100MHz_PCIX = 0x03,
177 PCI_SPEED_133MHz_PCIX = 0x04,
178 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
179 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
180 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
181 PCI_SPEED_66MHz_PCIX_266 = 0x09,
182 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
183 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
189 PCI_SPEED_66MHz_PCIX_533 = 0x11,
190 PCI_SPEED_100MHz_PCIX_533 = 0x12,
191 PCI_SPEED_133MHz_PCIX_533 = 0x13,
192 PCIE_SPEED_2_5GT = 0x14,
193 PCIE_SPEED_5_0GT = 0x15,
194 PCIE_SPEED_8_0GT = 0x16,
195 PCI_SPEED_UNKNOWN = 0xff,
198 struct pci_cap_saved_data {
204 struct pci_cap_saved_state {
205 struct hlist_node next;
206 struct pci_cap_saved_data cap;
209 struct pcie_link_state;
215 * The pci_dev structure is used to describe PCI devices.
218 struct list_head bus_list; /* node in per-bus list */
219 struct pci_bus *bus; /* bus this device is on */
220 struct pci_bus *subordinate; /* bus this device bridges to */
222 void *sysdata; /* hook for sys-specific extension */
223 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
224 struct pci_slot *slot; /* Physical slot this device is in */
226 unsigned int devfn; /* encoded device & function index */
227 unsigned short vendor;
228 unsigned short device;
229 unsigned short subsystem_vendor;
230 unsigned short subsystem_device;
231 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
232 u8 revision; /* PCI revision, low byte of class word */
233 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
234 u8 pcie_cap; /* PCI-E capability offset */
235 u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */
236 u8 rom_base_reg; /* which config register controls the ROM */
237 u8 pin; /* which interrupt pin this device uses */
238 u16 pcie_flags_reg; /* cached PCI-E Capabilities Register */
240 struct pci_driver *driver; /* which driver has allocated this device */
241 u64 dma_mask; /* Mask of the bits of bus address this
242 device implements. Normally this is
243 0xffffffff. You only need to change
244 this if your device has broken DMA
245 or supports 64-bit transfers. */
247 struct device_dma_parameters dma_parms;
249 pci_power_t current_state; /* Current operating state. In ACPI-speak,
250 this is D0-D3, D0 being fully functional,
252 u8 pm_cap; /* PM capability offset */
253 unsigned int pme_support:5; /* Bitmask of states from which PME#
255 unsigned int pme_interrupt:1;
256 unsigned int pme_poll:1; /* Poll device's PME status bit */
257 unsigned int d1_support:1; /* Low power state D1 is supported */
258 unsigned int d2_support:1; /* Low power state D2 is supported */
259 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
260 unsigned int no_d3cold:1; /* D3cold is forbidden */
261 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
262 unsigned int mmio_always_on:1; /* disallow turning off io/mem
263 decoding during bar sizing */
264 unsigned int wakeup_prepared:1;
265 unsigned int runtime_d3cold:1; /* whether go through runtime
266 D3cold, not set for devices
267 powered on/off by the
268 corresponding bridge */
269 unsigned int d3_delay; /* D3->D0 transition time in ms */
270 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
272 #ifdef CONFIG_PCIEASPM
273 struct pcie_link_state *link_state; /* ASPM link state. */
276 pci_channel_state_t error_state; /* current connectivity state */
277 struct device dev; /* Generic device interface */
279 int cfg_size; /* Size of configuration space */
282 * Instead of touching interrupt line and base address registers
283 * directly, use the values stored here. They might be different!
286 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
288 bool match_driver; /* Skip attaching driver */
289 /* These fields are used by common fixups */
290 unsigned int transparent:1; /* Transparent PCI bridge */
291 unsigned int multifunction:1;/* Part of multi-function device */
292 /* keep track of device state */
293 unsigned int is_added:1;
294 unsigned int is_busmaster:1; /* device is busmaster */
295 unsigned int no_msi:1; /* device may not use msi */
296 unsigned int block_cfg_access:1; /* config space access is blocked */
297 unsigned int broken_parity_status:1; /* Device generates false positive parity */
298 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
299 unsigned int msi_enabled:1;
300 unsigned int msix_enabled:1;
301 unsigned int ari_enabled:1; /* ARI forwarding */
302 unsigned int is_managed:1;
303 unsigned int is_pcie:1; /* Obsolete. Will be removed.
304 Use pci_is_pcie() instead */
305 unsigned int needs_freset:1; /* Dev requires fundamental reset */
306 unsigned int state_saved:1;
307 unsigned int is_physfn:1;
308 unsigned int is_virtfn:1;
309 unsigned int reset_fn:1;
310 unsigned int is_hotplug_bridge:1;
311 unsigned int __aer_firmware_first_valid:1;
312 unsigned int __aer_firmware_first:1;
313 unsigned int broken_intx_masking:1;
314 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
315 pci_dev_flags_t dev_flags;
316 atomic_t enable_cnt; /* pci_enable_device has been called */
318 u32 saved_config_space[16]; /* config space saved at suspend time */
319 struct hlist_head saved_cap_space;
320 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
321 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
322 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
323 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
324 #ifdef CONFIG_PCI_MSI
325 struct list_head msi_list;
326 struct kset *msi_kset;
329 #ifdef CONFIG_PCI_ATS
331 struct pci_sriov *sriov; /* SR-IOV capability related */
332 struct pci_dev *physfn; /* the PF this VF is associated with */
334 struct pci_ats *ats; /* Address Translation Service */
336 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
337 size_t romlen; /* Length of ROM if it's not from the BAR */
340 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
342 #ifdef CONFIG_PCI_IOV
350 extern struct pci_dev *alloc_pci_dev(void);
352 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
353 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
355 static inline int pci_channel_offline(struct pci_dev *pdev)
357 return (pdev->error_state != pci_channel_io_normal);
360 extern struct resource busn_resource;
362 struct pci_host_bridge_window {
363 struct list_head list;
364 struct resource *res; /* host bridge aperture (CPU address) */
365 resource_size_t offset; /* bus address + offset = CPU address */
368 struct pci_host_bridge {
370 struct pci_bus *bus; /* root bus */
371 struct list_head windows; /* pci_host_bridge_windows */
372 void (*release_fn)(struct pci_host_bridge *);
376 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
377 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
378 void (*release_fn)(struct pci_host_bridge *),
381 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
384 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
385 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
386 * buses below host bridges or subtractive decode bridges) go in the list.
387 * Use pci_bus_for_each_resource() to iterate through all the resources.
391 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
392 * and there's no way to program the bridge with the details of the window.
393 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
394 * decode bit set, because they are explicit and can be programmed with _SRS.
396 #define PCI_SUBTRACTIVE_DECODE 0x1
398 struct pci_bus_resource {
399 struct list_head list;
400 struct resource *res;
404 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
407 struct list_head node; /* node in list of buses */
408 struct pci_bus *parent; /* parent bus this bridge is on */
409 struct list_head children; /* list of child buses */
410 struct list_head devices; /* list of devices on this bus */
411 struct pci_dev *self; /* bridge device as seen by parent */
412 struct list_head slots; /* list of slots on this bus */
413 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
414 struct list_head resources; /* address space routed to this bus */
415 struct resource busn_res; /* bus numbers routed to this bus */
417 struct pci_ops *ops; /* configuration access functions */
418 void *sysdata; /* hook for sys-specific extension */
419 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
421 unsigned char number; /* bus number */
422 unsigned char primary; /* number of primary bridge */
423 unsigned char max_bus_speed; /* enum pci_bus_speed */
424 unsigned char cur_bus_speed; /* enum pci_bus_speed */
428 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
429 pci_bus_flags_t bus_flags; /* Inherited by child busses */
430 struct device *bridge;
432 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
433 struct bin_attribute *legacy_mem; /* legacy mem */
434 unsigned int is_added:1;
437 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
438 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
441 * Returns true if the pci bus is root (behind host-pci bridge),
444 static inline bool pci_is_root_bus(struct pci_bus *pbus)
446 return !(pbus->parent);
449 #ifdef CONFIG_PCI_MSI
450 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
452 return pci_dev->msi_enabled || pci_dev->msix_enabled;
455 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
459 * Error values that may be returned by PCI functions.
461 #define PCIBIOS_SUCCESSFUL 0x00
462 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
463 #define PCIBIOS_BAD_VENDOR_ID 0x83
464 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
465 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
466 #define PCIBIOS_SET_FAILED 0x88
467 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
470 * Translate above to generic errno for passing back through non-pci.
472 static inline int pcibios_err_to_errno(int err)
474 if (err <= PCIBIOS_SUCCESSFUL)
475 return err; /* Assume already errno */
478 case PCIBIOS_FUNC_NOT_SUPPORTED:
480 case PCIBIOS_BAD_VENDOR_ID:
482 case PCIBIOS_DEVICE_NOT_FOUND:
484 case PCIBIOS_BAD_REGISTER_NUMBER:
486 case PCIBIOS_SET_FAILED:
488 case PCIBIOS_BUFFER_TOO_SMALL:
495 /* Low-level architecture-dependent routines */
498 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
499 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
503 * ACPI needs to be able to access PCI config space before we've done a
504 * PCI bus scan and created pci_bus structures.
506 extern int raw_pci_read(unsigned int domain, unsigned int bus,
507 unsigned int devfn, int reg, int len, u32 *val);
508 extern int raw_pci_write(unsigned int domain, unsigned int bus,
509 unsigned int devfn, int reg, int len, u32 val);
511 struct pci_bus_region {
512 resource_size_t start;
517 spinlock_t lock; /* protects list, index */
518 struct list_head list; /* for IDs added at runtime */
521 /* ---------------------------------------------------------------- */
522 /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
523 * a set of callbacks in struct pci_error_handlers, then that device driver
524 * will be notified of PCI bus errors, and will be driven to recovery
525 * when an error occurs.
528 typedef unsigned int __bitwise pci_ers_result_t;
530 enum pci_ers_result {
531 /* no result/none/not supported in device driver */
532 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
534 /* Device driver can recover without slot reset */
535 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
537 /* Device driver wants slot to be reset. */
538 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
540 /* Device has completely failed, is unrecoverable */
541 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
543 /* Device driver is fully recovered and operational */
544 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
546 /* No AER capabilities registered for the driver */
547 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
550 /* PCI bus error event callbacks */
551 struct pci_error_handlers {
552 /* PCI bus error detected on this device */
553 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
554 enum pci_channel_state error);
556 /* MMIO has been re-enabled, but not DMA */
557 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
559 /* PCI Express link has been reset */
560 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
562 /* PCI slot has been reset */
563 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
565 /* Device driver may resume normal operations */
566 void (*resume)(struct pci_dev *dev);
569 /* ---------------------------------------------------------------- */
573 struct list_head node;
575 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
576 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
577 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
578 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
579 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
580 int (*resume_early) (struct pci_dev *dev);
581 int (*resume) (struct pci_dev *dev); /* Device woken up */
582 void (*shutdown) (struct pci_dev *dev);
583 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
584 const struct pci_error_handlers *err_handler;
585 struct device_driver driver;
586 struct pci_dynids dynids;
589 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
592 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
593 * @_table: device table name
595 * This macro is used to create a struct pci_device_id array (a device table)
596 * in a generic manner.
598 #define DEFINE_PCI_DEVICE_TABLE(_table) \
599 const struct pci_device_id _table[]
602 * PCI_DEVICE - macro used to describe a specific pci device
603 * @vend: the 16 bit PCI Vendor ID
604 * @dev: the 16 bit PCI Device ID
606 * This macro is used to create a struct pci_device_id that matches a
607 * specific device. The subvendor and subdevice fields will be set to
610 #define PCI_DEVICE(vend,dev) \
611 .vendor = (vend), .device = (dev), \
612 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
615 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
616 * @vend: the 16 bit PCI Vendor ID
617 * @dev: the 16 bit PCI Device ID
618 * @subvend: the 16 bit PCI Subvendor ID
619 * @subdev: the 16 bit PCI Subdevice ID
621 * This macro is used to create a struct pci_device_id that matches a
622 * specific device with subsystem information.
624 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
625 .vendor = (vend), .device = (dev), \
626 .subvendor = (subvend), .subdevice = (subdev)
629 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
630 * @dev_class: the class, subclass, prog-if triple for this device
631 * @dev_class_mask: the class mask for this device
633 * This macro is used to create a struct pci_device_id that matches a
634 * specific PCI class. The vendor, device, subvendor, and subdevice
635 * fields will be set to PCI_ANY_ID.
637 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
638 .class = (dev_class), .class_mask = (dev_class_mask), \
639 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
640 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
643 * PCI_VDEVICE - macro used to describe a specific pci device in short form
644 * @vendor: the vendor name
645 * @device: the 16 bit PCI Device ID
647 * This macro is used to create a struct pci_device_id that matches a
648 * specific PCI device. The subvendor, and subdevice fields will be set
649 * to PCI_ANY_ID. The macro allows the next field to follow as the device
653 #define PCI_VDEVICE(vendor, device) \
654 PCI_VENDOR_ID_##vendor, (device), \
655 PCI_ANY_ID, PCI_ANY_ID, 0, 0
657 /* these external functions are only available when PCI support is enabled */
660 extern void pcie_bus_configure_settings(struct pci_bus *bus, u8 smpss);
662 enum pcie_bus_config_types {
665 PCIE_BUS_PERFORMANCE,
669 extern enum pcie_bus_config_types pcie_bus_config;
671 extern struct bus_type pci_bus_type;
673 /* Do NOT directly access these two variables, unless you are arch specific pci
674 * code, or pci core code. */
675 extern struct list_head pci_root_buses; /* list of all known PCI buses */
676 /* Some device drivers need know if pci is initiated */
677 extern int no_pci_devices(void);
679 void pcibios_resource_survey_bus(struct pci_bus *bus);
680 void pcibios_fixup_bus(struct pci_bus *);
681 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
682 /* Architecture specific versions may override this (weak) */
683 char *pcibios_setup(char *str);
685 /* Used only when drivers/pci/setup.c is used */
686 resource_size_t pcibios_align_resource(void *, const struct resource *,
689 void pcibios_update_irq(struct pci_dev *, int irq);
691 /* Weak but can be overriden by arch */
692 void pci_fixup_cardbus(struct pci_bus *);
694 /* Generic PCI functions used internally */
696 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
697 struct resource *res);
698 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
699 struct pci_bus_region *region);
700 void pcibios_scan_specific_bus(int busn);
701 extern struct pci_bus *pci_find_bus(int domain, int busnr);
702 void pci_bus_add_devices(const struct pci_bus *bus);
703 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
704 struct pci_ops *ops, void *sysdata);
705 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
706 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
707 struct pci_ops *ops, void *sysdata,
708 struct list_head *resources);
709 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
710 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
711 void pci_bus_release_busn_res(struct pci_bus *b);
712 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
713 struct pci_ops *ops, void *sysdata,
714 struct list_head *resources);
715 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
717 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
718 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
720 struct hotplug_slot *hotplug);
721 void pci_destroy_slot(struct pci_slot *slot);
722 void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
723 int pci_scan_slot(struct pci_bus *bus, int devfn);
724 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
725 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
726 unsigned int pci_scan_child_bus(struct pci_bus *bus);
727 int __must_check pci_bus_add_device(struct pci_dev *dev);
728 void pci_read_bridge_bases(struct pci_bus *child);
729 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
730 struct resource *res);
731 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
732 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
733 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
734 extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
735 extern void pci_dev_put(struct pci_dev *dev);
736 extern void pci_remove_bus(struct pci_bus *b);
737 extern void pci_stop_and_remove_bus_device(struct pci_dev *dev);
738 void pci_stop_root_bus(struct pci_bus *bus);
739 void pci_remove_root_bus(struct pci_bus *bus);
740 void pci_setup_cardbus(struct pci_bus *bus);
741 extern void pci_sort_breadthfirst(void);
742 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
743 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
744 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
746 /* Generic PCI functions exported to card drivers */
748 enum pci_lost_interrupt_reason {
749 PCI_LOST_IRQ_NO_INFORMATION = 0,
750 PCI_LOST_IRQ_DISABLE_MSI,
751 PCI_LOST_IRQ_DISABLE_MSIX,
752 PCI_LOST_IRQ_DISABLE_ACPI,
754 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
755 int pci_find_capability(struct pci_dev *dev, int cap);
756 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
757 int pci_find_ext_capability(struct pci_dev *dev, int cap);
758 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
759 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
760 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
761 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
763 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
764 struct pci_dev *from);
765 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
766 unsigned int ss_vendor, unsigned int ss_device,
767 struct pci_dev *from);
768 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
769 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
771 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
774 return pci_get_domain_bus_and_slot(0, bus, devfn);
776 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
777 int pci_dev_present(const struct pci_device_id *ids);
779 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
781 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
782 int where, u16 *val);
783 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
784 int where, u32 *val);
785 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
787 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
789 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
791 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
793 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
795 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
797 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
799 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
801 static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
804 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
806 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
808 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
810 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
812 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
814 static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
817 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
820 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
821 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
822 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
823 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
824 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
826 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
829 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
832 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
835 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
838 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
841 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
844 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
847 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
850 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
853 /* user-space driven config access */
854 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
855 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
856 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
857 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
858 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
859 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
861 int __must_check pci_enable_device(struct pci_dev *dev);
862 int __must_check pci_enable_device_io(struct pci_dev *dev);
863 int __must_check pci_enable_device_mem(struct pci_dev *dev);
864 int __must_check pci_reenable_device(struct pci_dev *);
865 int __must_check pcim_enable_device(struct pci_dev *pdev);
866 void pcim_pin_device(struct pci_dev *pdev);
868 static inline int pci_is_enabled(struct pci_dev *pdev)
870 return (atomic_read(&pdev->enable_cnt) > 0);
873 static inline int pci_is_managed(struct pci_dev *pdev)
875 return pdev->is_managed;
878 void pci_disable_device(struct pci_dev *dev);
880 extern unsigned int pcibios_max_latency;
881 void pci_set_master(struct pci_dev *dev);
882 void pci_clear_master(struct pci_dev *dev);
884 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
885 int pci_set_cacheline_size(struct pci_dev *dev);
886 #define HAVE_PCI_SET_MWI
887 int __must_check pci_set_mwi(struct pci_dev *dev);
888 int pci_try_set_mwi(struct pci_dev *dev);
889 void pci_clear_mwi(struct pci_dev *dev);
890 void pci_intx(struct pci_dev *dev, int enable);
891 bool pci_intx_mask_supported(struct pci_dev *dev);
892 bool pci_check_and_mask_intx(struct pci_dev *dev);
893 bool pci_check_and_unmask_intx(struct pci_dev *dev);
894 void pci_msi_off(struct pci_dev *dev);
895 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
896 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
897 int pcix_get_max_mmrbc(struct pci_dev *dev);
898 int pcix_get_mmrbc(struct pci_dev *dev);
899 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
900 int pcie_get_readrq(struct pci_dev *dev);
901 int pcie_set_readrq(struct pci_dev *dev, int rq);
902 int pcie_get_mps(struct pci_dev *dev);
903 int pcie_set_mps(struct pci_dev *dev, int mps);
904 int __pci_reset_function(struct pci_dev *dev);
905 int __pci_reset_function_locked(struct pci_dev *dev);
906 int pci_reset_function(struct pci_dev *dev);
907 void pci_update_resource(struct pci_dev *dev, int resno);
908 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
909 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
910 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
912 /* ROM control related routines */
913 int pci_enable_rom(struct pci_dev *pdev);
914 void pci_disable_rom(struct pci_dev *pdev);
915 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
916 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
917 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
919 /* Power management related routines */
920 int pci_save_state(struct pci_dev *dev);
921 void pci_restore_state(struct pci_dev *dev);
922 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
923 int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state);
924 int pci_load_and_free_saved_state(struct pci_dev *dev,
925 struct pci_saved_state **state);
926 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
927 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
928 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
929 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
930 void pci_pme_active(struct pci_dev *dev, bool enable);
931 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
932 bool runtime, bool enable);
933 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
934 pci_power_t pci_target_state(struct pci_dev *dev);
935 int pci_prepare_to_sleep(struct pci_dev *dev);
936 int pci_back_from_sleep(struct pci_dev *dev);
937 bool pci_dev_run_wake(struct pci_dev *dev);
938 bool pci_check_pme_status(struct pci_dev *dev);
939 void pci_pme_wakeup_bus(struct pci_bus *bus);
941 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
944 return __pci_enable_wake(dev, state, false, enable);
947 #define PCI_EXP_IDO_REQUEST (1<<0)
948 #define PCI_EXP_IDO_COMPLETION (1<<1)
949 void pci_enable_ido(struct pci_dev *dev, unsigned long type);
950 void pci_disable_ido(struct pci_dev *dev, unsigned long type);
952 enum pci_obff_signal_type {
953 PCI_EXP_OBFF_SIGNAL_L0 = 0,
954 PCI_EXP_OBFF_SIGNAL_ALWAYS = 1,
956 int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type);
957 void pci_disable_obff(struct pci_dev *dev);
959 int pci_enable_ltr(struct pci_dev *dev);
960 void pci_disable_ltr(struct pci_dev *dev);
961 int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns);
963 /* For use by arch with custom probe code */
964 void set_pcie_port_type(struct pci_dev *pdev);
965 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
967 /* Functions for PCI Hotplug drivers to use */
968 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
969 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
970 unsigned int pci_rescan_bus(struct pci_bus *bus);
972 /* Vital product data routines */
973 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
974 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
975 int pci_vpd_truncate(struct pci_dev *dev, size_t size);
977 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
978 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
979 void pci_bus_assign_resources(const struct pci_bus *bus);
980 void pci_bus_size_bridges(struct pci_bus *bus);
981 int pci_claim_resource(struct pci_dev *, int);
982 void pci_assign_unassigned_resources(void);
983 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
984 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
985 void pdev_enable_device(struct pci_dev *);
986 int pci_enable_resources(struct pci_dev *, int mask);
987 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
988 int (*)(const struct pci_dev *, u8, u8));
989 #define HAVE_PCI_REQ_REGIONS 2
990 int __must_check pci_request_regions(struct pci_dev *, const char *);
991 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
992 void pci_release_regions(struct pci_dev *);
993 int __must_check pci_request_region(struct pci_dev *, int, const char *);
994 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
995 void pci_release_region(struct pci_dev *, int);
996 int pci_request_selected_regions(struct pci_dev *, int, const char *);
997 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
998 void pci_release_selected_regions(struct pci_dev *, int);
1000 /* drivers/pci/bus.c */
1001 void pci_add_resource(struct list_head *resources, struct resource *res);
1002 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1003 resource_size_t offset);
1004 void pci_free_resource_list(struct list_head *resources);
1005 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
1006 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1007 void pci_bus_remove_resources(struct pci_bus *bus);
1009 #define pci_bus_for_each_resource(bus, res, i) \
1011 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1014 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1015 struct resource *res, resource_size_t size,
1016 resource_size_t align, resource_size_t min,
1017 unsigned int type_mask,
1018 resource_size_t (*alignf)(void *,
1019 const struct resource *,
1023 void pci_enable_bridges(struct pci_bus *bus);
1025 /* Proper probing supporting hot-pluggable devices */
1026 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1027 const char *mod_name);
1030 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1032 #define pci_register_driver(driver) \
1033 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1035 void pci_unregister_driver(struct pci_driver *dev);
1038 * module_pci_driver() - Helper macro for registering a PCI driver
1039 * @__pci_driver: pci_driver struct
1041 * Helper macro for PCI drivers which do not do anything special in module
1042 * init/exit. This eliminates a lot of boilerplate. Each module may only
1043 * use this macro once, and calling it replaces module_init() and module_exit()
1045 #define module_pci_driver(__pci_driver) \
1046 module_driver(__pci_driver, pci_register_driver, \
1047 pci_unregister_driver)
1049 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1050 int pci_add_dynid(struct pci_driver *drv,
1051 unsigned int vendor, unsigned int device,
1052 unsigned int subvendor, unsigned int subdevice,
1053 unsigned int class, unsigned int class_mask,
1054 unsigned long driver_data);
1055 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1056 struct pci_dev *dev);
1057 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1060 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1062 int pci_cfg_space_size_ext(struct pci_dev *dev);
1063 int pci_cfg_space_size(struct pci_dev *dev);
1064 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1065 void pci_setup_bridge(struct pci_bus *bus);
1066 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1067 unsigned long type);
1069 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1070 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1072 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1073 unsigned int command_bits, u32 flags);
1074 /* kmem_cache style wrapper around pci_alloc_consistent() */
1076 #include <linux/pci-dma.h>
1077 #include <linux/dmapool.h>
1079 #define pci_pool dma_pool
1080 #define pci_pool_create(name, pdev, size, align, allocation) \
1081 dma_pool_create(name, &pdev->dev, size, align, allocation)
1082 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1083 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1084 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1086 enum pci_dma_burst_strategy {
1087 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
1088 strategy_parameter is N/A */
1089 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
1091 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
1092 strategy_parameter byte boundaries */
1096 u32 vector; /* kernel uses to write allocated vector */
1097 u16 entry; /* driver uses to specify entry, OS writes */
1101 #ifndef CONFIG_PCI_MSI
1102 static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
1108 pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec)
1113 static inline void pci_msi_shutdown(struct pci_dev *dev)
1115 static inline void pci_disable_msi(struct pci_dev *dev)
1118 static inline int pci_msix_table_size(struct pci_dev *dev)
1122 static inline int pci_enable_msix(struct pci_dev *dev,
1123 struct msix_entry *entries, int nvec)
1128 static inline void pci_msix_shutdown(struct pci_dev *dev)
1130 static inline void pci_disable_msix(struct pci_dev *dev)
1133 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
1136 static inline void pci_restore_msi_state(struct pci_dev *dev)
1138 static inline int pci_msi_enabled(void)
1143 extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
1144 extern int pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec);
1145 extern void pci_msi_shutdown(struct pci_dev *dev);
1146 extern void pci_disable_msi(struct pci_dev *dev);
1147 extern int pci_msix_table_size(struct pci_dev *dev);
1148 extern int pci_enable_msix(struct pci_dev *dev,
1149 struct msix_entry *entries, int nvec);
1150 extern void pci_msix_shutdown(struct pci_dev *dev);
1151 extern void pci_disable_msix(struct pci_dev *dev);
1152 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
1153 extern void pci_restore_msi_state(struct pci_dev *dev);
1154 extern int pci_msi_enabled(void);
1157 #ifdef CONFIG_PCIEPORTBUS
1158 extern bool pcie_ports_disabled;
1159 extern bool pcie_ports_auto;
1161 #define pcie_ports_disabled true
1162 #define pcie_ports_auto false
1165 #ifndef CONFIG_PCIEASPM
1166 static inline int pcie_aspm_enabled(void) { return 0; }
1167 static inline bool pcie_aspm_support_enabled(void) { return false; }
1169 extern int pcie_aspm_enabled(void);
1170 extern bool pcie_aspm_support_enabled(void);
1173 #ifdef CONFIG_PCIEAER
1174 void pci_no_aer(void);
1175 bool pci_aer_available(void);
1177 static inline void pci_no_aer(void) { }
1178 static inline bool pci_aer_available(void) { return false; }
1181 #ifndef CONFIG_PCIE_ECRC
1182 static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
1186 static inline void pcie_ecrc_get_policy(char *str) {};
1188 extern void pcie_set_ecrc_checking(struct pci_dev *dev);
1189 extern void pcie_ecrc_get_policy(char *str);
1192 #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
1194 #ifdef CONFIG_HT_IRQ
1195 /* The functions a driver should call */
1196 int ht_create_irq(struct pci_dev *dev, int idx);
1197 void ht_destroy_irq(unsigned int irq);
1198 #endif /* CONFIG_HT_IRQ */
1200 extern void pci_cfg_access_lock(struct pci_dev *dev);
1201 extern bool pci_cfg_access_trylock(struct pci_dev *dev);
1202 extern void pci_cfg_access_unlock(struct pci_dev *dev);
1205 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1206 * a PCI domain is defined to be a set of PCI busses which share
1207 * configuration space.
1209 #ifdef CONFIG_PCI_DOMAINS
1210 extern int pci_domains_supported;
1212 enum { pci_domains_supported = 0 };
1213 static inline int pci_domain_nr(struct pci_bus *bus)
1218 static inline int pci_proc_domain(struct pci_bus *bus)
1222 #endif /* CONFIG_PCI_DOMAINS */
1224 /* some architectures require additional setup to direct VGA traffic */
1225 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1226 unsigned int command_bits, u32 flags);
1227 extern void pci_register_set_vga_state(arch_set_vga_state_t func);
1229 #else /* CONFIG_PCI is not enabled */
1232 * If the system does not have PCI, clearly these return errors. Define
1233 * these as simple inline functions to avoid hair in drivers.
1236 #define _PCI_NOP(o, s, t) \
1237 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1239 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1241 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1242 _PCI_NOP(o, word, u16 x) \
1243 _PCI_NOP(o, dword, u32 x)
1244 _PCI_NOP_ALL(read, *)
1245 _PCI_NOP_ALL(write,)
1247 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1248 unsigned int device,
1249 struct pci_dev *from)
1254 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1255 unsigned int device,
1256 unsigned int ss_vendor,
1257 unsigned int ss_device,
1258 struct pci_dev *from)
1263 static inline struct pci_dev *pci_get_class(unsigned int class,
1264 struct pci_dev *from)
1269 #define pci_dev_present(ids) (0)
1270 #define no_pci_devices() (1)
1271 #define pci_dev_put(dev) do { } while (0)
1273 static inline void pci_set_master(struct pci_dev *dev)
1276 static inline int pci_enable_device(struct pci_dev *dev)
1281 static inline void pci_disable_device(struct pci_dev *dev)
1284 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1289 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1294 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1300 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1306 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1311 static inline int __pci_register_driver(struct pci_driver *drv,
1312 struct module *owner)
1317 static inline int pci_register_driver(struct pci_driver *drv)
1322 static inline void pci_unregister_driver(struct pci_driver *drv)
1325 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1330 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1336 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1341 /* Power management related routines */
1342 static inline int pci_save_state(struct pci_dev *dev)
1347 static inline void pci_restore_state(struct pci_dev *dev)
1350 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1355 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1360 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1366 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1372 static inline void pci_enable_ido(struct pci_dev *dev, unsigned long type)
1376 static inline void pci_disable_ido(struct pci_dev *dev, unsigned long type)
1380 static inline int pci_enable_obff(struct pci_dev *dev, unsigned long type)
1385 static inline void pci_disable_obff(struct pci_dev *dev)
1389 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1394 static inline void pci_release_regions(struct pci_dev *dev)
1397 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1399 static inline void pci_block_cfg_access(struct pci_dev *dev)
1402 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1405 static inline void pci_unblock_cfg_access(struct pci_dev *dev)
1408 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1411 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1415 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1419 static inline int pci_domain_nr(struct pci_bus *bus)
1422 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev)
1425 #define dev_is_pci(d) (false)
1426 #define dev_is_pf(d) (false)
1427 #define dev_num_vf(d) (0)
1428 #endif /* CONFIG_PCI */
1430 /* Include architecture-dependent settings and functions */
1432 #include <asm/pci.h>
1434 #ifndef PCIBIOS_MAX_MEM_32
1435 #define PCIBIOS_MAX_MEM_32 (-1)
1438 /* these helpers provide future and backwards compatibility
1439 * for accessing popular PCI BAR info */
1440 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1441 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1442 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1443 #define pci_resource_len(dev,bar) \
1444 ((pci_resource_start((dev), (bar)) == 0 && \
1445 pci_resource_end((dev), (bar)) == \
1446 pci_resource_start((dev), (bar))) ? 0 : \
1448 (pci_resource_end((dev), (bar)) - \
1449 pci_resource_start((dev), (bar)) + 1))
1451 /* Similar to the helpers above, these manipulate per-pci_dev
1452 * driver-specific data. They are really just a wrapper around
1453 * the generic device structure functions of these calls.
1455 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1457 return dev_get_drvdata(&pdev->dev);
1460 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1462 dev_set_drvdata(&pdev->dev, data);
1465 /* If you want to know what to call your pci_dev, ask this function.
1466 * Again, it's a wrapper around the generic device.
1468 static inline const char *pci_name(const struct pci_dev *pdev)
1470 return dev_name(&pdev->dev);
1474 /* Some archs don't want to expose struct resource to userland as-is
1475 * in sysfs and /proc
1477 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1478 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1479 const struct resource *rsrc, resource_size_t *start,
1480 resource_size_t *end)
1482 *start = rsrc->start;
1485 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1489 * The world is not perfect and supplies us with broken PCI devices.
1490 * For at least a part of these bugs we need a work-around, so both
1491 * generic (drivers/pci/quirks.c) and per-architecture code can define
1492 * fixup hooks to be called for particular buggy devices.
1496 u16 vendor; /* You can use PCI_ANY_ID here of course */
1497 u16 device; /* You can use PCI_ANY_ID here of course */
1498 u32 class; /* You can use PCI_ANY_ID here too */
1499 unsigned int class_shift; /* should be 0, 8, 16 */
1500 void (*hook)(struct pci_dev *dev);
1503 enum pci_fixup_pass {
1504 pci_fixup_early, /* Before probing BARs */
1505 pci_fixup_header, /* After reading configuration header */
1506 pci_fixup_final, /* Final phase of device fixups */
1507 pci_fixup_enable, /* pci_enable_device() time */
1508 pci_fixup_resume, /* pci_device_resume() */
1509 pci_fixup_suspend, /* pci_device_suspend */
1510 pci_fixup_resume_early, /* pci_device_resume_early() */
1513 /* Anonymous variables would be nice... */
1514 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1515 class_shift, hook) \
1516 static const struct pci_fixup __pci_fixup_##name __used \
1517 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1518 = { vendor, device, class, class_shift, hook };
1520 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1521 class_shift, hook) \
1522 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1523 vendor##device##hook, vendor, device, class, class_shift, hook)
1524 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1525 class_shift, hook) \
1526 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1527 vendor##device##hook, vendor, device, class, class_shift, hook)
1528 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1529 class_shift, hook) \
1530 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1531 vendor##device##hook, vendor, device, class, class_shift, hook)
1532 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1533 class_shift, hook) \
1534 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1535 vendor##device##hook, vendor, device, class, class_shift, hook)
1536 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1537 class_shift, hook) \
1538 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1539 resume##vendor##device##hook, vendor, device, class, \
1541 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1542 class_shift, hook) \
1543 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1544 resume_early##vendor##device##hook, vendor, device, \
1545 class, class_shift, hook)
1546 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1547 class_shift, hook) \
1548 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1549 suspend##vendor##device##hook, vendor, device, class, \
1552 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1553 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1554 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1555 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1556 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1557 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1558 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1559 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1560 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1561 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1562 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1563 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1564 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1565 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1566 resume##vendor##device##hook, vendor, device, \
1567 PCI_ANY_ID, 0, hook)
1568 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1569 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1570 resume_early##vendor##device##hook, vendor, device, \
1571 PCI_ANY_ID, 0, hook)
1572 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1573 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1574 suspend##vendor##device##hook, vendor, device, \
1575 PCI_ANY_ID, 0, hook)
1577 #ifdef CONFIG_PCI_QUIRKS
1578 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1579 struct pci_dev *pci_get_dma_source(struct pci_dev *dev);
1580 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1582 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1583 struct pci_dev *dev) {}
1584 static inline struct pci_dev *pci_get_dma_source(struct pci_dev *dev)
1586 return pci_dev_get(dev);
1588 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1595 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1596 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1597 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1598 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1599 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1601 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1603 extern int pci_pci_problems;
1604 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1605 #define PCIPCI_TRITON 2
1606 #define PCIPCI_NATOMA 4
1607 #define PCIPCI_VIAETBF 8
1608 #define PCIPCI_VSFX 16
1609 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1610 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1612 extern unsigned long pci_cardbus_io_size;
1613 extern unsigned long pci_cardbus_mem_size;
1614 extern u8 pci_dfl_cache_line_size;
1615 extern u8 pci_cache_line_size;
1617 extern unsigned long pci_hotplug_io_size;
1618 extern unsigned long pci_hotplug_mem_size;
1620 /* Architecture specific versions may override these (weak) */
1621 int pcibios_add_platform_entries(struct pci_dev *dev);
1622 void pcibios_disable_device(struct pci_dev *dev);
1623 void pcibios_set_master(struct pci_dev *dev);
1624 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1625 enum pcie_reset_state state);
1626 int pcibios_add_device(struct pci_dev *dev);
1628 #ifdef CONFIG_PCI_MMCONFIG
1629 extern void __init pci_mmcfg_early_init(void);
1630 extern void __init pci_mmcfg_late_init(void);
1632 static inline void pci_mmcfg_early_init(void) { }
1633 static inline void pci_mmcfg_late_init(void) { }
1636 int pci_ext_cfg_avail(void);
1638 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1640 #ifdef CONFIG_PCI_IOV
1641 extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1642 extern void pci_disable_sriov(struct pci_dev *dev);
1643 extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
1644 extern int pci_num_vf(struct pci_dev *dev);
1645 extern int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1646 extern int pci_sriov_get_totalvfs(struct pci_dev *dev);
1648 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1652 static inline void pci_disable_sriov(struct pci_dev *dev)
1655 static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1659 static inline int pci_num_vf(struct pci_dev *dev)
1663 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1667 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1673 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1674 extern void pci_hp_create_module_link(struct pci_slot *pci_slot);
1675 extern void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1679 * pci_pcie_cap - get the saved PCIe capability offset
1682 * PCIe capability offset is calculated at PCI device initialization
1683 * time and saved in the data structure. This function returns saved
1684 * PCIe capability offset. Using this instead of pci_find_capability()
1685 * reduces unnecessary search in the PCI configuration space. If you
1686 * need to calculate PCIe capability offset from raw device for some
1687 * reasons, please use pci_find_capability() instead.
1689 static inline int pci_pcie_cap(struct pci_dev *dev)
1691 return dev->pcie_cap;
1695 * pci_is_pcie - check if the PCI device is PCI Express capable
1698 * Retrun true if the PCI device is PCI Express capable, false otherwise.
1700 static inline bool pci_is_pcie(struct pci_dev *dev)
1702 return !!pci_pcie_cap(dev);
1706 * pcie_caps_reg - get the PCIe Capabilities Register
1709 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
1711 return dev->pcie_flags_reg;
1715 * pci_pcie_type - get the PCIe device/port type
1718 static inline int pci_pcie_type(const struct pci_dev *dev)
1720 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
1723 void pci_request_acs(void);
1724 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1725 bool pci_acs_path_enabled(struct pci_dev *start,
1726 struct pci_dev *end, u16 acs_flags);
1728 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1729 #define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT)
1731 /* Large Resource Data Type Tag Item Names */
1732 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1733 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1734 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1736 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1737 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1738 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1740 /* Small Resource Data Type Tag Item Names */
1741 #define PCI_VPD_STIN_END 0x78 /* End */
1743 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1745 #define PCI_VPD_SRDT_TIN_MASK 0x78
1746 #define PCI_VPD_SRDT_LEN_MASK 0x07
1748 #define PCI_VPD_LRDT_TAG_SIZE 3
1749 #define PCI_VPD_SRDT_TAG_SIZE 1
1751 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1753 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1754 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1755 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1756 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
1759 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1760 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1762 * Returns the extracted Large Resource Data Type length.
1764 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1766 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1770 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1771 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1773 * Returns the extracted Small Resource Data Type length.
1775 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1777 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1781 * pci_vpd_info_field_size - Extracts the information field length
1782 * @lrdt: Pointer to the beginning of an information field header
1784 * Returns the extracted information field length.
1786 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1788 return info_field[2];
1792 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1793 * @buf: Pointer to buffered vpd data
1794 * @off: The offset into the buffer at which to begin the search
1795 * @len: The length of the vpd buffer
1796 * @rdt: The Resource Data Type to search for
1798 * Returns the index where the Resource Data Type was found or
1799 * -ENOENT otherwise.
1801 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1804 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1805 * @buf: Pointer to buffered vpd data
1806 * @off: The offset into the buffer at which to begin the search
1807 * @len: The length of the buffer area, relative to off, in which to search
1808 * @kw: The keyword to search for
1810 * Returns the index where the information field keyword was found or
1811 * -ENOENT otherwise.
1813 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1814 unsigned int len, const char *kw);
1816 /* PCI <-> OF binding helpers */
1819 extern void pci_set_of_node(struct pci_dev *dev);
1820 extern void pci_release_of_node(struct pci_dev *dev);
1821 extern void pci_set_bus_of_node(struct pci_bus *bus);
1822 extern void pci_release_bus_of_node(struct pci_bus *bus);
1824 /* Arch may override this (weak) */
1825 extern struct device_node * __weak pcibios_get_phb_of_node(struct pci_bus *bus);
1827 static inline struct device_node *
1828 pci_device_to_OF_node(const struct pci_dev *pdev)
1830 return pdev ? pdev->dev.of_node : NULL;
1833 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1835 return bus ? bus->dev.of_node : NULL;
1838 #else /* CONFIG_OF */
1839 static inline void pci_set_of_node(struct pci_dev *dev) { }
1840 static inline void pci_release_of_node(struct pci_dev *dev) { }
1841 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1842 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1843 #endif /* CONFIG_OF */
1846 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
1848 return pdev->dev.archdata.edev;
1853 * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device
1854 * @pdev: the PCI device
1856 * if the device is PCIE, return NULL
1857 * if the device isn't connected to a PCIe bridge (that is its parent is a
1858 * legacy PCI bridge and the bridge is directly connected to bus 0), return its
1861 struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);
1863 #endif /* LINUX_PCI_H */