4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
20 #include <linux/mod_devicetable.h>
22 #include <linux/types.h>
23 #include <linux/init.h>
24 #include <linux/ioport.h>
25 #include <linux/list.h>
26 #include <linux/compiler.h>
27 #include <linux/errno.h>
28 #include <linux/kobject.h>
29 #include <linux/atomic.h>
30 #include <linux/device.h>
32 #include <uapi/linux/pci.h>
34 #include <linux/pci_ids.h>
37 * The PCI interface treats multi-function devices as independent
38 * devices. The slot/function address of each device is encoded
39 * in a single byte as follows:
44 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
45 * In the interest of not exposing interfaces to user-space unnecessarily,
46 * the following kernel-only defines are being added here.
48 #define PCI_DEVID(bus, devfn) ((((u16)bus) << 8) | devfn)
49 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
50 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
52 /* pci_slot represents a physical slot */
54 struct pci_bus *bus; /* The bus this slot is on */
55 struct list_head list; /* node in list of slots on this bus */
56 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
57 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
61 static inline const char *pci_slot_name(const struct pci_slot *slot)
63 return kobject_name(&slot->kobj);
66 /* File state for mmap()s on /proc/bus/pci/X/Y */
72 /* This defines the direction arg to the DMA mapping routines. */
73 #define PCI_DMA_BIDIRECTIONAL 0
74 #define PCI_DMA_TODEVICE 1
75 #define PCI_DMA_FROMDEVICE 2
76 #define PCI_DMA_NONE 3
79 * For PCI devices, the region numbers are assigned this way:
82 /* #0-5: standard PCI resources */
84 PCI_STD_RESOURCE_END = 5,
86 /* #6: expansion ROM resource */
89 /* device specific resources */
92 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
95 /* resources assigned to buses behind the bridge */
96 #define PCI_BRIDGE_RESOURCE_NUM 4
99 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
100 PCI_BRIDGE_RESOURCE_NUM - 1,
102 /* total resources associated with a PCI device */
105 /* preserve this for compatibility */
106 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
109 typedef int __bitwise pci_power_t;
111 #define PCI_D0 ((pci_power_t __force) 0)
112 #define PCI_D1 ((pci_power_t __force) 1)
113 #define PCI_D2 ((pci_power_t __force) 2)
114 #define PCI_D3hot ((pci_power_t __force) 3)
115 #define PCI_D3cold ((pci_power_t __force) 4)
116 #define PCI_UNKNOWN ((pci_power_t __force) 5)
117 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
119 /* Remember to update this when the list above changes! */
120 extern const char *pci_power_names[];
122 static inline const char *pci_power_name(pci_power_t state)
124 return pci_power_names[1 + (int) state];
127 #define PCI_PM_D2_DELAY 200
128 #define PCI_PM_D3_WAIT 10
129 #define PCI_PM_D3COLD_WAIT 100
130 #define PCI_PM_BUS_WAIT 50
132 /** The pci_channel state describes connectivity between the CPU and
133 * the pci device. If some PCI bus between here and the pci device
134 * has crashed or locked up, this info is reflected here.
136 typedef unsigned int __bitwise pci_channel_state_t;
138 enum pci_channel_state {
139 /* I/O channel is in normal state */
140 pci_channel_io_normal = (__force pci_channel_state_t) 1,
142 /* I/O to channel is blocked */
143 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
145 /* PCI card is dead */
146 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
149 typedef unsigned int __bitwise pcie_reset_state_t;
151 enum pcie_reset_state {
152 /* Reset is NOT asserted (Use to deassert reset) */
153 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
155 /* Use #PERST to reset PCIe device */
156 pcie_warm_reset = (__force pcie_reset_state_t) 2,
158 /* Use PCIe Hot Reset to reset device */
159 pcie_hot_reset = (__force pcie_reset_state_t) 3
162 typedef unsigned short __bitwise pci_dev_flags_t;
164 /* INTX_DISABLE in PCI_COMMAND register disables MSI
167 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
168 /* Device configuration is irrevocably lost if disabled into D3 */
169 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
170 /* Provide indication device is assigned by a Virtual Machine Manager */
171 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
172 /* Flag for quirk use to store if quirk-specific ACS is enabled */
173 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
174 /* Flag to indicate the device uses dma_alias_devfn */
175 PCI_DEV_FLAGS_DMA_ALIAS_DEVFN = (__force pci_dev_flags_t) (1 << 4),
176 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
177 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
180 enum pci_irq_reroute_variant {
181 INTEL_IRQ_REROUTE_VARIANT = 1,
182 MAX_IRQ_REROUTE_VARIANTS = 3
185 typedef unsigned short __bitwise pci_bus_flags_t;
187 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
188 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
191 /* These values come from the PCI Express Spec */
192 enum pcie_link_width {
193 PCIE_LNK_WIDTH_RESRV = 0x00,
201 PCIE_LNK_WIDTH_UNKNOWN = 0xFF,
204 /* Based on the PCI Hotplug Spec, but some values are made up by us */
206 PCI_SPEED_33MHz = 0x00,
207 PCI_SPEED_66MHz = 0x01,
208 PCI_SPEED_66MHz_PCIX = 0x02,
209 PCI_SPEED_100MHz_PCIX = 0x03,
210 PCI_SPEED_133MHz_PCIX = 0x04,
211 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
212 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
213 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
214 PCI_SPEED_66MHz_PCIX_266 = 0x09,
215 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
216 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
222 PCI_SPEED_66MHz_PCIX_533 = 0x11,
223 PCI_SPEED_100MHz_PCIX_533 = 0x12,
224 PCI_SPEED_133MHz_PCIX_533 = 0x13,
225 PCIE_SPEED_2_5GT = 0x14,
226 PCIE_SPEED_5_0GT = 0x15,
227 PCIE_SPEED_8_0GT = 0x16,
228 PCI_SPEED_UNKNOWN = 0xff,
231 struct pci_cap_saved_data {
238 struct pci_cap_saved_state {
239 struct hlist_node next;
240 struct pci_cap_saved_data cap;
243 struct pcie_link_state;
249 * The pci_dev structure is used to describe PCI devices.
252 struct list_head bus_list; /* node in per-bus list */
253 struct pci_bus *bus; /* bus this device is on */
254 struct pci_bus *subordinate; /* bus this device bridges to */
256 void *sysdata; /* hook for sys-specific extension */
257 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
258 struct pci_slot *slot; /* Physical slot this device is in */
260 unsigned int devfn; /* encoded device & function index */
261 unsigned short vendor;
262 unsigned short device;
263 unsigned short subsystem_vendor;
264 unsigned short subsystem_device;
265 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
266 u8 revision; /* PCI revision, low byte of class word */
267 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
268 u8 pcie_cap; /* PCIe capability offset */
269 u8 msi_cap; /* MSI capability offset */
270 u8 msix_cap; /* MSI-X capability offset */
271 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
272 u8 rom_base_reg; /* which config register controls the ROM */
273 u8 pin; /* which interrupt pin this device uses */
274 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */
275 u8 dma_alias_devfn;/* devfn of DMA alias, if any */
277 struct pci_driver *driver; /* which driver has allocated this device */
278 u64 dma_mask; /* Mask of the bits of bus address this
279 device implements. Normally this is
280 0xffffffff. You only need to change
281 this if your device has broken DMA
282 or supports 64-bit transfers. */
284 struct device_dma_parameters dma_parms;
286 pci_power_t current_state; /* Current operating state. In ACPI-speak,
287 this is D0-D3, D0 being fully functional,
289 u8 pm_cap; /* PM capability offset */
290 unsigned int pme_support:5; /* Bitmask of states from which PME#
292 unsigned int pme_interrupt:1;
293 unsigned int pme_poll:1; /* Poll device's PME status bit */
294 unsigned int d1_support:1; /* Low power state D1 is supported */
295 unsigned int d2_support:1; /* Low power state D2 is supported */
296 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
297 unsigned int no_d3cold:1; /* D3cold is forbidden */
298 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
299 unsigned int mmio_always_on:1; /* disallow turning off io/mem
300 decoding during bar sizing */
301 unsigned int wakeup_prepared:1;
302 unsigned int runtime_d3cold:1; /* whether go through runtime
303 D3cold, not set for devices
304 powered on/off by the
305 corresponding bridge */
306 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
307 unsigned int d3_delay; /* D3->D0 transition time in ms */
308 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
310 #ifdef CONFIG_PCIEASPM
311 struct pcie_link_state *link_state; /* ASPM link state */
314 pci_channel_state_t error_state; /* current connectivity state */
315 struct device dev; /* Generic device interface */
317 int cfg_size; /* Size of configuration space */
320 * Instead of touching interrupt line and base address registers
321 * directly, use the values stored here. They might be different!
324 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
326 bool match_driver; /* Skip attaching driver */
327 /* These fields are used by common fixups */
328 unsigned int transparent:1; /* Subtractive decode PCI bridge */
329 unsigned int multifunction:1;/* Part of multi-function device */
330 /* keep track of device state */
331 unsigned int is_added:1;
332 unsigned int is_busmaster:1; /* device is busmaster */
333 unsigned int no_msi:1; /* device may not use msi */
334 unsigned int block_cfg_access:1; /* config space access is blocked */
335 unsigned int broken_parity_status:1; /* Device generates false positive parity */
336 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
337 unsigned int msi_enabled:1;
338 unsigned int msix_enabled:1;
339 unsigned int ari_enabled:1; /* ARI forwarding */
340 unsigned int is_managed:1;
341 unsigned int needs_freset:1; /* Dev requires fundamental reset */
342 unsigned int state_saved:1;
343 unsigned int is_physfn:1;
344 unsigned int is_virtfn:1;
345 unsigned int reset_fn:1;
346 unsigned int is_hotplug_bridge:1;
347 unsigned int __aer_firmware_first_valid:1;
348 unsigned int __aer_firmware_first:1;
349 unsigned int broken_intx_masking:1;
350 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
351 pci_dev_flags_t dev_flags;
352 atomic_t enable_cnt; /* pci_enable_device has been called */
354 u32 saved_config_space[16]; /* config space saved at suspend time */
355 struct hlist_head saved_cap_space;
356 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
357 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
358 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
359 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
360 #ifdef CONFIG_PCI_MSI
361 struct list_head msi_list;
362 const struct attribute_group **msi_irq_groups;
365 #ifdef CONFIG_PCI_ATS
367 struct pci_sriov *sriov; /* SR-IOV capability related */
368 struct pci_dev *physfn; /* the PF this VF is associated with */
370 struct pci_ats *ats; /* Address Translation Service */
372 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
373 size_t romlen; /* Length of ROM if it's not from the BAR */
374 char *driver_override; /* Driver name to force a match */
377 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
379 #ifdef CONFIG_PCI_IOV
386 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
388 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
389 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
391 static inline int pci_channel_offline(struct pci_dev *pdev)
393 return (pdev->error_state != pci_channel_io_normal);
396 struct pci_host_bridge_window {
397 struct list_head list;
398 struct resource *res; /* host bridge aperture (CPU address) */
399 resource_size_t offset; /* bus address + offset = CPU address */
402 struct pci_host_bridge {
404 struct pci_bus *bus; /* root bus */
405 struct list_head windows; /* pci_host_bridge_windows */
406 void (*release_fn)(struct pci_host_bridge *);
410 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
411 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
412 void (*release_fn)(struct pci_host_bridge *),
415 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
418 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
419 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
420 * buses below host bridges or subtractive decode bridges) go in the list.
421 * Use pci_bus_for_each_resource() to iterate through all the resources.
425 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
426 * and there's no way to program the bridge with the details of the window.
427 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
428 * decode bit set, because they are explicit and can be programmed with _SRS.
430 #define PCI_SUBTRACTIVE_DECODE 0x1
432 struct pci_bus_resource {
433 struct list_head list;
434 struct resource *res;
438 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
441 struct list_head node; /* node in list of buses */
442 struct pci_bus *parent; /* parent bus this bridge is on */
443 struct list_head children; /* list of child buses */
444 struct list_head devices; /* list of devices on this bus */
445 struct pci_dev *self; /* bridge device as seen by parent */
446 struct list_head slots; /* list of slots on this bus */
447 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
448 struct list_head resources; /* address space routed to this bus */
449 struct resource busn_res; /* bus numbers routed to this bus */
451 struct pci_ops *ops; /* configuration access functions */
452 struct msi_chip *msi; /* MSI controller */
453 void *sysdata; /* hook for sys-specific extension */
454 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
456 unsigned char number; /* bus number */
457 unsigned char primary; /* number of primary bridge */
458 unsigned char max_bus_speed; /* enum pci_bus_speed */
459 unsigned char cur_bus_speed; /* enum pci_bus_speed */
463 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
464 pci_bus_flags_t bus_flags; /* inherited by child buses */
465 struct device *bridge;
467 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
468 struct bin_attribute *legacy_mem; /* legacy mem */
469 unsigned int is_added:1;
472 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
475 * Returns true if the PCI bus is root (behind host-PCI bridge),
478 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
479 * This is incorrect because "virtual" buses added for SR-IOV (via
480 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
482 static inline bool pci_is_root_bus(struct pci_bus *pbus)
484 return !(pbus->parent);
488 * pci_is_bridge - check if the PCI device is a bridge
491 * Return true if the PCI device is bridge whether it has subordinate
494 static inline bool pci_is_bridge(struct pci_dev *dev)
496 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
497 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
500 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
502 dev = pci_physfn(dev);
503 if (pci_is_root_bus(dev->bus))
506 return dev->bus->self;
509 #ifdef CONFIG_PCI_MSI
510 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
512 return pci_dev->msi_enabled || pci_dev->msix_enabled;
515 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
519 * Error values that may be returned by PCI functions.
521 #define PCIBIOS_SUCCESSFUL 0x00
522 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
523 #define PCIBIOS_BAD_VENDOR_ID 0x83
524 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
525 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
526 #define PCIBIOS_SET_FAILED 0x88
527 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
530 * Translate above to generic errno for passing back through non-PCI code.
532 static inline int pcibios_err_to_errno(int err)
534 if (err <= PCIBIOS_SUCCESSFUL)
535 return err; /* Assume already errno */
538 case PCIBIOS_FUNC_NOT_SUPPORTED:
540 case PCIBIOS_BAD_VENDOR_ID:
542 case PCIBIOS_DEVICE_NOT_FOUND:
544 case PCIBIOS_BAD_REGISTER_NUMBER:
546 case PCIBIOS_SET_FAILED:
548 case PCIBIOS_BUFFER_TOO_SMALL:
555 /* Low-level architecture-dependent routines */
558 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
559 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
563 * ACPI needs to be able to access PCI config space before we've done a
564 * PCI bus scan and created pci_bus structures.
566 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
567 int reg, int len, u32 *val);
568 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
569 int reg, int len, u32 val);
571 struct pci_bus_region {
577 spinlock_t lock; /* protects list, index */
578 struct list_head list; /* for IDs added at runtime */
583 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
584 * a set of callbacks in struct pci_error_handlers, that device driver
585 * will be notified of PCI bus errors, and will be driven to recovery
586 * when an error occurs.
589 typedef unsigned int __bitwise pci_ers_result_t;
591 enum pci_ers_result {
592 /* no result/none/not supported in device driver */
593 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
595 /* Device driver can recover without slot reset */
596 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
598 /* Device driver wants slot to be reset. */
599 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
601 /* Device has completely failed, is unrecoverable */
602 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
604 /* Device driver is fully recovered and operational */
605 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
607 /* No AER capabilities registered for the driver */
608 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
611 /* PCI bus error event callbacks */
612 struct pci_error_handlers {
613 /* PCI bus error detected on this device */
614 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
615 enum pci_channel_state error);
617 /* MMIO has been re-enabled, but not DMA */
618 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
620 /* PCI Express link has been reset */
621 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
623 /* PCI slot has been reset */
624 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
626 /* PCI function reset prepare or completed */
627 void (*reset_notify)(struct pci_dev *dev, bool prepare);
629 /* Device driver may resume normal operations */
630 void (*resume)(struct pci_dev *dev);
636 struct list_head node;
638 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
639 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
640 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
641 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
642 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
643 int (*resume_early) (struct pci_dev *dev);
644 int (*resume) (struct pci_dev *dev); /* Device woken up */
645 void (*shutdown) (struct pci_dev *dev);
646 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
647 const struct pci_error_handlers *err_handler;
648 struct device_driver driver;
649 struct pci_dynids dynids;
652 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
655 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
656 * @_table: device table name
658 * This macro is deprecated and should not be used in new code.
660 #define DEFINE_PCI_DEVICE_TABLE(_table) \
661 const struct pci_device_id _table[]
664 * PCI_DEVICE - macro used to describe a specific pci device
665 * @vend: the 16 bit PCI Vendor ID
666 * @dev: the 16 bit PCI Device ID
668 * This macro is used to create a struct pci_device_id that matches a
669 * specific device. The subvendor and subdevice fields will be set to
672 #define PCI_DEVICE(vend,dev) \
673 .vendor = (vend), .device = (dev), \
674 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
677 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
678 * @vend: the 16 bit PCI Vendor ID
679 * @dev: the 16 bit PCI Device ID
680 * @subvend: the 16 bit PCI Subvendor ID
681 * @subdev: the 16 bit PCI Subdevice ID
683 * This macro is used to create a struct pci_device_id that matches a
684 * specific device with subsystem information.
686 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
687 .vendor = (vend), .device = (dev), \
688 .subvendor = (subvend), .subdevice = (subdev)
691 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
692 * @dev_class: the class, subclass, prog-if triple for this device
693 * @dev_class_mask: the class mask for this device
695 * This macro is used to create a struct pci_device_id that matches a
696 * specific PCI class. The vendor, device, subvendor, and subdevice
697 * fields will be set to PCI_ANY_ID.
699 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
700 .class = (dev_class), .class_mask = (dev_class_mask), \
701 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
702 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
705 * PCI_VDEVICE - macro used to describe a specific pci device in short form
706 * @vend: the vendor name
707 * @dev: the 16 bit PCI Device ID
709 * This macro is used to create a struct pci_device_id that matches a
710 * specific PCI device. The subvendor, and subdevice fields will be set
711 * to PCI_ANY_ID. The macro allows the next field to follow as the device
715 #define PCI_VDEVICE(vend, dev) \
716 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
717 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
719 /* these external functions are only available when PCI support is enabled */
722 void pcie_bus_configure_settings(struct pci_bus *bus);
724 enum pcie_bus_config_types {
727 PCIE_BUS_PERFORMANCE,
731 extern enum pcie_bus_config_types pcie_bus_config;
733 extern struct bus_type pci_bus_type;
735 /* Do NOT directly access these two variables, unless you are arch-specific PCI
736 * code, or PCI core code. */
737 extern struct list_head pci_root_buses; /* list of all known PCI buses */
738 /* Some device drivers need know if PCI is initiated */
739 int no_pci_devices(void);
741 void pcibios_resource_survey_bus(struct pci_bus *bus);
742 void pcibios_add_bus(struct pci_bus *bus);
743 void pcibios_remove_bus(struct pci_bus *bus);
744 void pcibios_fixup_bus(struct pci_bus *);
745 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
746 /* Architecture-specific versions may override this (weak) */
747 char *pcibios_setup(char *str);
749 /* Used only when drivers/pci/setup.c is used */
750 resource_size_t pcibios_align_resource(void *, const struct resource *,
753 void pcibios_update_irq(struct pci_dev *, int irq);
755 /* Weak but can be overriden by arch */
756 void pci_fixup_cardbus(struct pci_bus *);
758 /* Generic PCI functions used internally */
760 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
761 struct resource *res);
762 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
763 struct pci_bus_region *region);
764 void pcibios_scan_specific_bus(int busn);
765 struct pci_bus *pci_find_bus(int domain, int busnr);
766 void pci_bus_add_devices(const struct pci_bus *bus);
767 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
768 struct pci_ops *ops, void *sysdata);
769 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
770 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
771 struct pci_ops *ops, void *sysdata,
772 struct list_head *resources);
773 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
774 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
775 void pci_bus_release_busn_res(struct pci_bus *b);
776 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
777 struct pci_ops *ops, void *sysdata,
778 struct list_head *resources);
779 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
781 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
782 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
784 struct hotplug_slot *hotplug);
785 void pci_destroy_slot(struct pci_slot *slot);
786 int pci_scan_slot(struct pci_bus *bus, int devfn);
787 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
788 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
789 unsigned int pci_scan_child_bus(struct pci_bus *bus);
790 void pci_bus_add_device(struct pci_dev *dev);
791 void pci_read_bridge_bases(struct pci_bus *child);
792 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
793 struct resource *res);
794 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
795 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
796 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
797 struct pci_dev *pci_dev_get(struct pci_dev *dev);
798 void pci_dev_put(struct pci_dev *dev);
799 void pci_remove_bus(struct pci_bus *b);
800 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
801 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
802 void pci_stop_root_bus(struct pci_bus *bus);
803 void pci_remove_root_bus(struct pci_bus *bus);
804 void pci_setup_cardbus(struct pci_bus *bus);
805 void pci_sort_breadthfirst(void);
806 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
807 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
808 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
810 /* Generic PCI functions exported to card drivers */
812 enum pci_lost_interrupt_reason {
813 PCI_LOST_IRQ_NO_INFORMATION = 0,
814 PCI_LOST_IRQ_DISABLE_MSI,
815 PCI_LOST_IRQ_DISABLE_MSIX,
816 PCI_LOST_IRQ_DISABLE_ACPI,
818 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
819 int pci_find_capability(struct pci_dev *dev, int cap);
820 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
821 int pci_find_ext_capability(struct pci_dev *dev, int cap);
822 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
823 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
824 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
825 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
827 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
828 struct pci_dev *from);
829 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
830 unsigned int ss_vendor, unsigned int ss_device,
831 struct pci_dev *from);
832 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
833 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
835 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
838 return pci_get_domain_bus_and_slot(0, bus, devfn);
840 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
841 int pci_dev_present(const struct pci_device_id *ids);
843 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
845 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
846 int where, u16 *val);
847 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
848 int where, u32 *val);
849 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
851 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
853 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
855 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
857 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
859 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
861 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
863 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
865 static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
868 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
870 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
872 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
874 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
876 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
878 static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
881 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
884 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
885 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
886 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
887 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
888 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
890 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
893 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
896 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
899 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
902 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
905 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
908 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
911 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
914 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
917 /* user-space driven config access */
918 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
919 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
920 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
921 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
922 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
923 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
925 int __must_check pci_enable_device(struct pci_dev *dev);
926 int __must_check pci_enable_device_io(struct pci_dev *dev);
927 int __must_check pci_enable_device_mem(struct pci_dev *dev);
928 int __must_check pci_reenable_device(struct pci_dev *);
929 int __must_check pcim_enable_device(struct pci_dev *pdev);
930 void pcim_pin_device(struct pci_dev *pdev);
932 static inline int pci_is_enabled(struct pci_dev *pdev)
934 return (atomic_read(&pdev->enable_cnt) > 0);
937 static inline int pci_is_managed(struct pci_dev *pdev)
939 return pdev->is_managed;
942 void pci_disable_device(struct pci_dev *dev);
944 extern unsigned int pcibios_max_latency;
945 void pci_set_master(struct pci_dev *dev);
946 void pci_clear_master(struct pci_dev *dev);
948 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
949 int pci_set_cacheline_size(struct pci_dev *dev);
950 #define HAVE_PCI_SET_MWI
951 int __must_check pci_set_mwi(struct pci_dev *dev);
952 int pci_try_set_mwi(struct pci_dev *dev);
953 void pci_clear_mwi(struct pci_dev *dev);
954 void pci_intx(struct pci_dev *dev, int enable);
955 bool pci_intx_mask_supported(struct pci_dev *dev);
956 bool pci_check_and_mask_intx(struct pci_dev *dev);
957 bool pci_check_and_unmask_intx(struct pci_dev *dev);
958 void pci_msi_off(struct pci_dev *dev);
959 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
960 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
961 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
962 int pci_wait_for_pending_transaction(struct pci_dev *dev);
963 int pcix_get_max_mmrbc(struct pci_dev *dev);
964 int pcix_get_mmrbc(struct pci_dev *dev);
965 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
966 int pcie_get_readrq(struct pci_dev *dev);
967 int pcie_set_readrq(struct pci_dev *dev, int rq);
968 int pcie_get_mps(struct pci_dev *dev);
969 int pcie_set_mps(struct pci_dev *dev, int mps);
970 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
971 enum pcie_link_width *width);
972 int __pci_reset_function(struct pci_dev *dev);
973 int __pci_reset_function_locked(struct pci_dev *dev);
974 int pci_reset_function(struct pci_dev *dev);
975 int pci_try_reset_function(struct pci_dev *dev);
976 int pci_probe_reset_slot(struct pci_slot *slot);
977 int pci_reset_slot(struct pci_slot *slot);
978 int pci_try_reset_slot(struct pci_slot *slot);
979 int pci_probe_reset_bus(struct pci_bus *bus);
980 int pci_reset_bus(struct pci_bus *bus);
981 int pci_try_reset_bus(struct pci_bus *bus);
982 void pci_reset_secondary_bus(struct pci_dev *dev);
983 void pcibios_reset_secondary_bus(struct pci_dev *dev);
984 void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
985 void pci_update_resource(struct pci_dev *dev, int resno);
986 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
987 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
988 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
989 bool pci_device_is_present(struct pci_dev *pdev);
991 /* ROM control related routines */
992 int pci_enable_rom(struct pci_dev *pdev);
993 void pci_disable_rom(struct pci_dev *pdev);
994 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
995 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
996 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
997 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
999 /* Power management related routines */
1000 int pci_save_state(struct pci_dev *dev);
1001 void pci_restore_state(struct pci_dev *dev);
1002 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1003 int pci_load_and_free_saved_state(struct pci_dev *dev,
1004 struct pci_saved_state **state);
1005 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1006 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1008 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1009 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1010 u16 cap, unsigned int size);
1011 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1012 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1013 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1014 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1015 void pci_pme_active(struct pci_dev *dev, bool enable);
1016 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1017 bool runtime, bool enable);
1018 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1019 int pci_prepare_to_sleep(struct pci_dev *dev);
1020 int pci_back_from_sleep(struct pci_dev *dev);
1021 bool pci_dev_run_wake(struct pci_dev *dev);
1022 bool pci_check_pme_status(struct pci_dev *dev);
1023 void pci_pme_wakeup_bus(struct pci_bus *bus);
1025 static inline void pci_ignore_hotplug(struct pci_dev *dev)
1027 dev->ignore_hotplug = 1;
1030 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1033 return __pci_enable_wake(dev, state, false, enable);
1036 /* PCI Virtual Channel */
1037 int pci_save_vc_state(struct pci_dev *dev);
1038 void pci_restore_vc_state(struct pci_dev *dev);
1039 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1041 /* For use by arch with custom probe code */
1042 void set_pcie_port_type(struct pci_dev *pdev);
1043 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1045 /* Functions for PCI Hotplug drivers to use */
1046 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1047 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1048 unsigned int pci_rescan_bus(struct pci_bus *bus);
1049 void pci_lock_rescan_remove(void);
1050 void pci_unlock_rescan_remove(void);
1052 /* Vital product data routines */
1053 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1054 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1056 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1057 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1058 void pci_bus_assign_resources(const struct pci_bus *bus);
1059 void pci_bus_size_bridges(struct pci_bus *bus);
1060 int pci_claim_resource(struct pci_dev *, int);
1061 void pci_assign_unassigned_resources(void);
1062 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1063 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1064 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1065 void pdev_enable_device(struct pci_dev *);
1066 int pci_enable_resources(struct pci_dev *, int mask);
1067 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
1068 int (*)(const struct pci_dev *, u8, u8));
1069 #define HAVE_PCI_REQ_REGIONS 2
1070 int __must_check pci_request_regions(struct pci_dev *, const char *);
1071 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1072 void pci_release_regions(struct pci_dev *);
1073 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1074 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1075 void pci_release_region(struct pci_dev *, int);
1076 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1077 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1078 void pci_release_selected_regions(struct pci_dev *, int);
1080 /* drivers/pci/bus.c */
1081 struct pci_bus *pci_bus_get(struct pci_bus *bus);
1082 void pci_bus_put(struct pci_bus *bus);
1083 void pci_add_resource(struct list_head *resources, struct resource *res);
1084 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1085 resource_size_t offset);
1086 void pci_free_resource_list(struct list_head *resources);
1087 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
1088 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1089 void pci_bus_remove_resources(struct pci_bus *bus);
1091 #define pci_bus_for_each_resource(bus, res, i) \
1093 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1096 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1097 struct resource *res, resource_size_t size,
1098 resource_size_t align, resource_size_t min,
1099 unsigned long type_mask,
1100 resource_size_t (*alignf)(void *,
1101 const struct resource *,
1106 static inline dma_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1108 struct pci_bus_region region;
1110 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1111 return region.start;
1114 /* Proper probing supporting hot-pluggable devices */
1115 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1116 const char *mod_name);
1119 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1121 #define pci_register_driver(driver) \
1122 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1124 void pci_unregister_driver(struct pci_driver *dev);
1127 * module_pci_driver() - Helper macro for registering a PCI driver
1128 * @__pci_driver: pci_driver struct
1130 * Helper macro for PCI drivers which do not do anything special in module
1131 * init/exit. This eliminates a lot of boilerplate. Each module may only
1132 * use this macro once, and calling it replaces module_init() and module_exit()
1134 #define module_pci_driver(__pci_driver) \
1135 module_driver(__pci_driver, pci_register_driver, \
1136 pci_unregister_driver)
1138 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1139 int pci_add_dynid(struct pci_driver *drv,
1140 unsigned int vendor, unsigned int device,
1141 unsigned int subvendor, unsigned int subdevice,
1142 unsigned int class, unsigned int class_mask,
1143 unsigned long driver_data);
1144 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1145 struct pci_dev *dev);
1146 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1149 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1151 int pci_cfg_space_size(struct pci_dev *dev);
1152 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1153 void pci_setup_bridge(struct pci_bus *bus);
1154 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1155 unsigned long type);
1157 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1158 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1160 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1161 unsigned int command_bits, u32 flags);
1162 /* kmem_cache style wrapper around pci_alloc_consistent() */
1164 #include <linux/pci-dma.h>
1165 #include <linux/dmapool.h>
1167 #define pci_pool dma_pool
1168 #define pci_pool_create(name, pdev, size, align, allocation) \
1169 dma_pool_create(name, &pdev->dev, size, align, allocation)
1170 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1171 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1172 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1174 enum pci_dma_burst_strategy {
1175 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
1176 strategy_parameter is N/A */
1177 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
1179 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
1180 strategy_parameter byte boundaries */
1184 u32 vector; /* kernel uses to write allocated vector */
1185 u16 entry; /* driver uses to specify entry, OS writes */
1189 #ifdef CONFIG_PCI_MSI
1190 int pci_msi_vec_count(struct pci_dev *dev);
1191 void pci_msi_shutdown(struct pci_dev *dev);
1192 void pci_disable_msi(struct pci_dev *dev);
1193 int pci_msix_vec_count(struct pci_dev *dev);
1194 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec);
1195 void pci_msix_shutdown(struct pci_dev *dev);
1196 void pci_disable_msix(struct pci_dev *dev);
1197 void pci_restore_msi_state(struct pci_dev *dev);
1198 int pci_msi_enabled(void);
1199 int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec);
1200 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1202 int rc = pci_enable_msi_range(dev, nvec, nvec);
1207 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1208 int minvec, int maxvec);
1209 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1210 struct msix_entry *entries, int nvec)
1212 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1218 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1219 static inline void pci_msi_shutdown(struct pci_dev *dev) { }
1220 static inline void pci_disable_msi(struct pci_dev *dev) { }
1221 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1222 static inline int pci_enable_msix(struct pci_dev *dev,
1223 struct msix_entry *entries, int nvec)
1225 static inline void pci_msix_shutdown(struct pci_dev *dev) { }
1226 static inline void pci_disable_msix(struct pci_dev *dev) { }
1227 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1228 static inline int pci_msi_enabled(void) { return 0; }
1229 static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec,
1232 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1234 static inline int pci_enable_msix_range(struct pci_dev *dev,
1235 struct msix_entry *entries, int minvec, int maxvec)
1237 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1238 struct msix_entry *entries, int nvec)
1242 #ifdef CONFIG_PCIEPORTBUS
1243 extern bool pcie_ports_disabled;
1244 extern bool pcie_ports_auto;
1246 #define pcie_ports_disabled true
1247 #define pcie_ports_auto false
1250 #ifdef CONFIG_PCIEASPM
1251 bool pcie_aspm_support_enabled(void);
1253 static inline bool pcie_aspm_support_enabled(void) { return false; }
1256 #ifdef CONFIG_PCIEAER
1257 void pci_no_aer(void);
1258 bool pci_aer_available(void);
1260 static inline void pci_no_aer(void) { }
1261 static inline bool pci_aer_available(void) { return false; }
1264 #ifdef CONFIG_PCIE_ECRC
1265 void pcie_set_ecrc_checking(struct pci_dev *dev);
1266 void pcie_ecrc_get_policy(char *str);
1268 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1269 static inline void pcie_ecrc_get_policy(char *str) { }
1272 #define pci_enable_msi(pdev) pci_enable_msi_exact(pdev, 1)
1274 #ifdef CONFIG_HT_IRQ
1275 /* The functions a driver should call */
1276 int ht_create_irq(struct pci_dev *dev, int idx);
1277 void ht_destroy_irq(unsigned int irq);
1278 #endif /* CONFIG_HT_IRQ */
1280 void pci_cfg_access_lock(struct pci_dev *dev);
1281 bool pci_cfg_access_trylock(struct pci_dev *dev);
1282 void pci_cfg_access_unlock(struct pci_dev *dev);
1285 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1286 * a PCI domain is defined to be a set of PCI buses which share
1287 * configuration space.
1289 #ifdef CONFIG_PCI_DOMAINS
1290 extern int pci_domains_supported;
1292 enum { pci_domains_supported = 0 };
1293 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1294 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1295 #endif /* CONFIG_PCI_DOMAINS */
1297 /* some architectures require additional setup to direct VGA traffic */
1298 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1299 unsigned int command_bits, u32 flags);
1300 void pci_register_set_vga_state(arch_set_vga_state_t func);
1302 #else /* CONFIG_PCI is not enabled */
1305 * If the system does not have PCI, clearly these return errors. Define
1306 * these as simple inline functions to avoid hair in drivers.
1309 #define _PCI_NOP(o, s, t) \
1310 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1312 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1314 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1315 _PCI_NOP(o, word, u16 x) \
1316 _PCI_NOP(o, dword, u32 x)
1317 _PCI_NOP_ALL(read, *)
1318 _PCI_NOP_ALL(write,)
1320 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1321 unsigned int device,
1322 struct pci_dev *from)
1325 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1326 unsigned int device,
1327 unsigned int ss_vendor,
1328 unsigned int ss_device,
1329 struct pci_dev *from)
1332 static inline struct pci_dev *pci_get_class(unsigned int class,
1333 struct pci_dev *from)
1336 #define pci_dev_present(ids) (0)
1337 #define no_pci_devices() (1)
1338 #define pci_dev_put(dev) do { } while (0)
1340 static inline void pci_set_master(struct pci_dev *dev) { }
1341 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1342 static inline void pci_disable_device(struct pci_dev *dev) { }
1343 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1345 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1347 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1350 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1353 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1355 static inline int __pci_register_driver(struct pci_driver *drv,
1356 struct module *owner)
1358 static inline int pci_register_driver(struct pci_driver *drv)
1360 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1361 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1363 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1366 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1369 /* Power management related routines */
1370 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1371 static inline void pci_restore_state(struct pci_dev *dev) { }
1372 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1374 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1376 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1379 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1383 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1385 static inline void pci_release_regions(struct pci_dev *dev) { }
1387 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1389 static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1390 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1392 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1394 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1396 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1399 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1403 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1404 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1406 #define dev_is_pci(d) (false)
1407 #define dev_is_pf(d) (false)
1408 #define dev_num_vf(d) (0)
1409 #endif /* CONFIG_PCI */
1411 /* Include architecture-dependent settings and functions */
1413 #include <asm/pci.h>
1415 /* these helpers provide future and backwards compatibility
1416 * for accessing popular PCI BAR info */
1417 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1418 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1419 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1420 #define pci_resource_len(dev,bar) \
1421 ((pci_resource_start((dev), (bar)) == 0 && \
1422 pci_resource_end((dev), (bar)) == \
1423 pci_resource_start((dev), (bar))) ? 0 : \
1425 (pci_resource_end((dev), (bar)) - \
1426 pci_resource_start((dev), (bar)) + 1))
1428 /* Similar to the helpers above, these manipulate per-pci_dev
1429 * driver-specific data. They are really just a wrapper around
1430 * the generic device structure functions of these calls.
1432 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1434 return dev_get_drvdata(&pdev->dev);
1437 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1439 dev_set_drvdata(&pdev->dev, data);
1442 /* If you want to know what to call your pci_dev, ask this function.
1443 * Again, it's a wrapper around the generic device.
1445 static inline const char *pci_name(const struct pci_dev *pdev)
1447 return dev_name(&pdev->dev);
1451 /* Some archs don't want to expose struct resource to userland as-is
1452 * in sysfs and /proc
1454 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1455 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1456 const struct resource *rsrc, resource_size_t *start,
1457 resource_size_t *end)
1459 *start = rsrc->start;
1462 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1466 * The world is not perfect and supplies us with broken PCI devices.
1467 * For at least a part of these bugs we need a work-around, so both
1468 * generic (drivers/pci/quirks.c) and per-architecture code can define
1469 * fixup hooks to be called for particular buggy devices.
1473 u16 vendor; /* You can use PCI_ANY_ID here of course */
1474 u16 device; /* You can use PCI_ANY_ID here of course */
1475 u32 class; /* You can use PCI_ANY_ID here too */
1476 unsigned int class_shift; /* should be 0, 8, 16 */
1477 void (*hook)(struct pci_dev *dev);
1480 enum pci_fixup_pass {
1481 pci_fixup_early, /* Before probing BARs */
1482 pci_fixup_header, /* After reading configuration header */
1483 pci_fixup_final, /* Final phase of device fixups */
1484 pci_fixup_enable, /* pci_enable_device() time */
1485 pci_fixup_resume, /* pci_device_resume() */
1486 pci_fixup_suspend, /* pci_device_suspend() */
1487 pci_fixup_resume_early, /* pci_device_resume_early() */
1488 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1491 /* Anonymous variables would be nice... */
1492 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1493 class_shift, hook) \
1494 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1495 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1496 = { vendor, device, class, class_shift, hook };
1498 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1499 class_shift, hook) \
1500 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1501 hook, vendor, device, class, class_shift, hook)
1502 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1503 class_shift, hook) \
1504 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1505 hook, vendor, device, class, class_shift, hook)
1506 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1507 class_shift, hook) \
1508 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1509 hook, vendor, device, class, class_shift, hook)
1510 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1511 class_shift, hook) \
1512 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1513 hook, vendor, device, class, class_shift, hook)
1514 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1515 class_shift, hook) \
1516 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1517 resume##hook, vendor, device, class, \
1519 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1520 class_shift, hook) \
1521 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1522 resume_early##hook, vendor, device, \
1523 class, class_shift, hook)
1524 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1525 class_shift, hook) \
1526 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1527 suspend##hook, vendor, device, class, \
1529 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1530 class_shift, hook) \
1531 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1532 suspend_late##hook, vendor, device, \
1533 class, class_shift, hook)
1535 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1536 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1537 hook, vendor, device, PCI_ANY_ID, 0, hook)
1538 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1539 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1540 hook, vendor, device, PCI_ANY_ID, 0, hook)
1541 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1542 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1543 hook, vendor, device, PCI_ANY_ID, 0, hook)
1544 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1545 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1546 hook, vendor, device, PCI_ANY_ID, 0, hook)
1547 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1548 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1549 resume##hook, vendor, device, \
1550 PCI_ANY_ID, 0, hook)
1551 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1552 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1553 resume_early##hook, vendor, device, \
1554 PCI_ANY_ID, 0, hook)
1555 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1556 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1557 suspend##hook, vendor, device, \
1558 PCI_ANY_ID, 0, hook)
1559 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1560 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1561 suspend_late##hook, vendor, device, \
1562 PCI_ANY_ID, 0, hook)
1564 #ifdef CONFIG_PCI_QUIRKS
1565 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1566 struct pci_dev *pci_get_dma_source(struct pci_dev *dev);
1567 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1568 void pci_dev_specific_enable_acs(struct pci_dev *dev);
1570 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1571 struct pci_dev *dev) { }
1572 static inline struct pci_dev *pci_get_dma_source(struct pci_dev *dev)
1574 return pci_dev_get(dev);
1576 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1581 static inline void pci_dev_specific_enable_acs(struct pci_dev *dev) { }
1584 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1585 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1586 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1587 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1588 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1590 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1592 extern int pci_pci_problems;
1593 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1594 #define PCIPCI_TRITON 2
1595 #define PCIPCI_NATOMA 4
1596 #define PCIPCI_VIAETBF 8
1597 #define PCIPCI_VSFX 16
1598 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1599 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1601 extern unsigned long pci_cardbus_io_size;
1602 extern unsigned long pci_cardbus_mem_size;
1603 extern u8 pci_dfl_cache_line_size;
1604 extern u8 pci_cache_line_size;
1606 extern unsigned long pci_hotplug_io_size;
1607 extern unsigned long pci_hotplug_mem_size;
1609 /* Architecture-specific versions may override these (weak) */
1610 void pcibios_disable_device(struct pci_dev *dev);
1611 void pcibios_set_master(struct pci_dev *dev);
1612 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1613 enum pcie_reset_state state);
1614 int pcibios_add_device(struct pci_dev *dev);
1615 void pcibios_release_device(struct pci_dev *dev);
1616 void pcibios_penalize_isa_irq(int irq, int active);
1618 #ifdef CONFIG_HIBERNATE_CALLBACKS
1619 extern struct dev_pm_ops pcibios_pm_ops;
1622 #ifdef CONFIG_PCI_MMCONFIG
1623 void __init pci_mmcfg_early_init(void);
1624 void __init pci_mmcfg_late_init(void);
1626 static inline void pci_mmcfg_early_init(void) { }
1627 static inline void pci_mmcfg_late_init(void) { }
1630 int pci_ext_cfg_avail(void);
1632 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1634 #ifdef CONFIG_PCI_IOV
1635 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1636 void pci_disable_sriov(struct pci_dev *dev);
1637 int pci_num_vf(struct pci_dev *dev);
1638 int pci_vfs_assigned(struct pci_dev *dev);
1639 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1640 int pci_sriov_get_totalvfs(struct pci_dev *dev);
1642 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1644 static inline void pci_disable_sriov(struct pci_dev *dev) { }
1645 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
1646 static inline int pci_vfs_assigned(struct pci_dev *dev)
1648 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1650 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1654 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1655 void pci_hp_create_module_link(struct pci_slot *pci_slot);
1656 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1660 * pci_pcie_cap - get the saved PCIe capability offset
1663 * PCIe capability offset is calculated at PCI device initialization
1664 * time and saved in the data structure. This function returns saved
1665 * PCIe capability offset. Using this instead of pci_find_capability()
1666 * reduces unnecessary search in the PCI configuration space. If you
1667 * need to calculate PCIe capability offset from raw device for some
1668 * reasons, please use pci_find_capability() instead.
1670 static inline int pci_pcie_cap(struct pci_dev *dev)
1672 return dev->pcie_cap;
1676 * pci_is_pcie - check if the PCI device is PCI Express capable
1679 * Returns: true if the PCI device is PCI Express capable, false otherwise.
1681 static inline bool pci_is_pcie(struct pci_dev *dev)
1683 return pci_pcie_cap(dev);
1687 * pcie_caps_reg - get the PCIe Capabilities Register
1690 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
1692 return dev->pcie_flags_reg;
1696 * pci_pcie_type - get the PCIe device/port type
1699 static inline int pci_pcie_type(const struct pci_dev *dev)
1701 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
1704 void pci_request_acs(void);
1705 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1706 bool pci_acs_path_enabled(struct pci_dev *start,
1707 struct pci_dev *end, u16 acs_flags);
1709 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1710 #define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT)
1712 /* Large Resource Data Type Tag Item Names */
1713 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1714 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1715 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1717 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1718 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1719 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1721 /* Small Resource Data Type Tag Item Names */
1722 #define PCI_VPD_STIN_END 0x78 /* End */
1724 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1726 #define PCI_VPD_SRDT_TIN_MASK 0x78
1727 #define PCI_VPD_SRDT_LEN_MASK 0x07
1729 #define PCI_VPD_LRDT_TAG_SIZE 3
1730 #define PCI_VPD_SRDT_TAG_SIZE 1
1732 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1734 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1735 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1736 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1737 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
1740 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1741 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1743 * Returns the extracted Large Resource Data Type length.
1745 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1747 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1751 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1752 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1754 * Returns the extracted Small Resource Data Type length.
1756 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1758 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1762 * pci_vpd_info_field_size - Extracts the information field length
1763 * @lrdt: Pointer to the beginning of an information field header
1765 * Returns the extracted information field length.
1767 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1769 return info_field[2];
1773 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1774 * @buf: Pointer to buffered vpd data
1775 * @off: The offset into the buffer at which to begin the search
1776 * @len: The length of the vpd buffer
1777 * @rdt: The Resource Data Type to search for
1779 * Returns the index where the Resource Data Type was found or
1780 * -ENOENT otherwise.
1782 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1785 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1786 * @buf: Pointer to buffered vpd data
1787 * @off: The offset into the buffer at which to begin the search
1788 * @len: The length of the buffer area, relative to off, in which to search
1789 * @kw: The keyword to search for
1791 * Returns the index where the information field keyword was found or
1792 * -ENOENT otherwise.
1794 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1795 unsigned int len, const char *kw);
1797 /* PCI <-> OF binding helpers */
1800 void pci_set_of_node(struct pci_dev *dev);
1801 void pci_release_of_node(struct pci_dev *dev);
1802 void pci_set_bus_of_node(struct pci_bus *bus);
1803 void pci_release_bus_of_node(struct pci_bus *bus);
1805 /* Arch may override this (weak) */
1806 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
1808 static inline struct device_node *
1809 pci_device_to_OF_node(const struct pci_dev *pdev)
1811 return pdev ? pdev->dev.of_node : NULL;
1814 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1816 return bus ? bus->dev.of_node : NULL;
1819 #else /* CONFIG_OF */
1820 static inline void pci_set_of_node(struct pci_dev *dev) { }
1821 static inline void pci_release_of_node(struct pci_dev *dev) { }
1822 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1823 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1824 #endif /* CONFIG_OF */
1827 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
1829 return pdev->dev.archdata.edev;
1833 int pci_for_each_dma_alias(struct pci_dev *pdev,
1834 int (*fn)(struct pci_dev *pdev,
1835 u16 alias, void *data), void *data);
1838 * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device
1839 * @pdev: the PCI device
1841 * if the device is PCIE, return NULL
1842 * if the device isn't connected to a PCIe bridge (that is its parent is a
1843 * legacy PCI bridge and the bridge is directly connected to bus 0), return its
1846 struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);
1848 #endif /* LINUX_PCI_H */