4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
20 #include <linux/mod_devicetable.h>
22 #include <linux/types.h>
23 #include <linux/init.h>
24 #include <linux/ioport.h>
25 #include <linux/list.h>
26 #include <linux/compiler.h>
27 #include <linux/errno.h>
28 #include <linux/kobject.h>
29 #include <linux/atomic.h>
30 #include <linux/device.h>
32 #include <linux/irqreturn.h>
33 #include <uapi/linux/pci.h>
35 /* Include the ID list */
36 #include <linux/pci_ids.h>
39 * The PCI interface treats multi-function devices as independent
40 * devices. The slot/function address of each device is encoded
41 * in a single byte as follows:
45 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined uapi/linux/pci.h
46 * In the interest of not exposing interfaces to user-space unnecessarily,
47 * the following kernel only defines are being added here.
49 #define PCI_DEVID(bus, devfn) ((((u16)bus) << 8) | devfn)
50 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
51 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
53 /* pci_slot represents a physical slot */
55 struct pci_bus *bus; /* The bus this slot is on */
56 struct list_head list; /* node in list of slots on this bus */
57 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
58 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
62 static inline const char *pci_slot_name(const struct pci_slot *slot)
64 return kobject_name(&slot->kobj);
67 /* File state for mmap()s on /proc/bus/pci/X/Y */
73 /* This defines the direction arg to the DMA mapping routines. */
74 #define PCI_DMA_BIDIRECTIONAL 0
75 #define PCI_DMA_TODEVICE 1
76 #define PCI_DMA_FROMDEVICE 2
77 #define PCI_DMA_NONE 3
80 * For PCI devices, the region numbers are assigned this way:
83 /* #0-5: standard PCI resources */
85 PCI_STD_RESOURCE_END = 5,
87 /* #6: expansion ROM resource */
90 /* device specific resources */
93 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
96 /* resources assigned to buses behind the bridge */
97 #define PCI_BRIDGE_RESOURCE_NUM 4
100 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
101 PCI_BRIDGE_RESOURCE_NUM - 1,
103 /* total resources associated with a PCI device */
106 /* preserve this for compatibility */
107 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
110 typedef int __bitwise pci_power_t;
112 #define PCI_D0 ((pci_power_t __force) 0)
113 #define PCI_D1 ((pci_power_t __force) 1)
114 #define PCI_D2 ((pci_power_t __force) 2)
115 #define PCI_D3hot ((pci_power_t __force) 3)
116 #define PCI_D3cold ((pci_power_t __force) 4)
117 #define PCI_UNKNOWN ((pci_power_t __force) 5)
118 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
120 /* Remember to update this when the list above changes! */
121 extern const char *pci_power_names[];
123 static inline const char *pci_power_name(pci_power_t state)
125 return pci_power_names[1 + (int) state];
128 #define PCI_PM_D2_DELAY 200
129 #define PCI_PM_D3_WAIT 10
130 #define PCI_PM_D3COLD_WAIT 100
131 #define PCI_PM_BUS_WAIT 50
133 /** The pci_channel state describes connectivity between the CPU and
134 * the pci device. If some PCI bus between here and the pci device
135 * has crashed or locked up, this info is reflected here.
137 typedef unsigned int __bitwise pci_channel_state_t;
139 enum pci_channel_state {
140 /* I/O channel is in normal state */
141 pci_channel_io_normal = (__force pci_channel_state_t) 1,
143 /* I/O to channel is blocked */
144 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
146 /* PCI card is dead */
147 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
150 typedef unsigned int __bitwise pcie_reset_state_t;
152 enum pcie_reset_state {
153 /* Reset is NOT asserted (Use to deassert reset) */
154 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
156 /* Use #PERST to reset PCI-E device */
157 pcie_warm_reset = (__force pcie_reset_state_t) 2,
159 /* Use PCI-E Hot Reset to reset device */
160 pcie_hot_reset = (__force pcie_reset_state_t) 3
163 typedef unsigned short __bitwise pci_dev_flags_t;
165 /* INTX_DISABLE in PCI_COMMAND register disables MSI
168 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
169 /* Device configuration is irrevocably lost if disabled into D3 */
170 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
171 /* Provide indication device is assigned by a Virtual Machine Manager */
172 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4,
175 enum pci_irq_reroute_variant {
176 INTEL_IRQ_REROUTE_VARIANT = 1,
177 MAX_IRQ_REROUTE_VARIANTS = 3
180 typedef unsigned short __bitwise pci_bus_flags_t;
182 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
183 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
186 /* Based on the PCI Hotplug Spec, but some values are made up by us */
188 PCI_SPEED_33MHz = 0x00,
189 PCI_SPEED_66MHz = 0x01,
190 PCI_SPEED_66MHz_PCIX = 0x02,
191 PCI_SPEED_100MHz_PCIX = 0x03,
192 PCI_SPEED_133MHz_PCIX = 0x04,
193 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
194 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
195 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
196 PCI_SPEED_66MHz_PCIX_266 = 0x09,
197 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
198 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
204 PCI_SPEED_66MHz_PCIX_533 = 0x11,
205 PCI_SPEED_100MHz_PCIX_533 = 0x12,
206 PCI_SPEED_133MHz_PCIX_533 = 0x13,
207 PCIE_SPEED_2_5GT = 0x14,
208 PCIE_SPEED_5_0GT = 0x15,
209 PCIE_SPEED_8_0GT = 0x16,
210 PCI_SPEED_UNKNOWN = 0xff,
213 struct pci_cap_saved_data {
219 struct pci_cap_saved_state {
220 struct hlist_node next;
221 struct pci_cap_saved_data cap;
224 struct pcie_link_state;
230 * The pci_dev structure is used to describe PCI devices.
233 struct list_head bus_list; /* node in per-bus list */
234 struct pci_bus *bus; /* bus this device is on */
235 struct pci_bus *subordinate; /* bus this device bridges to */
237 void *sysdata; /* hook for sys-specific extension */
238 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
239 struct pci_slot *slot; /* Physical slot this device is in */
241 unsigned int devfn; /* encoded device & function index */
242 unsigned short vendor;
243 unsigned short device;
244 unsigned short subsystem_vendor;
245 unsigned short subsystem_device;
246 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
247 u8 revision; /* PCI revision, low byte of class word */
248 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
249 u8 pcie_cap; /* PCI-E capability offset */
250 u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */
251 u8 rom_base_reg; /* which config register controls the ROM */
252 u8 pin; /* which interrupt pin this device uses */
253 u16 pcie_flags_reg; /* cached PCI-E Capabilities Register */
255 struct pci_driver *driver; /* which driver has allocated this device */
256 u64 dma_mask; /* Mask of the bits of bus address this
257 device implements. Normally this is
258 0xffffffff. You only need to change
259 this if your device has broken DMA
260 or supports 64-bit transfers. */
262 struct device_dma_parameters dma_parms;
264 pci_power_t current_state; /* Current operating state. In ACPI-speak,
265 this is D0-D3, D0 being fully functional,
267 int pm_cap; /* PM capability offset in the
268 configuration space */
269 unsigned int pme_support:5; /* Bitmask of states from which PME#
271 unsigned int pme_interrupt:1;
272 unsigned int pme_poll:1; /* Poll device's PME status bit */
273 unsigned int d1_support:1; /* Low power state D1 is supported */
274 unsigned int d2_support:1; /* Low power state D2 is supported */
275 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
276 unsigned int no_d3cold:1; /* D3cold is forbidden */
277 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
278 unsigned int mmio_always_on:1; /* disallow turning off io/mem
279 decoding during bar sizing */
280 unsigned int wakeup_prepared:1;
281 unsigned int runtime_d3cold:1; /* whether go through runtime
282 D3cold, not set for devices
283 powered on/off by the
284 corresponding bridge */
285 unsigned int d3_delay; /* D3->D0 transition time in ms */
286 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
288 #ifdef CONFIG_PCIEASPM
289 struct pcie_link_state *link_state; /* ASPM link state. */
292 pci_channel_state_t error_state; /* current connectivity state */
293 struct device dev; /* Generic device interface */
295 int cfg_size; /* Size of configuration space */
298 * Instead of touching interrupt line and base address registers
299 * directly, use the values stored here. They might be different!
302 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
304 bool match_driver; /* Skip attaching driver */
305 /* These fields are used by common fixups */
306 unsigned int transparent:1; /* Transparent PCI bridge */
307 unsigned int multifunction:1;/* Part of multi-function device */
308 /* keep track of device state */
309 unsigned int is_added:1;
310 unsigned int is_busmaster:1; /* device is busmaster */
311 unsigned int no_msi:1; /* device may not use msi */
312 unsigned int block_cfg_access:1; /* config space access is blocked */
313 unsigned int broken_parity_status:1; /* Device generates false positive parity */
314 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
315 unsigned int msi_enabled:1;
316 unsigned int msix_enabled:1;
317 unsigned int ari_enabled:1; /* ARI forwarding */
318 unsigned int is_managed:1;
319 unsigned int is_pcie:1; /* Obsolete. Will be removed.
320 Use pci_is_pcie() instead */
321 unsigned int needs_freset:1; /* Dev requires fundamental reset */
322 unsigned int state_saved:1;
323 unsigned int is_physfn:1;
324 unsigned int is_virtfn:1;
325 unsigned int reset_fn:1;
326 unsigned int is_hotplug_bridge:1;
327 unsigned int __aer_firmware_first_valid:1;
328 unsigned int __aer_firmware_first:1;
329 unsigned int broken_intx_masking:1;
330 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
331 pci_dev_flags_t dev_flags;
332 atomic_t enable_cnt; /* pci_enable_device has been called */
334 u32 saved_config_space[16]; /* config space saved at suspend time */
335 struct hlist_head saved_cap_space;
336 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
337 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
338 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
339 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
340 #ifdef CONFIG_PCI_MSI
341 struct list_head msi_list;
342 struct kset *msi_kset;
345 #ifdef CONFIG_PCI_ATS
347 struct pci_sriov *sriov; /* SR-IOV capability related */
348 struct pci_dev *physfn; /* the PF this VF is associated with */
350 struct pci_ats *ats; /* Address Translation Service */
352 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
353 size_t romlen; /* Length of ROM if it's not from the BAR */
356 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
358 #ifdef CONFIG_PCI_IOV
366 extern struct pci_dev *alloc_pci_dev(void);
368 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
369 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
371 static inline int pci_channel_offline(struct pci_dev *pdev)
373 return (pdev->error_state != pci_channel_io_normal);
376 extern struct resource busn_resource;
378 struct pci_host_bridge_window {
379 struct list_head list;
380 struct resource *res; /* host bridge aperture (CPU address) */
381 resource_size_t offset; /* bus address + offset = CPU address */
384 struct pci_host_bridge {
386 struct pci_bus *bus; /* root bus */
387 struct list_head windows; /* pci_host_bridge_windows */
388 void (*release_fn)(struct pci_host_bridge *);
392 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
393 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
394 void (*release_fn)(struct pci_host_bridge *),
397 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
400 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
401 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
402 * buses below host bridges or subtractive decode bridges) go in the list.
403 * Use pci_bus_for_each_resource() to iterate through all the resources.
407 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
408 * and there's no way to program the bridge with the details of the window.
409 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
410 * decode bit set, because they are explicit and can be programmed with _SRS.
412 #define PCI_SUBTRACTIVE_DECODE 0x1
414 struct pci_bus_resource {
415 struct list_head list;
416 struct resource *res;
420 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
423 struct list_head node; /* node in list of buses */
424 struct pci_bus *parent; /* parent bus this bridge is on */
425 struct list_head children; /* list of child buses */
426 struct list_head devices; /* list of devices on this bus */
427 struct pci_dev *self; /* bridge device as seen by parent */
428 struct list_head slots; /* list of slots on this bus */
429 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
430 struct list_head resources; /* address space routed to this bus */
431 struct resource busn_res; /* bus numbers routed to this bus */
433 struct pci_ops *ops; /* configuration access functions */
434 void *sysdata; /* hook for sys-specific extension */
435 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
437 unsigned char number; /* bus number */
438 unsigned char primary; /* number of primary bridge */
439 unsigned char max_bus_speed; /* enum pci_bus_speed */
440 unsigned char cur_bus_speed; /* enum pci_bus_speed */
444 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
445 pci_bus_flags_t bus_flags; /* Inherited by child busses */
446 struct device *bridge;
448 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
449 struct bin_attribute *legacy_mem; /* legacy mem */
450 unsigned int is_added:1;
453 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
454 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
457 * Returns true if the pci bus is root (behind host-pci bridge),
460 static inline bool pci_is_root_bus(struct pci_bus *pbus)
462 return !(pbus->parent);
465 #ifdef CONFIG_PCI_MSI
466 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
468 return pci_dev->msi_enabled || pci_dev->msix_enabled;
471 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
475 * Error values that may be returned by PCI functions.
477 #define PCIBIOS_SUCCESSFUL 0x00
478 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
479 #define PCIBIOS_BAD_VENDOR_ID 0x83
480 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
481 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
482 #define PCIBIOS_SET_FAILED 0x88
483 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
486 * Translate above to generic errno for passing back through non-pci.
488 static inline int pcibios_err_to_errno(int err)
490 if (err <= PCIBIOS_SUCCESSFUL)
491 return err; /* Assume already errno */
494 case PCIBIOS_FUNC_NOT_SUPPORTED:
496 case PCIBIOS_BAD_VENDOR_ID:
498 case PCIBIOS_DEVICE_NOT_FOUND:
500 case PCIBIOS_BAD_REGISTER_NUMBER:
502 case PCIBIOS_SET_FAILED:
504 case PCIBIOS_BUFFER_TOO_SMALL:
511 /* Low-level architecture-dependent routines */
514 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
515 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
519 * ACPI needs to be able to access PCI config space before we've done a
520 * PCI bus scan and created pci_bus structures.
522 extern int raw_pci_read(unsigned int domain, unsigned int bus,
523 unsigned int devfn, int reg, int len, u32 *val);
524 extern int raw_pci_write(unsigned int domain, unsigned int bus,
525 unsigned int devfn, int reg, int len, u32 val);
527 struct pci_bus_region {
528 resource_size_t start;
533 spinlock_t lock; /* protects list, index */
534 struct list_head list; /* for IDs added at runtime */
537 /* ---------------------------------------------------------------- */
538 /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
539 * a set of callbacks in struct pci_error_handlers, then that device driver
540 * will be notified of PCI bus errors, and will be driven to recovery
541 * when an error occurs.
544 typedef unsigned int __bitwise pci_ers_result_t;
546 enum pci_ers_result {
547 /* no result/none/not supported in device driver */
548 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
550 /* Device driver can recover without slot reset */
551 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
553 /* Device driver wants slot to be reset. */
554 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
556 /* Device has completely failed, is unrecoverable */
557 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
559 /* Device driver is fully recovered and operational */
560 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
562 /* No AER capabilities registered for the driver */
563 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
566 /* PCI bus error event callbacks */
567 struct pci_error_handlers {
568 /* PCI bus error detected on this device */
569 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
570 enum pci_channel_state error);
572 /* MMIO has been re-enabled, but not DMA */
573 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
575 /* PCI Express link has been reset */
576 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
578 /* PCI slot has been reset */
579 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
581 /* Device driver may resume normal operations */
582 void (*resume)(struct pci_dev *dev);
585 /* ---------------------------------------------------------------- */
589 struct list_head node;
591 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
592 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
593 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
594 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
595 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
596 int (*resume_early) (struct pci_dev *dev);
597 int (*resume) (struct pci_dev *dev); /* Device woken up */
598 void (*shutdown) (struct pci_dev *dev);
599 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
600 const struct pci_error_handlers *err_handler;
601 struct device_driver driver;
602 struct pci_dynids dynids;
605 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
608 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
609 * @_table: device table name
611 * This macro is used to create a struct pci_device_id array (a device table)
612 * in a generic manner.
614 #define DEFINE_PCI_DEVICE_TABLE(_table) \
615 const struct pci_device_id _table[]
618 * PCI_DEVICE - macro used to describe a specific pci device
619 * @vend: the 16 bit PCI Vendor ID
620 * @dev: the 16 bit PCI Device ID
622 * This macro is used to create a struct pci_device_id that matches a
623 * specific device. The subvendor and subdevice fields will be set to
626 #define PCI_DEVICE(vend,dev) \
627 .vendor = (vend), .device = (dev), \
628 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
631 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
632 * @vend: the 16 bit PCI Vendor ID
633 * @dev: the 16 bit PCI Device ID
634 * @subvend: the 16 bit PCI Subvendor ID
635 * @subdev: the 16 bit PCI Subdevice ID
637 * This macro is used to create a struct pci_device_id that matches a
638 * specific device with subsystem information.
640 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
641 .vendor = (vend), .device = (dev), \
642 .subvendor = (subvend), .subdevice = (subdev)
645 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
646 * @dev_class: the class, subclass, prog-if triple for this device
647 * @dev_class_mask: the class mask for this device
649 * This macro is used to create a struct pci_device_id that matches a
650 * specific PCI class. The vendor, device, subvendor, and subdevice
651 * fields will be set to PCI_ANY_ID.
653 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
654 .class = (dev_class), .class_mask = (dev_class_mask), \
655 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
656 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
659 * PCI_VDEVICE - macro used to describe a specific pci device in short form
660 * @vendor: the vendor name
661 * @device: the 16 bit PCI Device ID
663 * This macro is used to create a struct pci_device_id that matches a
664 * specific PCI device. The subvendor, and subdevice fields will be set
665 * to PCI_ANY_ID. The macro allows the next field to follow as the device
669 #define PCI_VDEVICE(vendor, device) \
670 PCI_VENDOR_ID_##vendor, (device), \
671 PCI_ANY_ID, PCI_ANY_ID, 0, 0
673 /* these external functions are only available when PCI support is enabled */
676 extern void pcie_bus_configure_settings(struct pci_bus *bus, u8 smpss);
678 enum pcie_bus_config_types {
681 PCIE_BUS_PERFORMANCE,
685 extern enum pcie_bus_config_types pcie_bus_config;
687 extern struct bus_type pci_bus_type;
689 /* Do NOT directly access these two variables, unless you are arch specific pci
690 * code, or pci core code. */
691 extern struct list_head pci_root_buses; /* list of all known PCI buses */
692 /* Some device drivers need know if pci is initiated */
693 extern int no_pci_devices(void);
695 void pcibios_resource_survey_bus(struct pci_bus *bus);
696 void pcibios_fixup_bus(struct pci_bus *);
697 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
698 /* Architecture specific versions may override this (weak) */
699 char *pcibios_setup(char *str);
701 /* Used only when drivers/pci/setup.c is used */
702 resource_size_t pcibios_align_resource(void *, const struct resource *,
705 void pcibios_update_irq(struct pci_dev *, int irq);
707 /* Weak but can be overriden by arch */
708 void pci_fixup_cardbus(struct pci_bus *);
710 /* Generic PCI functions used internally */
712 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
713 struct resource *res);
714 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
715 struct pci_bus_region *region);
716 void pcibios_scan_specific_bus(int busn);
717 extern struct pci_bus *pci_find_bus(int domain, int busnr);
718 void pci_bus_add_devices(const struct pci_bus *bus);
719 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
720 struct pci_ops *ops, void *sysdata);
721 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
722 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
723 struct pci_ops *ops, void *sysdata,
724 struct list_head *resources);
725 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
726 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
727 void pci_bus_release_busn_res(struct pci_bus *b);
728 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
729 struct pci_ops *ops, void *sysdata,
730 struct list_head *resources);
731 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
733 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
734 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
736 struct hotplug_slot *hotplug);
737 void pci_destroy_slot(struct pci_slot *slot);
738 void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
739 int pci_scan_slot(struct pci_bus *bus, int devfn);
740 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
741 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
742 unsigned int pci_scan_child_bus(struct pci_bus *bus);
743 int __must_check pci_bus_add_device(struct pci_dev *dev);
744 void pci_read_bridge_bases(struct pci_bus *child);
745 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
746 struct resource *res);
747 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
748 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
749 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
750 extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
751 extern void pci_dev_put(struct pci_dev *dev);
752 extern void pci_remove_bus(struct pci_bus *b);
753 extern void pci_stop_and_remove_bus_device(struct pci_dev *dev);
754 void pci_stop_root_bus(struct pci_bus *bus);
755 void pci_remove_root_bus(struct pci_bus *bus);
756 void pci_setup_cardbus(struct pci_bus *bus);
757 extern void pci_sort_breadthfirst(void);
758 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
759 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
760 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
762 /* Generic PCI functions exported to card drivers */
764 enum pci_lost_interrupt_reason {
765 PCI_LOST_IRQ_NO_INFORMATION = 0,
766 PCI_LOST_IRQ_DISABLE_MSI,
767 PCI_LOST_IRQ_DISABLE_MSIX,
768 PCI_LOST_IRQ_DISABLE_ACPI,
770 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
771 int pci_find_capability(struct pci_dev *dev, int cap);
772 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
773 int pci_find_ext_capability(struct pci_dev *dev, int cap);
774 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
775 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
776 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
777 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
779 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
780 struct pci_dev *from);
781 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
782 unsigned int ss_vendor, unsigned int ss_device,
783 struct pci_dev *from);
784 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
785 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
787 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
790 return pci_get_domain_bus_and_slot(0, bus, devfn);
792 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
793 int pci_dev_present(const struct pci_device_id *ids);
795 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
797 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
798 int where, u16 *val);
799 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
800 int where, u32 *val);
801 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
803 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
805 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
807 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
809 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
811 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
813 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
815 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
817 static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
820 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
822 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
824 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
826 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
828 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
830 static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
833 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
836 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
837 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
838 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
839 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
840 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
842 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
845 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
848 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
851 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
854 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
857 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
860 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
863 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
866 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
869 /* user-space driven config access */
870 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
871 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
872 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
873 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
874 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
875 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
877 int __must_check pci_enable_device(struct pci_dev *dev);
878 int __must_check pci_enable_device_io(struct pci_dev *dev);
879 int __must_check pci_enable_device_mem(struct pci_dev *dev);
880 int __must_check pci_reenable_device(struct pci_dev *);
881 int __must_check pcim_enable_device(struct pci_dev *pdev);
882 void pcim_pin_device(struct pci_dev *pdev);
884 static inline int pci_is_enabled(struct pci_dev *pdev)
886 return (atomic_read(&pdev->enable_cnt) > 0);
889 static inline int pci_is_managed(struct pci_dev *pdev)
891 return pdev->is_managed;
894 void pci_disable_device(struct pci_dev *dev);
896 extern unsigned int pcibios_max_latency;
897 void pci_set_master(struct pci_dev *dev);
898 void pci_clear_master(struct pci_dev *dev);
900 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
901 int pci_set_cacheline_size(struct pci_dev *dev);
902 #define HAVE_PCI_SET_MWI
903 int __must_check pci_set_mwi(struct pci_dev *dev);
904 int pci_try_set_mwi(struct pci_dev *dev);
905 void pci_clear_mwi(struct pci_dev *dev);
906 void pci_intx(struct pci_dev *dev, int enable);
907 bool pci_intx_mask_supported(struct pci_dev *dev);
908 bool pci_check_and_mask_intx(struct pci_dev *dev);
909 bool pci_check_and_unmask_intx(struct pci_dev *dev);
910 void pci_msi_off(struct pci_dev *dev);
911 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
912 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
913 int pcix_get_max_mmrbc(struct pci_dev *dev);
914 int pcix_get_mmrbc(struct pci_dev *dev);
915 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
916 int pcie_get_readrq(struct pci_dev *dev);
917 int pcie_set_readrq(struct pci_dev *dev, int rq);
918 int pcie_get_mps(struct pci_dev *dev);
919 int pcie_set_mps(struct pci_dev *dev, int mps);
920 int __pci_reset_function(struct pci_dev *dev);
921 int __pci_reset_function_locked(struct pci_dev *dev);
922 int pci_reset_function(struct pci_dev *dev);
923 void pci_update_resource(struct pci_dev *dev, int resno);
924 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
925 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
926 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
928 /* ROM control related routines */
929 int pci_enable_rom(struct pci_dev *pdev);
930 void pci_disable_rom(struct pci_dev *pdev);
931 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
932 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
933 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
935 /* Power management related routines */
936 int pci_save_state(struct pci_dev *dev);
937 void pci_restore_state(struct pci_dev *dev);
938 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
939 int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state);
940 int pci_load_and_free_saved_state(struct pci_dev *dev,
941 struct pci_saved_state **state);
942 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
943 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
944 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
945 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
946 void pci_pme_active(struct pci_dev *dev, bool enable);
947 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
948 bool runtime, bool enable);
949 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
950 pci_power_t pci_target_state(struct pci_dev *dev);
951 int pci_prepare_to_sleep(struct pci_dev *dev);
952 int pci_back_from_sleep(struct pci_dev *dev);
953 bool pci_dev_run_wake(struct pci_dev *dev);
954 bool pci_check_pme_status(struct pci_dev *dev);
955 void pci_pme_wakeup_bus(struct pci_bus *bus);
957 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
960 return __pci_enable_wake(dev, state, false, enable);
963 #define PCI_EXP_IDO_REQUEST (1<<0)
964 #define PCI_EXP_IDO_COMPLETION (1<<1)
965 void pci_enable_ido(struct pci_dev *dev, unsigned long type);
966 void pci_disable_ido(struct pci_dev *dev, unsigned long type);
968 enum pci_obff_signal_type {
969 PCI_EXP_OBFF_SIGNAL_L0 = 0,
970 PCI_EXP_OBFF_SIGNAL_ALWAYS = 1,
972 int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type);
973 void pci_disable_obff(struct pci_dev *dev);
975 int pci_enable_ltr(struct pci_dev *dev);
976 void pci_disable_ltr(struct pci_dev *dev);
977 int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns);
979 /* For use by arch with custom probe code */
980 void set_pcie_port_type(struct pci_dev *pdev);
981 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
983 /* Functions for PCI Hotplug drivers to use */
984 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
985 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
986 unsigned int pci_rescan_bus(struct pci_bus *bus);
988 /* Vital product data routines */
989 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
990 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
991 int pci_vpd_truncate(struct pci_dev *dev, size_t size);
993 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
994 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
995 void pci_bus_assign_resources(const struct pci_bus *bus);
996 void pci_bus_size_bridges(struct pci_bus *bus);
997 int pci_claim_resource(struct pci_dev *, int);
998 void pci_assign_unassigned_resources(void);
999 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1000 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1001 void pdev_enable_device(struct pci_dev *);
1002 int pci_enable_resources(struct pci_dev *, int mask);
1003 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
1004 int (*)(const struct pci_dev *, u8, u8));
1005 #define HAVE_PCI_REQ_REGIONS 2
1006 int __must_check pci_request_regions(struct pci_dev *, const char *);
1007 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1008 void pci_release_regions(struct pci_dev *);
1009 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1010 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1011 void pci_release_region(struct pci_dev *, int);
1012 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1013 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1014 void pci_release_selected_regions(struct pci_dev *, int);
1016 /* drivers/pci/bus.c */
1017 void pci_add_resource(struct list_head *resources, struct resource *res);
1018 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1019 resource_size_t offset);
1020 void pci_free_resource_list(struct list_head *resources);
1021 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
1022 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1023 void pci_bus_remove_resources(struct pci_bus *bus);
1025 #define pci_bus_for_each_resource(bus, res, i) \
1027 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1030 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1031 struct resource *res, resource_size_t size,
1032 resource_size_t align, resource_size_t min,
1033 unsigned int type_mask,
1034 resource_size_t (*alignf)(void *,
1035 const struct resource *,
1039 void pci_enable_bridges(struct pci_bus *bus);
1041 /* Proper probing supporting hot-pluggable devices */
1042 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1043 const char *mod_name);
1046 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1048 #define pci_register_driver(driver) \
1049 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1051 void pci_unregister_driver(struct pci_driver *dev);
1054 * module_pci_driver() - Helper macro for registering a PCI driver
1055 * @__pci_driver: pci_driver struct
1057 * Helper macro for PCI drivers which do not do anything special in module
1058 * init/exit. This eliminates a lot of boilerplate. Each module may only
1059 * use this macro once, and calling it replaces module_init() and module_exit()
1061 #define module_pci_driver(__pci_driver) \
1062 module_driver(__pci_driver, pci_register_driver, \
1063 pci_unregister_driver)
1065 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1066 int pci_add_dynid(struct pci_driver *drv,
1067 unsigned int vendor, unsigned int device,
1068 unsigned int subvendor, unsigned int subdevice,
1069 unsigned int class, unsigned int class_mask,
1070 unsigned long driver_data);
1071 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1072 struct pci_dev *dev);
1073 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1076 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1078 int pci_cfg_space_size_ext(struct pci_dev *dev);
1079 int pci_cfg_space_size(struct pci_dev *dev);
1080 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1081 void pci_setup_bridge(struct pci_bus *bus);
1082 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1083 unsigned long type);
1085 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1086 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1088 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1089 unsigned int command_bits, u32 flags);
1090 /* kmem_cache style wrapper around pci_alloc_consistent() */
1092 #include <linux/pci-dma.h>
1093 #include <linux/dmapool.h>
1095 #define pci_pool dma_pool
1096 #define pci_pool_create(name, pdev, size, align, allocation) \
1097 dma_pool_create(name, &pdev->dev, size, align, allocation)
1098 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1099 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1100 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1102 enum pci_dma_burst_strategy {
1103 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
1104 strategy_parameter is N/A */
1105 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
1107 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
1108 strategy_parameter byte boundaries */
1112 u32 vector; /* kernel uses to write allocated vector */
1113 u16 entry; /* driver uses to specify entry, OS writes */
1117 #ifndef CONFIG_PCI_MSI
1118 static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
1124 pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec)
1129 static inline void pci_msi_shutdown(struct pci_dev *dev)
1131 static inline void pci_disable_msi(struct pci_dev *dev)
1134 static inline int pci_msix_table_size(struct pci_dev *dev)
1138 static inline int pci_enable_msix(struct pci_dev *dev,
1139 struct msix_entry *entries, int nvec)
1144 static inline void pci_msix_shutdown(struct pci_dev *dev)
1146 static inline void pci_disable_msix(struct pci_dev *dev)
1149 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
1152 static inline void pci_restore_msi_state(struct pci_dev *dev)
1154 static inline int pci_msi_enabled(void)
1159 extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
1160 extern int pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec);
1161 extern void pci_msi_shutdown(struct pci_dev *dev);
1162 extern void pci_disable_msi(struct pci_dev *dev);
1163 extern int pci_msix_table_size(struct pci_dev *dev);
1164 extern int pci_enable_msix(struct pci_dev *dev,
1165 struct msix_entry *entries, int nvec);
1166 extern void pci_msix_shutdown(struct pci_dev *dev);
1167 extern void pci_disable_msix(struct pci_dev *dev);
1168 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
1169 extern void pci_restore_msi_state(struct pci_dev *dev);
1170 extern int pci_msi_enabled(void);
1173 #ifdef CONFIG_PCIEPORTBUS
1174 extern bool pcie_ports_disabled;
1175 extern bool pcie_ports_auto;
1177 #define pcie_ports_disabled true
1178 #define pcie_ports_auto false
1181 #ifndef CONFIG_PCIEASPM
1182 static inline int pcie_aspm_enabled(void) { return 0; }
1183 static inline bool pcie_aspm_support_enabled(void) { return false; }
1185 extern int pcie_aspm_enabled(void);
1186 extern bool pcie_aspm_support_enabled(void);
1189 #ifdef CONFIG_PCIEAER
1190 void pci_no_aer(void);
1191 bool pci_aer_available(void);
1193 static inline void pci_no_aer(void) { }
1194 static inline bool pci_aer_available(void) { return false; }
1197 #ifndef CONFIG_PCIE_ECRC
1198 static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
1202 static inline void pcie_ecrc_get_policy(char *str) {};
1204 extern void pcie_set_ecrc_checking(struct pci_dev *dev);
1205 extern void pcie_ecrc_get_policy(char *str);
1208 #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
1210 #ifdef CONFIG_HT_IRQ
1211 /* The functions a driver should call */
1212 int ht_create_irq(struct pci_dev *dev, int idx);
1213 void ht_destroy_irq(unsigned int irq);
1214 #endif /* CONFIG_HT_IRQ */
1216 extern void pci_cfg_access_lock(struct pci_dev *dev);
1217 extern bool pci_cfg_access_trylock(struct pci_dev *dev);
1218 extern void pci_cfg_access_unlock(struct pci_dev *dev);
1221 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1222 * a PCI domain is defined to be a set of PCI busses which share
1223 * configuration space.
1225 #ifdef CONFIG_PCI_DOMAINS
1226 extern int pci_domains_supported;
1228 enum { pci_domains_supported = 0 };
1229 static inline int pci_domain_nr(struct pci_bus *bus)
1234 static inline int pci_proc_domain(struct pci_bus *bus)
1238 #endif /* CONFIG_PCI_DOMAINS */
1240 /* some architectures require additional setup to direct VGA traffic */
1241 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1242 unsigned int command_bits, u32 flags);
1243 extern void pci_register_set_vga_state(arch_set_vga_state_t func);
1245 #else /* CONFIG_PCI is not enabled */
1248 * If the system does not have PCI, clearly these return errors. Define
1249 * these as simple inline functions to avoid hair in drivers.
1252 #define _PCI_NOP(o, s, t) \
1253 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1255 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1257 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1258 _PCI_NOP(o, word, u16 x) \
1259 _PCI_NOP(o, dword, u32 x)
1260 _PCI_NOP_ALL(read, *)
1261 _PCI_NOP_ALL(write,)
1263 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1264 unsigned int device,
1265 struct pci_dev *from)
1270 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1271 unsigned int device,
1272 unsigned int ss_vendor,
1273 unsigned int ss_device,
1274 struct pci_dev *from)
1279 static inline struct pci_dev *pci_get_class(unsigned int class,
1280 struct pci_dev *from)
1285 #define pci_dev_present(ids) (0)
1286 #define no_pci_devices() (1)
1287 #define pci_dev_put(dev) do { } while (0)
1289 static inline void pci_set_master(struct pci_dev *dev)
1292 static inline int pci_enable_device(struct pci_dev *dev)
1297 static inline void pci_disable_device(struct pci_dev *dev)
1300 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1305 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1310 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1316 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1322 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1327 static inline int __pci_register_driver(struct pci_driver *drv,
1328 struct module *owner)
1333 static inline int pci_register_driver(struct pci_driver *drv)
1338 static inline void pci_unregister_driver(struct pci_driver *drv)
1341 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1346 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1352 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1357 /* Power management related routines */
1358 static inline int pci_save_state(struct pci_dev *dev)
1363 static inline void pci_restore_state(struct pci_dev *dev)
1366 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1371 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1376 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1382 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1388 static inline void pci_enable_ido(struct pci_dev *dev, unsigned long type)
1392 static inline void pci_disable_ido(struct pci_dev *dev, unsigned long type)
1396 static inline int pci_enable_obff(struct pci_dev *dev, unsigned long type)
1401 static inline void pci_disable_obff(struct pci_dev *dev)
1405 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1410 static inline void pci_release_regions(struct pci_dev *dev)
1413 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1415 static inline void pci_block_cfg_access(struct pci_dev *dev)
1418 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1421 static inline void pci_unblock_cfg_access(struct pci_dev *dev)
1424 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1427 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1431 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1435 static inline int pci_domain_nr(struct pci_bus *bus)
1438 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev)
1441 #define dev_is_pci(d) (false)
1442 #define dev_is_pf(d) (false)
1443 #define dev_num_vf(d) (0)
1444 #endif /* CONFIG_PCI */
1446 /* Include architecture-dependent settings and functions */
1448 #include <asm/pci.h>
1450 #ifndef PCIBIOS_MAX_MEM_32
1451 #define PCIBIOS_MAX_MEM_32 (-1)
1454 /* these helpers provide future and backwards compatibility
1455 * for accessing popular PCI BAR info */
1456 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1457 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1458 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1459 #define pci_resource_len(dev,bar) \
1460 ((pci_resource_start((dev), (bar)) == 0 && \
1461 pci_resource_end((dev), (bar)) == \
1462 pci_resource_start((dev), (bar))) ? 0 : \
1464 (pci_resource_end((dev), (bar)) - \
1465 pci_resource_start((dev), (bar)) + 1))
1467 /* Similar to the helpers above, these manipulate per-pci_dev
1468 * driver-specific data. They are really just a wrapper around
1469 * the generic device structure functions of these calls.
1471 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1473 return dev_get_drvdata(&pdev->dev);
1476 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1478 dev_set_drvdata(&pdev->dev, data);
1481 /* If you want to know what to call your pci_dev, ask this function.
1482 * Again, it's a wrapper around the generic device.
1484 static inline const char *pci_name(const struct pci_dev *pdev)
1486 return dev_name(&pdev->dev);
1490 /* Some archs don't want to expose struct resource to userland as-is
1491 * in sysfs and /proc
1493 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1494 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1495 const struct resource *rsrc, resource_size_t *start,
1496 resource_size_t *end)
1498 *start = rsrc->start;
1501 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1505 * The world is not perfect and supplies us with broken PCI devices.
1506 * For at least a part of these bugs we need a work-around, so both
1507 * generic (drivers/pci/quirks.c) and per-architecture code can define
1508 * fixup hooks to be called for particular buggy devices.
1512 u16 vendor; /* You can use PCI_ANY_ID here of course */
1513 u16 device; /* You can use PCI_ANY_ID here of course */
1514 u32 class; /* You can use PCI_ANY_ID here too */
1515 unsigned int class_shift; /* should be 0, 8, 16 */
1516 void (*hook)(struct pci_dev *dev);
1519 enum pci_fixup_pass {
1520 pci_fixup_early, /* Before probing BARs */
1521 pci_fixup_header, /* After reading configuration header */
1522 pci_fixup_final, /* Final phase of device fixups */
1523 pci_fixup_enable, /* pci_enable_device() time */
1524 pci_fixup_resume, /* pci_device_resume() */
1525 pci_fixup_suspend, /* pci_device_suspend */
1526 pci_fixup_resume_early, /* pci_device_resume_early() */
1529 /* Anonymous variables would be nice... */
1530 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1531 class_shift, hook) \
1532 static const struct pci_fixup __pci_fixup_##name __used \
1533 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1534 = { vendor, device, class, class_shift, hook };
1536 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1537 class_shift, hook) \
1538 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1539 vendor##device##hook, vendor, device, class, class_shift, hook)
1540 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1541 class_shift, hook) \
1542 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1543 vendor##device##hook, vendor, device, class, class_shift, hook)
1544 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1545 class_shift, hook) \
1546 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1547 vendor##device##hook, vendor, device, class, class_shift, hook)
1548 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1549 class_shift, hook) \
1550 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1551 vendor##device##hook, vendor, device, class, class_shift, hook)
1552 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1553 class_shift, hook) \
1554 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1555 resume##vendor##device##hook, vendor, device, class, \
1557 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1558 class_shift, hook) \
1559 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1560 resume_early##vendor##device##hook, vendor, device, \
1561 class, class_shift, hook)
1562 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1563 class_shift, hook) \
1564 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1565 suspend##vendor##device##hook, vendor, device, class, \
1568 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1569 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1570 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1571 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1572 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1573 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1574 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1575 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1576 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1577 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1578 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1579 vendor##device##hook, vendor, device, PCI_ANY_ID, 0, hook)
1580 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1581 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1582 resume##vendor##device##hook, vendor, device, \
1583 PCI_ANY_ID, 0, hook)
1584 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1585 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1586 resume_early##vendor##device##hook, vendor, device, \
1587 PCI_ANY_ID, 0, hook)
1588 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1589 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1590 suspend##vendor##device##hook, vendor, device, \
1591 PCI_ANY_ID, 0, hook)
1593 #ifdef CONFIG_PCI_QUIRKS
1594 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1595 struct pci_dev *pci_get_dma_source(struct pci_dev *dev);
1596 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1598 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1599 struct pci_dev *dev) {}
1600 static inline struct pci_dev *pci_get_dma_source(struct pci_dev *dev)
1602 return pci_dev_get(dev);
1604 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1611 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1612 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1613 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1614 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1615 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1617 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1619 extern int pci_pci_problems;
1620 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1621 #define PCIPCI_TRITON 2
1622 #define PCIPCI_NATOMA 4
1623 #define PCIPCI_VIAETBF 8
1624 #define PCIPCI_VSFX 16
1625 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1626 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1628 extern unsigned long pci_cardbus_io_size;
1629 extern unsigned long pci_cardbus_mem_size;
1630 extern u8 pci_dfl_cache_line_size;
1631 extern u8 pci_cache_line_size;
1633 extern unsigned long pci_hotplug_io_size;
1634 extern unsigned long pci_hotplug_mem_size;
1636 /* Architecture specific versions may override these (weak) */
1637 int pcibios_add_platform_entries(struct pci_dev *dev);
1638 void pcibios_disable_device(struct pci_dev *dev);
1639 void pcibios_set_master(struct pci_dev *dev);
1640 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1641 enum pcie_reset_state state);
1642 int pcibios_add_device(struct pci_dev *dev);
1644 #ifdef CONFIG_PCI_MMCONFIG
1645 extern void __init pci_mmcfg_early_init(void);
1646 extern void __init pci_mmcfg_late_init(void);
1648 static inline void pci_mmcfg_early_init(void) { }
1649 static inline void pci_mmcfg_late_init(void) { }
1652 int pci_ext_cfg_avail(void);
1654 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1656 #ifdef CONFIG_PCI_IOV
1657 extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1658 extern void pci_disable_sriov(struct pci_dev *dev);
1659 extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
1660 extern int pci_num_vf(struct pci_dev *dev);
1661 extern int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1662 extern int pci_sriov_get_totalvfs(struct pci_dev *dev);
1664 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1668 static inline void pci_disable_sriov(struct pci_dev *dev)
1671 static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1675 static inline int pci_num_vf(struct pci_dev *dev)
1679 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1683 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1689 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1690 extern void pci_hp_create_module_link(struct pci_slot *pci_slot);
1691 extern void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1695 * pci_pcie_cap - get the saved PCIe capability offset
1698 * PCIe capability offset is calculated at PCI device initialization
1699 * time and saved in the data structure. This function returns saved
1700 * PCIe capability offset. Using this instead of pci_find_capability()
1701 * reduces unnecessary search in the PCI configuration space. If you
1702 * need to calculate PCIe capability offset from raw device for some
1703 * reasons, please use pci_find_capability() instead.
1705 static inline int pci_pcie_cap(struct pci_dev *dev)
1707 return dev->pcie_cap;
1711 * pci_is_pcie - check if the PCI device is PCI Express capable
1714 * Retrun true if the PCI device is PCI Express capable, false otherwise.
1716 static inline bool pci_is_pcie(struct pci_dev *dev)
1718 return !!pci_pcie_cap(dev);
1722 * pcie_caps_reg - get the PCIe Capabilities Register
1725 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
1727 return dev->pcie_flags_reg;
1731 * pci_pcie_type - get the PCIe device/port type
1734 static inline int pci_pcie_type(const struct pci_dev *dev)
1736 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
1739 void pci_request_acs(void);
1740 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1741 bool pci_acs_path_enabled(struct pci_dev *start,
1742 struct pci_dev *end, u16 acs_flags);
1744 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1745 #define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT)
1747 /* Large Resource Data Type Tag Item Names */
1748 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1749 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1750 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1752 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1753 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1754 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1756 /* Small Resource Data Type Tag Item Names */
1757 #define PCI_VPD_STIN_END 0x78 /* End */
1759 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1761 #define PCI_VPD_SRDT_TIN_MASK 0x78
1762 #define PCI_VPD_SRDT_LEN_MASK 0x07
1764 #define PCI_VPD_LRDT_TAG_SIZE 3
1765 #define PCI_VPD_SRDT_TAG_SIZE 1
1767 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1769 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1770 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1771 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1772 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
1775 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1776 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1778 * Returns the extracted Large Resource Data Type length.
1780 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1782 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1786 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1787 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1789 * Returns the extracted Small Resource Data Type length.
1791 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1793 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1797 * pci_vpd_info_field_size - Extracts the information field length
1798 * @lrdt: Pointer to the beginning of an information field header
1800 * Returns the extracted information field length.
1802 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1804 return info_field[2];
1808 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1809 * @buf: Pointer to buffered vpd data
1810 * @off: The offset into the buffer at which to begin the search
1811 * @len: The length of the vpd buffer
1812 * @rdt: The Resource Data Type to search for
1814 * Returns the index where the Resource Data Type was found or
1815 * -ENOENT otherwise.
1817 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1820 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1821 * @buf: Pointer to buffered vpd data
1822 * @off: The offset into the buffer at which to begin the search
1823 * @len: The length of the buffer area, relative to off, in which to search
1824 * @kw: The keyword to search for
1826 * Returns the index where the information field keyword was found or
1827 * -ENOENT otherwise.
1829 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1830 unsigned int len, const char *kw);
1832 /* PCI <-> OF binding helpers */
1835 extern void pci_set_of_node(struct pci_dev *dev);
1836 extern void pci_release_of_node(struct pci_dev *dev);
1837 extern void pci_set_bus_of_node(struct pci_bus *bus);
1838 extern void pci_release_bus_of_node(struct pci_bus *bus);
1840 /* Arch may override this (weak) */
1841 extern struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
1843 static inline struct device_node *
1844 pci_device_to_OF_node(const struct pci_dev *pdev)
1846 return pdev ? pdev->dev.of_node : NULL;
1849 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1851 return bus ? bus->dev.of_node : NULL;
1854 #else /* CONFIG_OF */
1855 static inline void pci_set_of_node(struct pci_dev *dev) { }
1856 static inline void pci_release_of_node(struct pci_dev *dev) { }
1857 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1858 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1859 #endif /* CONFIG_OF */
1862 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
1864 return pdev->dev.archdata.edev;
1869 * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device
1870 * @pdev: the PCI device
1872 * if the device is PCIE, return NULL
1873 * if the device isn't connected to a PCIe bridge (that is its parent is a
1874 * legacy PCI bridge and the bridge is directly connected to bus 0), return its
1877 struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);
1879 #endif /* LINUX_PCI_H */