4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
20 #include <linux/pci_regs.h> /* The pci register defines */
23 * The PCI interface treats multi-function devices as independent
24 * devices. The slot/function address of each device is encoded
25 * in a single byte as follows:
30 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
31 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
32 #define PCI_FUNC(devfn) ((devfn) & 0x07)
34 /* Ioctls for /proc/bus/pci/X/Y nodes. */
35 #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
36 #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
37 #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
38 #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
39 #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
43 #include <linux/mod_devicetable.h>
45 #include <linux/types.h>
46 #include <linux/init.h>
47 #include <linux/ioport.h>
48 #include <linux/list.h>
49 #include <linux/compiler.h>
50 #include <linux/errno.h>
51 #include <linux/kobject.h>
52 #include <linux/atomic.h>
53 #include <linux/device.h>
55 #include <linux/irqreturn.h>
57 /* Include the ID list */
58 #include <linux/pci_ids.h>
60 /* pci_slot represents a physical slot */
62 struct pci_bus *bus; /* The bus this slot is on */
63 struct list_head list; /* node in list of slots on this bus */
64 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
65 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
69 static inline const char *pci_slot_name(const struct pci_slot *slot)
71 return kobject_name(&slot->kobj);
74 /* File state for mmap()s on /proc/bus/pci/X/Y */
80 /* This defines the direction arg to the DMA mapping routines. */
81 #define PCI_DMA_BIDIRECTIONAL 0
82 #define PCI_DMA_TODEVICE 1
83 #define PCI_DMA_FROMDEVICE 2
84 #define PCI_DMA_NONE 3
87 * For PCI devices, the region numbers are assigned this way:
90 /* #0-5: standard PCI resources */
92 PCI_STD_RESOURCE_END = 5,
94 /* #6: expansion ROM resource */
97 /* device specific resources */
100 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
103 /* resources assigned to buses behind the bridge */
104 #define PCI_BRIDGE_RESOURCE_NUM 4
106 PCI_BRIDGE_RESOURCES,
107 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
108 PCI_BRIDGE_RESOURCE_NUM - 1,
110 /* total resources associated with a PCI device */
113 /* preserve this for compatibility */
114 DEVICE_COUNT_RESOURCE
117 typedef int __bitwise pci_power_t;
119 #define PCI_D0 ((pci_power_t __force) 0)
120 #define PCI_D1 ((pci_power_t __force) 1)
121 #define PCI_D2 ((pci_power_t __force) 2)
122 #define PCI_D3hot ((pci_power_t __force) 3)
123 #define PCI_D3cold ((pci_power_t __force) 4)
124 #define PCI_UNKNOWN ((pci_power_t __force) 5)
125 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
127 /* Remember to update this when the list above changes! */
128 extern const char *pci_power_names[];
130 static inline const char *pci_power_name(pci_power_t state)
132 return pci_power_names[1 + (int) state];
135 #define PCI_PM_D2_DELAY 200
136 #define PCI_PM_D3_WAIT 10
137 #define PCI_PM_BUS_WAIT 50
139 /** The pci_channel state describes connectivity between the CPU and
140 * the pci device. If some PCI bus between here and the pci device
141 * has crashed or locked up, this info is reflected here.
143 typedef unsigned int __bitwise pci_channel_state_t;
145 enum pci_channel_state {
146 /* I/O channel is in normal state */
147 pci_channel_io_normal = (__force pci_channel_state_t) 1,
149 /* I/O to channel is blocked */
150 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
152 /* PCI card is dead */
153 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
156 typedef unsigned int __bitwise pcie_reset_state_t;
158 enum pcie_reset_state {
159 /* Reset is NOT asserted (Use to deassert reset) */
160 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
162 /* Use #PERST to reset PCI-E device */
163 pcie_warm_reset = (__force pcie_reset_state_t) 2,
165 /* Use PCI-E Hot Reset to reset device */
166 pcie_hot_reset = (__force pcie_reset_state_t) 3
169 typedef unsigned short __bitwise pci_dev_flags_t;
171 /* INTX_DISABLE in PCI_COMMAND register disables MSI
174 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) 1,
175 /* Device configuration is irrevocably lost if disabled into D3 */
176 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) 2,
177 /* Provide indication device is assigned by a Virtual Machine Manager */
178 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) 4,
181 enum pci_irq_reroute_variant {
182 INTEL_IRQ_REROUTE_VARIANT = 1,
183 MAX_IRQ_REROUTE_VARIANTS = 3
186 typedef unsigned short __bitwise pci_bus_flags_t;
188 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
189 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
192 /* Based on the PCI Hotplug Spec, but some values are made up by us */
194 PCI_SPEED_33MHz = 0x00,
195 PCI_SPEED_66MHz = 0x01,
196 PCI_SPEED_66MHz_PCIX = 0x02,
197 PCI_SPEED_100MHz_PCIX = 0x03,
198 PCI_SPEED_133MHz_PCIX = 0x04,
199 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
200 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
201 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
202 PCI_SPEED_66MHz_PCIX_266 = 0x09,
203 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
204 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
210 PCI_SPEED_66MHz_PCIX_533 = 0x11,
211 PCI_SPEED_100MHz_PCIX_533 = 0x12,
212 PCI_SPEED_133MHz_PCIX_533 = 0x13,
213 PCIE_SPEED_2_5GT = 0x14,
214 PCIE_SPEED_5_0GT = 0x15,
215 PCIE_SPEED_8_0GT = 0x16,
216 PCI_SPEED_UNKNOWN = 0xff,
219 struct pci_cap_saved_data {
225 struct pci_cap_saved_state {
226 struct hlist_node next;
227 struct pci_cap_saved_data cap;
230 struct pcie_link_state;
236 * The pci_dev structure is used to describe PCI devices.
239 struct list_head bus_list; /* node in per-bus list */
240 struct pci_bus *bus; /* bus this device is on */
241 struct pci_bus *subordinate; /* bus this device bridges to */
243 void *sysdata; /* hook for sys-specific extension */
244 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
245 struct pci_slot *slot; /* Physical slot this device is in */
247 unsigned int devfn; /* encoded device & function index */
248 unsigned short vendor;
249 unsigned short device;
250 unsigned short subsystem_vendor;
251 unsigned short subsystem_device;
252 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
253 u8 revision; /* PCI revision, low byte of class word */
254 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
255 u8 pcie_cap; /* PCI-E capability offset */
256 u8 pcie_type; /* PCI-E device/port type */
257 u8 rom_base_reg; /* which config register controls the ROM */
258 u8 pin; /* which interrupt pin this device uses */
260 struct pci_driver *driver; /* which driver has allocated this device */
261 u64 dma_mask; /* Mask of the bits of bus address this
262 device implements. Normally this is
263 0xffffffff. You only need to change
264 this if your device has broken DMA
265 or supports 64-bit transfers. */
267 struct device_dma_parameters dma_parms;
269 pci_power_t current_state; /* Current operating state. In ACPI-speak,
270 this is D0-D3, D0 being fully functional,
272 int pm_cap; /* PM capability offset in the
273 configuration space */
274 unsigned int pme_support:5; /* Bitmask of states from which PME#
276 unsigned int pme_interrupt:1;
277 unsigned int d1_support:1; /* Low power state D1 is supported */
278 unsigned int d2_support:1; /* Low power state D2 is supported */
279 unsigned int no_d1d2:1; /* Only allow D0 and D3 */
280 unsigned int mmio_always_on:1; /* disallow turning off io/mem
281 decoding during bar sizing */
282 unsigned int wakeup_prepared:1;
283 unsigned int d3_delay; /* D3->D0 transition time in ms */
285 #ifdef CONFIG_PCIEASPM
286 struct pcie_link_state *link_state; /* ASPM link state. */
289 pci_channel_state_t error_state; /* current connectivity state */
290 struct device dev; /* Generic device interface */
292 int cfg_size; /* Size of configuration space */
295 * Instead of touching interrupt line and base address registers
296 * directly, use the values stored here. They might be different!
299 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
300 resource_size_t fw_addr[DEVICE_COUNT_RESOURCE]; /* FW-assigned addr */
302 /* These fields are used by common fixups */
303 unsigned int transparent:1; /* Transparent PCI bridge */
304 unsigned int multifunction:1;/* Part of multi-function device */
305 /* keep track of device state */
306 unsigned int is_added:1;
307 unsigned int is_busmaster:1; /* device is busmaster */
308 unsigned int no_msi:1; /* device may not use msi */
309 unsigned int block_ucfg_access:1; /* userspace config space access is blocked */
310 unsigned int broken_parity_status:1; /* Device generates false positive parity */
311 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
312 unsigned int msi_enabled:1;
313 unsigned int msix_enabled:1;
314 unsigned int ari_enabled:1; /* ARI forwarding */
315 unsigned int is_managed:1;
316 unsigned int is_pcie:1; /* Obsolete. Will be removed.
317 Use pci_is_pcie() instead */
318 unsigned int needs_freset:1; /* Dev requires fundamental reset */
319 unsigned int state_saved:1;
320 unsigned int is_physfn:1;
321 unsigned int is_virtfn:1;
322 unsigned int reset_fn:1;
323 unsigned int is_hotplug_bridge:1;
324 unsigned int __aer_firmware_first_valid:1;
325 unsigned int __aer_firmware_first:1;
326 pci_dev_flags_t dev_flags;
327 atomic_t enable_cnt; /* pci_enable_device has been called */
329 u32 saved_config_space[16]; /* config space saved at suspend time */
330 struct hlist_head saved_cap_space;
331 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
332 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
333 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
334 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
335 #ifdef CONFIG_PCI_MSI
336 struct list_head msi_list;
339 #ifdef CONFIG_PCI_IOV
341 struct pci_sriov *sriov; /* SR-IOV capability related */
342 struct pci_dev *physfn; /* the PF this VF is associated with */
344 struct pci_ats *ats; /* Address Translation Service */
348 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
350 #ifdef CONFIG_PCI_IOV
358 extern struct pci_dev *alloc_pci_dev(void);
360 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
361 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
362 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
364 static inline int pci_channel_offline(struct pci_dev *pdev)
366 return (pdev->error_state != pci_channel_io_normal);
369 static inline struct pci_cap_saved_state *pci_find_saved_cap(
370 struct pci_dev *pci_dev, char cap)
372 struct pci_cap_saved_state *tmp;
373 struct hlist_node *pos;
375 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
376 if (tmp->cap.cap_nr == cap)
382 static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
383 struct pci_cap_saved_state *new_cap)
385 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
389 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
390 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
391 * buses below host bridges or subtractive decode bridges) go in the list.
392 * Use pci_bus_for_each_resource() to iterate through all the resources.
396 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
397 * and there's no way to program the bridge with the details of the window.
398 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
399 * decode bit set, because they are explicit and can be programmed with _SRS.
401 #define PCI_SUBTRACTIVE_DECODE 0x1
403 struct pci_bus_resource {
404 struct list_head list;
405 struct resource *res;
409 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
412 struct list_head node; /* node in list of buses */
413 struct pci_bus *parent; /* parent bus this bridge is on */
414 struct list_head children; /* list of child buses */
415 struct list_head devices; /* list of devices on this bus */
416 struct pci_dev *self; /* bridge device as seen by parent */
417 struct list_head slots; /* list of slots on this bus */
418 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
419 struct list_head resources; /* address space routed to this bus */
421 struct pci_ops *ops; /* configuration access functions */
422 void *sysdata; /* hook for sys-specific extension */
423 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
425 unsigned char number; /* bus number */
426 unsigned char primary; /* number of primary bridge */
427 unsigned char secondary; /* number of secondary bridge */
428 unsigned char subordinate; /* max number of subordinate buses */
429 unsigned char max_bus_speed; /* enum pci_bus_speed */
430 unsigned char cur_bus_speed; /* enum pci_bus_speed */
434 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
435 pci_bus_flags_t bus_flags; /* Inherited by child busses */
436 struct device *bridge;
438 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
439 struct bin_attribute *legacy_mem; /* legacy mem */
440 unsigned int is_added:1;
443 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
444 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
447 * Returns true if the pci bus is root (behind host-pci bridge),
450 static inline bool pci_is_root_bus(struct pci_bus *pbus)
452 return !(pbus->parent);
455 #ifdef CONFIG_PCI_MSI
456 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
458 return pci_dev->msi_enabled || pci_dev->msix_enabled;
461 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
465 * Error values that may be returned by PCI functions.
467 #define PCIBIOS_SUCCESSFUL 0x00
468 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
469 #define PCIBIOS_BAD_VENDOR_ID 0x83
470 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
471 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
472 #define PCIBIOS_SET_FAILED 0x88
473 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
475 /* Low-level architecture-dependent routines */
478 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
479 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
483 * ACPI needs to be able to access PCI config space before we've done a
484 * PCI bus scan and created pci_bus structures.
486 extern int raw_pci_read(unsigned int domain, unsigned int bus,
487 unsigned int devfn, int reg, int len, u32 *val);
488 extern int raw_pci_write(unsigned int domain, unsigned int bus,
489 unsigned int devfn, int reg, int len, u32 val);
491 struct pci_bus_region {
492 resource_size_t start;
497 spinlock_t lock; /* protects list, index */
498 struct list_head list; /* for IDs added at runtime */
501 /* ---------------------------------------------------------------- */
502 /** PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
503 * a set of callbacks in struct pci_error_handlers, then that device driver
504 * will be notified of PCI bus errors, and will be driven to recovery
505 * when an error occurs.
508 typedef unsigned int __bitwise pci_ers_result_t;
510 enum pci_ers_result {
511 /* no result/none/not supported in device driver */
512 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
514 /* Device driver can recover without slot reset */
515 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
517 /* Device driver wants slot to be reset. */
518 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
520 /* Device has completely failed, is unrecoverable */
521 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
523 /* Device driver is fully recovered and operational */
524 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
527 /* PCI bus error event callbacks */
528 struct pci_error_handlers {
529 /* PCI bus error detected on this device */
530 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
531 enum pci_channel_state error);
533 /* MMIO has been re-enabled, but not DMA */
534 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
536 /* PCI Express link has been reset */
537 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
539 /* PCI slot has been reset */
540 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
542 /* Device driver may resume normal operations */
543 void (*resume)(struct pci_dev *dev);
546 /* ---------------------------------------------------------------- */
550 struct list_head node;
552 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
553 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
554 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
555 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
556 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
557 int (*resume_early) (struct pci_dev *dev);
558 int (*resume) (struct pci_dev *dev); /* Device woken up */
559 void (*shutdown) (struct pci_dev *dev);
560 struct pci_error_handlers *err_handler;
561 struct device_driver driver;
562 struct pci_dynids dynids;
565 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
568 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
569 * @_table: device table name
571 * This macro is used to create a struct pci_device_id array (a device table)
572 * in a generic manner.
574 #define DEFINE_PCI_DEVICE_TABLE(_table) \
575 const struct pci_device_id _table[] __devinitconst
578 * PCI_DEVICE - macro used to describe a specific pci device
579 * @vend: the 16 bit PCI Vendor ID
580 * @dev: the 16 bit PCI Device ID
582 * This macro is used to create a struct pci_device_id that matches a
583 * specific device. The subvendor and subdevice fields will be set to
586 #define PCI_DEVICE(vend,dev) \
587 .vendor = (vend), .device = (dev), \
588 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
591 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
592 * @dev_class: the class, subclass, prog-if triple for this device
593 * @dev_class_mask: the class mask for this device
595 * This macro is used to create a struct pci_device_id that matches a
596 * specific PCI class. The vendor, device, subvendor, and subdevice
597 * fields will be set to PCI_ANY_ID.
599 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
600 .class = (dev_class), .class_mask = (dev_class_mask), \
601 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
602 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
605 * PCI_VDEVICE - macro used to describe a specific pci device in short form
606 * @vendor: the vendor name
607 * @device: the 16 bit PCI Device ID
609 * This macro is used to create a struct pci_device_id that matches a
610 * specific PCI device. The subvendor, and subdevice fields will be set
611 * to PCI_ANY_ID. The macro allows the next field to follow as the device
615 #define PCI_VDEVICE(vendor, device) \
616 PCI_VENDOR_ID_##vendor, (device), \
617 PCI_ANY_ID, PCI_ANY_ID, 0, 0
619 /* these external functions are only available when PCI support is enabled */
622 extern struct bus_type pci_bus_type;
624 /* Do NOT directly access these two variables, unless you are arch specific pci
625 * code, or pci core code. */
626 extern struct list_head pci_root_buses; /* list of all known PCI buses */
627 /* Some device drivers need know if pci is initiated */
628 extern int no_pci_devices(void);
630 void pcibios_fixup_bus(struct pci_bus *);
631 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
632 char *pcibios_setup(char *str);
634 /* Used only when drivers/pci/setup.c is used */
635 resource_size_t pcibios_align_resource(void *, const struct resource *,
638 void pcibios_update_irq(struct pci_dev *, int irq);
640 /* Weak but can be overriden by arch */
641 void pci_fixup_cardbus(struct pci_bus *);
643 /* Generic PCI functions used internally */
645 void pcibios_scan_specific_bus(int busn);
646 extern struct pci_bus *pci_find_bus(int domain, int busnr);
647 void pci_bus_add_devices(const struct pci_bus *bus);
648 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
649 struct pci_ops *ops, void *sysdata);
650 static inline struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops,
653 struct pci_bus *root_bus;
654 root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata);
656 pci_bus_add_devices(root_bus);
659 struct pci_bus *pci_create_bus(struct device *parent, int bus,
660 struct pci_ops *ops, void *sysdata);
661 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
663 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
664 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
666 struct hotplug_slot *hotplug);
667 void pci_destroy_slot(struct pci_slot *slot);
668 void pci_renumber_slot(struct pci_slot *slot, int slot_nr);
669 int pci_scan_slot(struct pci_bus *bus, int devfn);
670 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
671 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
672 unsigned int pci_scan_child_bus(struct pci_bus *bus);
673 int __must_check pci_bus_add_device(struct pci_dev *dev);
674 void pci_read_bridge_bases(struct pci_bus *child);
675 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
676 struct resource *res);
677 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin);
678 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
679 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
680 extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
681 extern void pci_dev_put(struct pci_dev *dev);
682 extern void pci_remove_bus(struct pci_bus *b);
683 extern void pci_remove_bus_device(struct pci_dev *dev);
684 extern void pci_stop_bus_device(struct pci_dev *dev);
685 void pci_setup_cardbus(struct pci_bus *bus);
686 extern void pci_sort_breadthfirst(void);
687 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
688 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
689 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
691 /* Generic PCI functions exported to card drivers */
693 enum pci_lost_interrupt_reason {
694 PCI_LOST_IRQ_NO_INFORMATION = 0,
695 PCI_LOST_IRQ_DISABLE_MSI,
696 PCI_LOST_IRQ_DISABLE_MSIX,
697 PCI_LOST_IRQ_DISABLE_ACPI,
699 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
700 int pci_find_capability(struct pci_dev *dev, int cap);
701 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
702 int pci_find_ext_capability(struct pci_dev *dev, int cap);
703 int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
705 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
706 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
707 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
709 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
710 struct pci_dev *from);
711 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
712 unsigned int ss_vendor, unsigned int ss_device,
713 struct pci_dev *from);
714 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
715 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
717 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
720 return pci_get_domain_bus_and_slot(0, bus, devfn);
722 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
723 int pci_dev_present(const struct pci_device_id *ids);
725 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
727 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
728 int where, u16 *val);
729 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
730 int where, u32 *val);
731 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
733 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
735 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
737 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
739 static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
741 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
743 static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
745 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
747 static inline int pci_read_config_dword(struct pci_dev *dev, int where,
750 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
752 static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
754 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
756 static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val)
758 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
760 static inline int pci_write_config_dword(struct pci_dev *dev, int where,
763 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
766 int __must_check pci_enable_device(struct pci_dev *dev);
767 int __must_check pci_enable_device_io(struct pci_dev *dev);
768 int __must_check pci_enable_device_mem(struct pci_dev *dev);
769 int __must_check pci_reenable_device(struct pci_dev *);
770 int __must_check pcim_enable_device(struct pci_dev *pdev);
771 void pcim_pin_device(struct pci_dev *pdev);
773 static inline int pci_is_enabled(struct pci_dev *pdev)
775 return (atomic_read(&pdev->enable_cnt) > 0);
778 static inline int pci_is_managed(struct pci_dev *pdev)
780 return pdev->is_managed;
783 void pci_disable_device(struct pci_dev *dev);
784 void pci_set_master(struct pci_dev *dev);
785 void pci_clear_master(struct pci_dev *dev);
786 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
787 int pci_set_cacheline_size(struct pci_dev *dev);
788 #define HAVE_PCI_SET_MWI
789 int __must_check pci_set_mwi(struct pci_dev *dev);
790 int pci_try_set_mwi(struct pci_dev *dev);
791 void pci_clear_mwi(struct pci_dev *dev);
792 void pci_intx(struct pci_dev *dev, int enable);
793 void pci_msi_off(struct pci_dev *dev);
794 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
795 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
796 int pcix_get_max_mmrbc(struct pci_dev *dev);
797 int pcix_get_mmrbc(struct pci_dev *dev);
798 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
799 int pcie_get_readrq(struct pci_dev *dev);
800 int pcie_set_readrq(struct pci_dev *dev, int rq);
801 int __pci_reset_function(struct pci_dev *dev);
802 int pci_reset_function(struct pci_dev *dev);
803 void pci_update_resource(struct pci_dev *dev, int resno);
804 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
805 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
807 /* ROM control related routines */
808 int pci_enable_rom(struct pci_dev *pdev);
809 void pci_disable_rom(struct pci_dev *pdev);
810 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
811 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
812 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
814 /* Power management related routines */
815 int pci_save_state(struct pci_dev *dev);
816 void pci_restore_state(struct pci_dev *dev);
817 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
818 int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state);
819 int pci_load_and_free_saved_state(struct pci_dev *dev,
820 struct pci_saved_state **state);
821 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
822 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
823 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
824 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
825 void pci_pme_active(struct pci_dev *dev, bool enable);
826 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
827 bool runtime, bool enable);
828 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
829 pci_power_t pci_target_state(struct pci_dev *dev);
830 int pci_prepare_to_sleep(struct pci_dev *dev);
831 int pci_back_from_sleep(struct pci_dev *dev);
832 bool pci_dev_run_wake(struct pci_dev *dev);
833 bool pci_check_pme_status(struct pci_dev *dev);
834 void pci_pme_wakeup_bus(struct pci_bus *bus);
836 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
839 return __pci_enable_wake(dev, state, false, enable);
842 #define PCI_EXP_IDO_REQUEST (1<<0)
843 #define PCI_EXP_IDO_COMPLETION (1<<1)
844 void pci_enable_ido(struct pci_dev *dev, unsigned long type);
845 void pci_disable_ido(struct pci_dev *dev, unsigned long type);
847 enum pci_obff_signal_type {
848 PCI_EXP_OBFF_SIGNAL_L0 = 0,
849 PCI_EXP_OBFF_SIGNAL_ALWAYS = 1,
851 int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type);
852 void pci_disable_obff(struct pci_dev *dev);
854 bool pci_ltr_supported(struct pci_dev *dev);
855 int pci_enable_ltr(struct pci_dev *dev);
856 void pci_disable_ltr(struct pci_dev *dev);
857 int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns);
859 /* For use by arch with custom probe code */
860 void set_pcie_port_type(struct pci_dev *pdev);
861 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
863 /* Functions for PCI Hotplug drivers to use */
864 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
865 #ifdef CONFIG_HOTPLUG
866 unsigned int pci_rescan_bus(struct pci_bus *bus);
869 /* Vital product data routines */
870 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
871 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
872 int pci_vpd_truncate(struct pci_dev *dev, size_t size);
874 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
875 void pci_bus_assign_resources(const struct pci_bus *bus);
876 void pci_bus_size_bridges(struct pci_bus *bus);
877 int pci_claim_resource(struct pci_dev *, int);
878 void pci_assign_unassigned_resources(void);
879 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
880 void pdev_enable_device(struct pci_dev *);
881 void pdev_sort_resources(struct pci_dev *, struct resource_list *);
882 int pci_enable_resources(struct pci_dev *, int mask);
883 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
884 int (*)(const struct pci_dev *, u8, u8));
885 #define HAVE_PCI_REQ_REGIONS 2
886 int __must_check pci_request_regions(struct pci_dev *, const char *);
887 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
888 void pci_release_regions(struct pci_dev *);
889 int __must_check pci_request_region(struct pci_dev *, int, const char *);
890 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
891 void pci_release_region(struct pci_dev *, int);
892 int pci_request_selected_regions(struct pci_dev *, int, const char *);
893 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
894 void pci_release_selected_regions(struct pci_dev *, int);
896 /* drivers/pci/bus.c */
897 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
898 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
899 void pci_bus_remove_resources(struct pci_bus *bus);
901 #define pci_bus_for_each_resource(bus, res, i) \
903 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
906 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
907 struct resource *res, resource_size_t size,
908 resource_size_t align, resource_size_t min,
909 unsigned int type_mask,
910 resource_size_t (*alignf)(void *,
911 const struct resource *,
915 void pci_enable_bridges(struct pci_bus *bus);
917 /* Proper probing supporting hot-pluggable devices */
918 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
919 const char *mod_name);
922 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
924 #define pci_register_driver(driver) \
925 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
927 void pci_unregister_driver(struct pci_driver *dev);
928 void pci_remove_behind_bridge(struct pci_dev *dev);
929 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
930 int pci_add_dynid(struct pci_driver *drv,
931 unsigned int vendor, unsigned int device,
932 unsigned int subvendor, unsigned int subdevice,
933 unsigned int class, unsigned int class_mask,
934 unsigned long driver_data);
935 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
936 struct pci_dev *dev);
937 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
940 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
942 int pci_cfg_space_size_ext(struct pci_dev *dev);
943 int pci_cfg_space_size(struct pci_dev *dev);
944 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
946 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
947 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
949 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
950 unsigned int command_bits, u32 flags);
951 /* kmem_cache style wrapper around pci_alloc_consistent() */
953 #include <linux/pci-dma.h>
954 #include <linux/dmapool.h>
956 #define pci_pool dma_pool
957 #define pci_pool_create(name, pdev, size, align, allocation) \
958 dma_pool_create(name, &pdev->dev, size, align, allocation)
959 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
960 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
961 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
963 enum pci_dma_burst_strategy {
964 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
965 strategy_parameter is N/A */
966 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
968 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
969 strategy_parameter byte boundaries */
973 u32 vector; /* kernel uses to write allocated vector */
974 u16 entry; /* driver uses to specify entry, OS writes */
978 #ifndef CONFIG_PCI_MSI
979 static inline int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
984 static inline void pci_msi_shutdown(struct pci_dev *dev)
986 static inline void pci_disable_msi(struct pci_dev *dev)
989 static inline int pci_msix_table_size(struct pci_dev *dev)
993 static inline int pci_enable_msix(struct pci_dev *dev,
994 struct msix_entry *entries, int nvec)
999 static inline void pci_msix_shutdown(struct pci_dev *dev)
1001 static inline void pci_disable_msix(struct pci_dev *dev)
1004 static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
1007 static inline void pci_restore_msi_state(struct pci_dev *dev)
1009 static inline int pci_msi_enabled(void)
1014 extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
1015 extern void pci_msi_shutdown(struct pci_dev *dev);
1016 extern void pci_disable_msi(struct pci_dev *dev);
1017 extern int pci_msix_table_size(struct pci_dev *dev);
1018 extern int pci_enable_msix(struct pci_dev *dev,
1019 struct msix_entry *entries, int nvec);
1020 extern void pci_msix_shutdown(struct pci_dev *dev);
1021 extern void pci_disable_msix(struct pci_dev *dev);
1022 extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
1023 extern void pci_restore_msi_state(struct pci_dev *dev);
1024 extern int pci_msi_enabled(void);
1027 #ifdef CONFIG_PCIEPORTBUS
1028 extern bool pcie_ports_disabled;
1029 extern bool pcie_ports_auto;
1031 #define pcie_ports_disabled true
1032 #define pcie_ports_auto false
1035 #ifndef CONFIG_PCIEASPM
1036 static inline int pcie_aspm_enabled(void) { return 0; }
1037 static inline bool pcie_aspm_support_enabled(void) { return false; }
1039 extern int pcie_aspm_enabled(void);
1040 extern bool pcie_aspm_support_enabled(void);
1043 #ifdef CONFIG_PCIEAER
1044 void pci_no_aer(void);
1045 bool pci_aer_available(void);
1047 static inline void pci_no_aer(void) { }
1048 static inline bool pci_aer_available(void) { return false; }
1051 #ifndef CONFIG_PCIE_ECRC
1052 static inline void pcie_set_ecrc_checking(struct pci_dev *dev)
1056 static inline void pcie_ecrc_get_policy(char *str) {};
1058 extern void pcie_set_ecrc_checking(struct pci_dev *dev);
1059 extern void pcie_ecrc_get_policy(char *str);
1062 #define pci_enable_msi(pdev) pci_enable_msi_block(pdev, 1)
1064 #ifdef CONFIG_HT_IRQ
1065 /* The functions a driver should call */
1066 int ht_create_irq(struct pci_dev *dev, int idx);
1067 void ht_destroy_irq(unsigned int irq);
1068 #endif /* CONFIG_HT_IRQ */
1070 extern void pci_block_user_cfg_access(struct pci_dev *dev);
1071 extern void pci_unblock_user_cfg_access(struct pci_dev *dev);
1074 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1075 * a PCI domain is defined to be a set of PCI busses which share
1076 * configuration space.
1078 #ifdef CONFIG_PCI_DOMAINS
1079 extern int pci_domains_supported;
1081 enum { pci_domains_supported = 0 };
1082 static inline int pci_domain_nr(struct pci_bus *bus)
1087 static inline int pci_proc_domain(struct pci_bus *bus)
1091 #endif /* CONFIG_PCI_DOMAINS */
1093 /* some architectures require additional setup to direct VGA traffic */
1094 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1095 unsigned int command_bits, u32 flags);
1096 extern void pci_register_set_vga_state(arch_set_vga_state_t func);
1098 #else /* CONFIG_PCI is not enabled */
1101 * If the system does not have PCI, clearly these return errors. Define
1102 * these as simple inline functions to avoid hair in drivers.
1105 #define _PCI_NOP(o, s, t) \
1106 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1108 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1110 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1111 _PCI_NOP(o, word, u16 x) \
1112 _PCI_NOP(o, dword, u32 x)
1113 _PCI_NOP_ALL(read, *)
1114 _PCI_NOP_ALL(write,)
1116 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1117 unsigned int device,
1118 struct pci_dev *from)
1123 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1124 unsigned int device,
1125 unsigned int ss_vendor,
1126 unsigned int ss_device,
1127 struct pci_dev *from)
1132 static inline struct pci_dev *pci_get_class(unsigned int class,
1133 struct pci_dev *from)
1138 #define pci_dev_present(ids) (0)
1139 #define no_pci_devices() (1)
1140 #define pci_dev_put(dev) do { } while (0)
1142 static inline void pci_set_master(struct pci_dev *dev)
1145 static inline int pci_enable_device(struct pci_dev *dev)
1150 static inline void pci_disable_device(struct pci_dev *dev)
1153 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1158 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1163 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1169 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1175 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1180 static inline int __pci_register_driver(struct pci_driver *drv,
1181 struct module *owner)
1186 static inline int pci_register_driver(struct pci_driver *drv)
1191 static inline void pci_unregister_driver(struct pci_driver *drv)
1194 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1199 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1205 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1210 /* Power management related routines */
1211 static inline int pci_save_state(struct pci_dev *dev)
1216 static inline void pci_restore_state(struct pci_dev *dev)
1219 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1224 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1229 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1235 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1241 static inline void pci_enable_ido(struct pci_dev *dev, unsigned long type)
1245 static inline void pci_disable_ido(struct pci_dev *dev, unsigned long type)
1249 static inline int pci_enable_obff(struct pci_dev *dev, unsigned long type)
1254 static inline void pci_disable_obff(struct pci_dev *dev)
1258 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1263 static inline void pci_release_regions(struct pci_dev *dev)
1266 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1268 static inline void pci_block_user_cfg_access(struct pci_dev *dev)
1271 static inline void pci_unblock_user_cfg_access(struct pci_dev *dev)
1274 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1277 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1281 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1285 static inline int pci_domain_nr(struct pci_bus *bus)
1288 #define dev_is_pci(d) (false)
1289 #define dev_is_pf(d) (false)
1290 #define dev_num_vf(d) (0)
1291 #endif /* CONFIG_PCI */
1293 /* Include architecture-dependent settings and functions */
1295 #include <asm/pci.h>
1297 #ifndef PCIBIOS_MAX_MEM_32
1298 #define PCIBIOS_MAX_MEM_32 (-1)
1301 /* these helpers provide future and backwards compatibility
1302 * for accessing popular PCI BAR info */
1303 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1304 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1305 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1306 #define pci_resource_len(dev,bar) \
1307 ((pci_resource_start((dev), (bar)) == 0 && \
1308 pci_resource_end((dev), (bar)) == \
1309 pci_resource_start((dev), (bar))) ? 0 : \
1311 (pci_resource_end((dev), (bar)) - \
1312 pci_resource_start((dev), (bar)) + 1))
1314 /* Similar to the helpers above, these manipulate per-pci_dev
1315 * driver-specific data. They are really just a wrapper around
1316 * the generic device structure functions of these calls.
1318 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1320 return dev_get_drvdata(&pdev->dev);
1323 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1325 dev_set_drvdata(&pdev->dev, data);
1328 /* If you want to know what to call your pci_dev, ask this function.
1329 * Again, it's a wrapper around the generic device.
1331 static inline const char *pci_name(const struct pci_dev *pdev)
1333 return dev_name(&pdev->dev);
1337 /* Some archs don't want to expose struct resource to userland as-is
1338 * in sysfs and /proc
1340 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1341 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1342 const struct resource *rsrc, resource_size_t *start,
1343 resource_size_t *end)
1345 *start = rsrc->start;
1348 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1352 * The world is not perfect and supplies us with broken PCI devices.
1353 * For at least a part of these bugs we need a work-around, so both
1354 * generic (drivers/pci/quirks.c) and per-architecture code can define
1355 * fixup hooks to be called for particular buggy devices.
1359 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
1360 void (*hook)(struct pci_dev *dev);
1363 enum pci_fixup_pass {
1364 pci_fixup_early, /* Before probing BARs */
1365 pci_fixup_header, /* After reading configuration header */
1366 pci_fixup_final, /* Final phase of device fixups */
1367 pci_fixup_enable, /* pci_enable_device() time */
1368 pci_fixup_resume, /* pci_device_resume() */
1369 pci_fixup_suspend, /* pci_device_suspend */
1370 pci_fixup_resume_early, /* pci_device_resume_early() */
1373 /* Anonymous variables would be nice... */
1374 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, hook) \
1375 static const struct pci_fixup __pci_fixup_##name __used \
1376 __attribute__((__section__(#section))) = { vendor, device, hook };
1377 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1378 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1379 vendor##device##hook, vendor, device, hook)
1380 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1381 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1382 vendor##device##hook, vendor, device, hook)
1383 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1384 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1385 vendor##device##hook, vendor, device, hook)
1386 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1387 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1388 vendor##device##hook, vendor, device, hook)
1389 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1390 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1391 resume##vendor##device##hook, vendor, device, hook)
1392 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1393 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1394 resume_early##vendor##device##hook, vendor, device, hook)
1395 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1396 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1397 suspend##vendor##device##hook, vendor, device, hook)
1399 #ifdef CONFIG_PCI_QUIRKS
1400 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1402 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1403 struct pci_dev *dev) {}
1406 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1407 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1408 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1409 int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name);
1410 int pcim_iomap_regions_request_all(struct pci_dev *pdev, u16 mask,
1412 void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask);
1414 extern int pci_pci_problems;
1415 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1416 #define PCIPCI_TRITON 2
1417 #define PCIPCI_NATOMA 4
1418 #define PCIPCI_VIAETBF 8
1419 #define PCIPCI_VSFX 16
1420 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1421 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1423 extern unsigned long pci_cardbus_io_size;
1424 extern unsigned long pci_cardbus_mem_size;
1425 extern u8 __devinitdata pci_dfl_cache_line_size;
1426 extern u8 pci_cache_line_size;
1428 extern unsigned long pci_hotplug_io_size;
1429 extern unsigned long pci_hotplug_mem_size;
1431 int pcibios_add_platform_entries(struct pci_dev *dev);
1432 void pcibios_disable_device(struct pci_dev *dev);
1433 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1434 enum pcie_reset_state state);
1436 #ifdef CONFIG_PCI_MMCONFIG
1437 extern void __init pci_mmcfg_early_init(void);
1438 extern void __init pci_mmcfg_late_init(void);
1440 static inline void pci_mmcfg_early_init(void) { }
1441 static inline void pci_mmcfg_late_init(void) { }
1444 int pci_ext_cfg_avail(struct pci_dev *dev);
1446 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1448 #ifdef CONFIG_PCI_IOV
1449 extern int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1450 extern void pci_disable_sriov(struct pci_dev *dev);
1451 extern irqreturn_t pci_sriov_migration(struct pci_dev *dev);
1452 extern int pci_num_vf(struct pci_dev *dev);
1454 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1458 static inline void pci_disable_sriov(struct pci_dev *dev)
1461 static inline irqreturn_t pci_sriov_migration(struct pci_dev *dev)
1465 static inline int pci_num_vf(struct pci_dev *dev)
1471 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1472 extern void pci_hp_create_module_link(struct pci_slot *pci_slot);
1473 extern void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1477 * pci_pcie_cap - get the saved PCIe capability offset
1480 * PCIe capability offset is calculated at PCI device initialization
1481 * time and saved in the data structure. This function returns saved
1482 * PCIe capability offset. Using this instead of pci_find_capability()
1483 * reduces unnecessary search in the PCI configuration space. If you
1484 * need to calculate PCIe capability offset from raw device for some
1485 * reasons, please use pci_find_capability() instead.
1487 static inline int pci_pcie_cap(struct pci_dev *dev)
1489 return dev->pcie_cap;
1493 * pci_is_pcie - check if the PCI device is PCI Express capable
1496 * Retrun true if the PCI device is PCI Express capable, false otherwise.
1498 static inline bool pci_is_pcie(struct pci_dev *dev)
1500 return !!pci_pcie_cap(dev);
1503 void pci_request_acs(void);
1506 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1507 #define PCI_VPD_LRDT_ID(x) (x | PCI_VPD_LRDT)
1509 /* Large Resource Data Type Tag Item Names */
1510 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1511 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1512 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1514 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1515 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1516 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1518 /* Small Resource Data Type Tag Item Names */
1519 #define PCI_VPD_STIN_END 0x78 /* End */
1521 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1523 #define PCI_VPD_SRDT_TIN_MASK 0x78
1524 #define PCI_VPD_SRDT_LEN_MASK 0x07
1526 #define PCI_VPD_LRDT_TAG_SIZE 3
1527 #define PCI_VPD_SRDT_TAG_SIZE 1
1529 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1531 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1532 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1533 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1534 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
1537 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1538 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1540 * Returns the extracted Large Resource Data Type length.
1542 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1544 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1548 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1549 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1551 * Returns the extracted Small Resource Data Type length.
1553 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1555 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1559 * pci_vpd_info_field_size - Extracts the information field length
1560 * @lrdt: Pointer to the beginning of an information field header
1562 * Returns the extracted information field length.
1564 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1566 return info_field[2];
1570 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1571 * @buf: Pointer to buffered vpd data
1572 * @off: The offset into the buffer at which to begin the search
1573 * @len: The length of the vpd buffer
1574 * @rdt: The Resource Data Type to search for
1576 * Returns the index where the Resource Data Type was found or
1577 * -ENOENT otherwise.
1579 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1582 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1583 * @buf: Pointer to buffered vpd data
1584 * @off: The offset into the buffer at which to begin the search
1585 * @len: The length of the buffer area, relative to off, in which to search
1586 * @kw: The keyword to search for
1588 * Returns the index where the information field keyword was found or
1589 * -ENOENT otherwise.
1591 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1592 unsigned int len, const char *kw);
1594 /* PCI <-> OF binding helpers */
1597 extern void pci_set_of_node(struct pci_dev *dev);
1598 extern void pci_release_of_node(struct pci_dev *dev);
1599 extern void pci_set_bus_of_node(struct pci_bus *bus);
1600 extern void pci_release_bus_of_node(struct pci_bus *bus);
1602 /* Arch may override this (weak) */
1603 extern struct device_node * __weak pcibios_get_phb_of_node(struct pci_bus *bus);
1605 static inline struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
1607 return pdev ? pdev->dev.of_node : NULL;
1610 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1612 return bus ? bus->dev.of_node : NULL;
1615 #else /* CONFIG_OF */
1616 static inline void pci_set_of_node(struct pci_dev *dev) { }
1617 static inline void pci_release_of_node(struct pci_dev *dev) { }
1618 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1619 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1620 #endif /* CONFIG_OF */
1623 * pci_find_upstream_pcie_bridge - find upstream PCIe-to-PCI bridge of a device
1624 * @pdev: the PCI device
1626 * if the device is PCIE, return NULL
1627 * if the device isn't connected to a PCIe bridge (that is its parent is a
1628 * legacy PCI bridge and the bridge is directly connected to bus 0), return its
1631 struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);
1633 #endif /* __KERNEL__ */
1634 #endif /* LINUX_PCI_H */