4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
20 #include <linux/mod_devicetable.h>
22 #include <linux/types.h>
23 #include <linux/init.h>
24 #include <linux/ioport.h>
25 #include <linux/list.h>
26 #include <linux/compiler.h>
27 #include <linux/errno.h>
28 #include <linux/kobject.h>
29 #include <linux/atomic.h>
30 #include <linux/device.h>
32 #include <uapi/linux/pci.h>
34 #include <linux/pci_ids.h>
37 * The PCI interface treats multi-function devices as independent
38 * devices. The slot/function address of each device is encoded
39 * in a single byte as follows:
44 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
45 * In the interest of not exposing interfaces to user-space unnecessarily,
46 * the following kernel-only defines are being added here.
48 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
49 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
50 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
52 /* pci_slot represents a physical slot */
54 struct pci_bus *bus; /* The bus this slot is on */
55 struct list_head list; /* node in list of slots on this bus */
56 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
57 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
61 static inline const char *pci_slot_name(const struct pci_slot *slot)
63 return kobject_name(&slot->kobj);
66 /* File state for mmap()s on /proc/bus/pci/X/Y */
72 /* This defines the direction arg to the DMA mapping routines. */
73 #define PCI_DMA_BIDIRECTIONAL 0
74 #define PCI_DMA_TODEVICE 1
75 #define PCI_DMA_FROMDEVICE 2
76 #define PCI_DMA_NONE 3
79 * For PCI devices, the region numbers are assigned this way:
82 /* #0-5: standard PCI resources */
84 PCI_STD_RESOURCE_END = 5,
86 /* #6: expansion ROM resource */
89 /* device specific resources */
92 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
95 /* resources assigned to buses behind the bridge */
96 #define PCI_BRIDGE_RESOURCE_NUM 4
99 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
100 PCI_BRIDGE_RESOURCE_NUM - 1,
102 /* total resources associated with a PCI device */
105 /* preserve this for compatibility */
106 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
109 typedef int __bitwise pci_power_t;
111 #define PCI_D0 ((pci_power_t __force) 0)
112 #define PCI_D1 ((pci_power_t __force) 1)
113 #define PCI_D2 ((pci_power_t __force) 2)
114 #define PCI_D3hot ((pci_power_t __force) 3)
115 #define PCI_D3cold ((pci_power_t __force) 4)
116 #define PCI_UNKNOWN ((pci_power_t __force) 5)
117 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
119 /* Remember to update this when the list above changes! */
120 extern const char *pci_power_names[];
122 static inline const char *pci_power_name(pci_power_t state)
124 return pci_power_names[1 + (int) state];
127 #define PCI_PM_D2_DELAY 200
128 #define PCI_PM_D3_WAIT 10
129 #define PCI_PM_D3COLD_WAIT 100
130 #define PCI_PM_BUS_WAIT 50
132 /** The pci_channel state describes connectivity between the CPU and
133 * the pci device. If some PCI bus between here and the pci device
134 * has crashed or locked up, this info is reflected here.
136 typedef unsigned int __bitwise pci_channel_state_t;
138 enum pci_channel_state {
139 /* I/O channel is in normal state */
140 pci_channel_io_normal = (__force pci_channel_state_t) 1,
142 /* I/O to channel is blocked */
143 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
145 /* PCI card is dead */
146 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
149 typedef unsigned int __bitwise pcie_reset_state_t;
151 enum pcie_reset_state {
152 /* Reset is NOT asserted (Use to deassert reset) */
153 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
155 /* Use #PERST to reset PCIe device */
156 pcie_warm_reset = (__force pcie_reset_state_t) 2,
158 /* Use PCIe Hot Reset to reset device */
159 pcie_hot_reset = (__force pcie_reset_state_t) 3
162 typedef unsigned short __bitwise pci_dev_flags_t;
164 /* INTX_DISABLE in PCI_COMMAND register disables MSI
167 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
168 /* Device configuration is irrevocably lost if disabled into D3 */
169 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
170 /* Provide indication device is assigned by a Virtual Machine Manager */
171 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
172 /* Flag for quirk use to store if quirk-specific ACS is enabled */
173 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
174 /* Flag to indicate the device uses dma_alias_devfn */
175 PCI_DEV_FLAGS_DMA_ALIAS_DEVFN = (__force pci_dev_flags_t) (1 << 4),
176 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
177 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
178 /* Do not use bus resets for device */
179 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
182 enum pci_irq_reroute_variant {
183 INTEL_IRQ_REROUTE_VARIANT = 1,
184 MAX_IRQ_REROUTE_VARIANTS = 3
187 typedef unsigned short __bitwise pci_bus_flags_t;
189 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
190 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
193 /* These values come from the PCI Express Spec */
194 enum pcie_link_width {
195 PCIE_LNK_WIDTH_RESRV = 0x00,
203 PCIE_LNK_WIDTH_UNKNOWN = 0xFF,
206 /* Based on the PCI Hotplug Spec, but some values are made up by us */
208 PCI_SPEED_33MHz = 0x00,
209 PCI_SPEED_66MHz = 0x01,
210 PCI_SPEED_66MHz_PCIX = 0x02,
211 PCI_SPEED_100MHz_PCIX = 0x03,
212 PCI_SPEED_133MHz_PCIX = 0x04,
213 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
214 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
215 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
216 PCI_SPEED_66MHz_PCIX_266 = 0x09,
217 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
218 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
224 PCI_SPEED_66MHz_PCIX_533 = 0x11,
225 PCI_SPEED_100MHz_PCIX_533 = 0x12,
226 PCI_SPEED_133MHz_PCIX_533 = 0x13,
227 PCIE_SPEED_2_5GT = 0x14,
228 PCIE_SPEED_5_0GT = 0x15,
229 PCIE_SPEED_8_0GT = 0x16,
230 PCI_SPEED_UNKNOWN = 0xff,
233 struct pci_cap_saved_data {
240 struct pci_cap_saved_state {
241 struct hlist_node next;
242 struct pci_cap_saved_data cap;
245 struct pcie_link_state;
251 * The pci_dev structure is used to describe PCI devices.
254 struct list_head bus_list; /* node in per-bus list */
255 struct pci_bus *bus; /* bus this device is on */
256 struct pci_bus *subordinate; /* bus this device bridges to */
258 void *sysdata; /* hook for sys-specific extension */
259 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
260 struct pci_slot *slot; /* Physical slot this device is in */
262 unsigned int devfn; /* encoded device & function index */
263 unsigned short vendor;
264 unsigned short device;
265 unsigned short subsystem_vendor;
266 unsigned short subsystem_device;
267 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
268 u8 revision; /* PCI revision, low byte of class word */
269 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
270 u8 pcie_cap; /* PCIe capability offset */
271 u8 msi_cap; /* MSI capability offset */
272 u8 msix_cap; /* MSI-X capability offset */
273 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
274 u8 rom_base_reg; /* which config register controls the ROM */
275 u8 pin; /* which interrupt pin this device uses */
276 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */
277 u8 dma_alias_devfn;/* devfn of DMA alias, if any */
279 struct pci_driver *driver; /* which driver has allocated this device */
280 u64 dma_mask; /* Mask of the bits of bus address this
281 device implements. Normally this is
282 0xffffffff. You only need to change
283 this if your device has broken DMA
284 or supports 64-bit transfers. */
286 struct device_dma_parameters dma_parms;
288 pci_power_t current_state; /* Current operating state. In ACPI-speak,
289 this is D0-D3, D0 being fully functional,
291 u8 pm_cap; /* PM capability offset */
292 unsigned int pme_support:5; /* Bitmask of states from which PME#
294 unsigned int pme_interrupt:1;
295 unsigned int pme_poll:1; /* Poll device's PME status bit */
296 unsigned int d1_support:1; /* Low power state D1 is supported */
297 unsigned int d2_support:1; /* Low power state D2 is supported */
298 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
299 unsigned int no_d3cold:1; /* D3cold is forbidden */
300 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
301 unsigned int mmio_always_on:1; /* disallow turning off io/mem
302 decoding during bar sizing */
303 unsigned int wakeup_prepared:1;
304 unsigned int runtime_d3cold:1; /* whether go through runtime
305 D3cold, not set for devices
306 powered on/off by the
307 corresponding bridge */
308 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
309 unsigned int d3_delay; /* D3->D0 transition time in ms */
310 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
312 #ifdef CONFIG_PCIEASPM
313 struct pcie_link_state *link_state; /* ASPM link state */
316 pci_channel_state_t error_state; /* current connectivity state */
317 struct device dev; /* Generic device interface */
319 int cfg_size; /* Size of configuration space */
322 * Instead of touching interrupt line and base address registers
323 * directly, use the values stored here. They might be different!
326 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
328 bool match_driver; /* Skip attaching driver */
329 /* These fields are used by common fixups */
330 unsigned int transparent:1; /* Subtractive decode PCI bridge */
331 unsigned int multifunction:1;/* Part of multi-function device */
332 /* keep track of device state */
333 unsigned int is_added:1;
334 unsigned int is_busmaster:1; /* device is busmaster */
335 unsigned int no_msi:1; /* device may not use msi */
336 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */
337 unsigned int block_cfg_access:1; /* config space access is blocked */
338 unsigned int broken_parity_status:1; /* Device generates false positive parity */
339 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
340 unsigned int msi_enabled:1;
341 unsigned int msix_enabled:1;
342 unsigned int ari_enabled:1; /* ARI forwarding */
343 unsigned int is_managed:1;
344 unsigned int needs_freset:1; /* Dev requires fundamental reset */
345 unsigned int state_saved:1;
346 unsigned int is_physfn:1;
347 unsigned int is_virtfn:1;
348 unsigned int reset_fn:1;
349 unsigned int is_hotplug_bridge:1;
350 unsigned int __aer_firmware_first_valid:1;
351 unsigned int __aer_firmware_first:1;
352 unsigned int broken_intx_masking:1;
353 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
354 unsigned int irq_managed:1;
355 pci_dev_flags_t dev_flags;
356 atomic_t enable_cnt; /* pci_enable_device has been called */
358 u32 saved_config_space[16]; /* config space saved at suspend time */
359 struct hlist_head saved_cap_space;
360 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
361 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
362 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
363 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
364 #ifdef CONFIG_PCI_MSI
365 struct list_head msi_list;
366 const struct attribute_group **msi_irq_groups;
369 #ifdef CONFIG_PCI_ATS
371 struct pci_sriov *sriov; /* SR-IOV capability related */
372 struct pci_dev *physfn; /* the PF this VF is associated with */
374 struct pci_ats *ats; /* Address Translation Service */
376 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
377 size_t romlen; /* Length of ROM if it's not from the BAR */
378 char *driver_override; /* Driver name to force a match */
381 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
383 #ifdef CONFIG_PCI_IOV
390 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
392 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
393 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
395 static inline int pci_channel_offline(struct pci_dev *pdev)
397 return (pdev->error_state != pci_channel_io_normal);
400 struct pci_host_bridge_window {
401 struct list_head list;
402 struct resource *res; /* host bridge aperture (CPU address) */
403 resource_size_t offset; /* bus address + offset = CPU address */
406 struct pci_host_bridge {
408 struct pci_bus *bus; /* root bus */
409 struct list_head windows; /* pci_host_bridge_windows */
410 void (*release_fn)(struct pci_host_bridge *);
414 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
415 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
416 void (*release_fn)(struct pci_host_bridge *),
419 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
422 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
423 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
424 * buses below host bridges or subtractive decode bridges) go in the list.
425 * Use pci_bus_for_each_resource() to iterate through all the resources.
429 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
430 * and there's no way to program the bridge with the details of the window.
431 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
432 * decode bit set, because they are explicit and can be programmed with _SRS.
434 #define PCI_SUBTRACTIVE_DECODE 0x1
436 struct pci_bus_resource {
437 struct list_head list;
438 struct resource *res;
442 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
445 struct list_head node; /* node in list of buses */
446 struct pci_bus *parent; /* parent bus this bridge is on */
447 struct list_head children; /* list of child buses */
448 struct list_head devices; /* list of devices on this bus */
449 struct pci_dev *self; /* bridge device as seen by parent */
450 struct list_head slots; /* list of slots on this bus */
451 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
452 struct list_head resources; /* address space routed to this bus */
453 struct resource busn_res; /* bus numbers routed to this bus */
455 struct pci_ops *ops; /* configuration access functions */
456 struct msi_controller *msi; /* MSI controller */
457 void *sysdata; /* hook for sys-specific extension */
458 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
460 unsigned char number; /* bus number */
461 unsigned char primary; /* number of primary bridge */
462 unsigned char max_bus_speed; /* enum pci_bus_speed */
463 unsigned char cur_bus_speed; /* enum pci_bus_speed */
464 #ifdef CONFIG_PCI_DOMAINS_GENERIC
470 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
471 pci_bus_flags_t bus_flags; /* inherited by child buses */
472 struct device *bridge;
474 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
475 struct bin_attribute *legacy_mem; /* legacy mem */
476 unsigned int is_added:1;
479 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
482 * Returns true if the PCI bus is root (behind host-PCI bridge),
485 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
486 * This is incorrect because "virtual" buses added for SR-IOV (via
487 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
489 static inline bool pci_is_root_bus(struct pci_bus *pbus)
491 return !(pbus->parent);
495 * pci_is_bridge - check if the PCI device is a bridge
498 * Return true if the PCI device is bridge whether it has subordinate
501 static inline bool pci_is_bridge(struct pci_dev *dev)
503 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
504 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
507 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
509 dev = pci_physfn(dev);
510 if (pci_is_root_bus(dev->bus))
513 return dev->bus->self;
516 #ifdef CONFIG_PCI_MSI
517 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
519 return pci_dev->msi_enabled || pci_dev->msix_enabled;
522 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
526 * Error values that may be returned by PCI functions.
528 #define PCIBIOS_SUCCESSFUL 0x00
529 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
530 #define PCIBIOS_BAD_VENDOR_ID 0x83
531 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
532 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
533 #define PCIBIOS_SET_FAILED 0x88
534 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
537 * Translate above to generic errno for passing back through non-PCI code.
539 static inline int pcibios_err_to_errno(int err)
541 if (err <= PCIBIOS_SUCCESSFUL)
542 return err; /* Assume already errno */
545 case PCIBIOS_FUNC_NOT_SUPPORTED:
547 case PCIBIOS_BAD_VENDOR_ID:
549 case PCIBIOS_DEVICE_NOT_FOUND:
551 case PCIBIOS_BAD_REGISTER_NUMBER:
553 case PCIBIOS_SET_FAILED:
555 case PCIBIOS_BUFFER_TOO_SMALL:
562 /* Low-level architecture-dependent routines */
565 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
566 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
570 * ACPI needs to be able to access PCI config space before we've done a
571 * PCI bus scan and created pci_bus structures.
573 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
574 int reg, int len, u32 *val);
575 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
576 int reg, int len, u32 val);
578 struct pci_bus_region {
584 spinlock_t lock; /* protects list, index */
585 struct list_head list; /* for IDs added at runtime */
590 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
591 * a set of callbacks in struct pci_error_handlers, that device driver
592 * will be notified of PCI bus errors, and will be driven to recovery
593 * when an error occurs.
596 typedef unsigned int __bitwise pci_ers_result_t;
598 enum pci_ers_result {
599 /* no result/none/not supported in device driver */
600 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
602 /* Device driver can recover without slot reset */
603 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
605 /* Device driver wants slot to be reset. */
606 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
608 /* Device has completely failed, is unrecoverable */
609 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
611 /* Device driver is fully recovered and operational */
612 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
614 /* No AER capabilities registered for the driver */
615 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
618 /* PCI bus error event callbacks */
619 struct pci_error_handlers {
620 /* PCI bus error detected on this device */
621 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
622 enum pci_channel_state error);
624 /* MMIO has been re-enabled, but not DMA */
625 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
627 /* PCI Express link has been reset */
628 pci_ers_result_t (*link_reset)(struct pci_dev *dev);
630 /* PCI slot has been reset */
631 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
633 /* PCI function reset prepare or completed */
634 void (*reset_notify)(struct pci_dev *dev, bool prepare);
636 /* Device driver may resume normal operations */
637 void (*resume)(struct pci_dev *dev);
643 struct list_head node;
645 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
646 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
647 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
648 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
649 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
650 int (*resume_early) (struct pci_dev *dev);
651 int (*resume) (struct pci_dev *dev); /* Device woken up */
652 void (*shutdown) (struct pci_dev *dev);
653 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
654 const struct pci_error_handlers *err_handler;
655 struct device_driver driver;
656 struct pci_dynids dynids;
659 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
662 * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
663 * @_table: device table name
665 * This macro is deprecated and should not be used in new code.
667 #define DEFINE_PCI_DEVICE_TABLE(_table) \
668 const struct pci_device_id _table[]
671 * PCI_DEVICE - macro used to describe a specific pci device
672 * @vend: the 16 bit PCI Vendor ID
673 * @dev: the 16 bit PCI Device ID
675 * This macro is used to create a struct pci_device_id that matches a
676 * specific device. The subvendor and subdevice fields will be set to
679 #define PCI_DEVICE(vend,dev) \
680 .vendor = (vend), .device = (dev), \
681 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
684 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
685 * @vend: the 16 bit PCI Vendor ID
686 * @dev: the 16 bit PCI Device ID
687 * @subvend: the 16 bit PCI Subvendor ID
688 * @subdev: the 16 bit PCI Subdevice ID
690 * This macro is used to create a struct pci_device_id that matches a
691 * specific device with subsystem information.
693 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
694 .vendor = (vend), .device = (dev), \
695 .subvendor = (subvend), .subdevice = (subdev)
698 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
699 * @dev_class: the class, subclass, prog-if triple for this device
700 * @dev_class_mask: the class mask for this device
702 * This macro is used to create a struct pci_device_id that matches a
703 * specific PCI class. The vendor, device, subvendor, and subdevice
704 * fields will be set to PCI_ANY_ID.
706 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
707 .class = (dev_class), .class_mask = (dev_class_mask), \
708 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
709 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
712 * PCI_VDEVICE - macro used to describe a specific pci device in short form
713 * @vend: the vendor name
714 * @dev: the 16 bit PCI Device ID
716 * This macro is used to create a struct pci_device_id that matches a
717 * specific PCI device. The subvendor, and subdevice fields will be set
718 * to PCI_ANY_ID. The macro allows the next field to follow as the device
722 #define PCI_VDEVICE(vend, dev) \
723 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
724 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
726 /* these external functions are only available when PCI support is enabled */
729 void pcie_bus_configure_settings(struct pci_bus *bus);
731 enum pcie_bus_config_types {
734 PCIE_BUS_PERFORMANCE,
738 extern enum pcie_bus_config_types pcie_bus_config;
740 extern struct bus_type pci_bus_type;
742 /* Do NOT directly access these two variables, unless you are arch-specific PCI
743 * code, or PCI core code. */
744 extern struct list_head pci_root_buses; /* list of all known PCI buses */
745 /* Some device drivers need know if PCI is initiated */
746 int no_pci_devices(void);
748 void pcibios_resource_survey_bus(struct pci_bus *bus);
749 void pcibios_add_bus(struct pci_bus *bus);
750 void pcibios_remove_bus(struct pci_bus *bus);
751 void pcibios_fixup_bus(struct pci_bus *);
752 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
753 /* Architecture-specific versions may override this (weak) */
754 char *pcibios_setup(char *str);
756 /* Used only when drivers/pci/setup.c is used */
757 resource_size_t pcibios_align_resource(void *, const struct resource *,
760 void pcibios_update_irq(struct pci_dev *, int irq);
762 /* Weak but can be overriden by arch */
763 void pci_fixup_cardbus(struct pci_bus *);
765 /* Generic PCI functions used internally */
767 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
768 struct resource *res);
769 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
770 struct pci_bus_region *region);
771 void pcibios_scan_specific_bus(int busn);
772 struct pci_bus *pci_find_bus(int domain, int busnr);
773 void pci_bus_add_devices(const struct pci_bus *bus);
774 struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus,
775 struct pci_ops *ops, void *sysdata);
776 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
777 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
778 struct pci_ops *ops, void *sysdata,
779 struct list_head *resources);
780 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
781 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
782 void pci_bus_release_busn_res(struct pci_bus *b);
783 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
784 struct pci_ops *ops, void *sysdata,
785 struct list_head *resources);
786 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
788 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
789 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
791 struct hotplug_slot *hotplug);
792 void pci_destroy_slot(struct pci_slot *slot);
793 int pci_scan_slot(struct pci_bus *bus, int devfn);
794 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
795 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
796 unsigned int pci_scan_child_bus(struct pci_bus *bus);
797 void pci_bus_add_device(struct pci_dev *dev);
798 void pci_read_bridge_bases(struct pci_bus *child);
799 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
800 struct resource *res);
801 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
802 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
803 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
804 struct pci_dev *pci_dev_get(struct pci_dev *dev);
805 void pci_dev_put(struct pci_dev *dev);
806 void pci_remove_bus(struct pci_bus *b);
807 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
808 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
809 void pci_stop_root_bus(struct pci_bus *bus);
810 void pci_remove_root_bus(struct pci_bus *bus);
811 void pci_setup_cardbus(struct pci_bus *bus);
812 void pci_sort_breadthfirst(void);
813 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
814 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
815 #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0))
817 /* Generic PCI functions exported to card drivers */
819 enum pci_lost_interrupt_reason {
820 PCI_LOST_IRQ_NO_INFORMATION = 0,
821 PCI_LOST_IRQ_DISABLE_MSI,
822 PCI_LOST_IRQ_DISABLE_MSIX,
823 PCI_LOST_IRQ_DISABLE_ACPI,
825 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
826 int pci_find_capability(struct pci_dev *dev, int cap);
827 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
828 int pci_find_ext_capability(struct pci_dev *dev, int cap);
829 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
830 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
831 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
832 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
834 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
835 struct pci_dev *from);
836 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
837 unsigned int ss_vendor, unsigned int ss_device,
838 struct pci_dev *from);
839 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
840 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
842 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
845 return pci_get_domain_bus_and_slot(0, bus, devfn);
847 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
848 int pci_dev_present(const struct pci_device_id *ids);
850 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
852 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
853 int where, u16 *val);
854 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
855 int where, u32 *val);
856 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
858 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
860 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
862 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
864 static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
866 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
868 static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
870 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
872 static inline int pci_read_config_dword(const struct pci_dev *dev, int where,
875 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
877 static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
879 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
881 static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
883 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
885 static inline int pci_write_config_dword(const struct pci_dev *dev, int where,
888 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
891 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
892 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
893 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
894 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
895 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
897 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
900 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
903 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
906 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
909 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
912 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
915 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
918 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
921 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
924 /* user-space driven config access */
925 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
926 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
927 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
928 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
929 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
930 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
932 int __must_check pci_enable_device(struct pci_dev *dev);
933 int __must_check pci_enable_device_io(struct pci_dev *dev);
934 int __must_check pci_enable_device_mem(struct pci_dev *dev);
935 int __must_check pci_reenable_device(struct pci_dev *);
936 int __must_check pcim_enable_device(struct pci_dev *pdev);
937 void pcim_pin_device(struct pci_dev *pdev);
939 static inline int pci_is_enabled(struct pci_dev *pdev)
941 return (atomic_read(&pdev->enable_cnt) > 0);
944 static inline int pci_is_managed(struct pci_dev *pdev)
946 return pdev->is_managed;
949 void pci_disable_device(struct pci_dev *dev);
951 extern unsigned int pcibios_max_latency;
952 void pci_set_master(struct pci_dev *dev);
953 void pci_clear_master(struct pci_dev *dev);
955 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
956 int pci_set_cacheline_size(struct pci_dev *dev);
957 #define HAVE_PCI_SET_MWI
958 int __must_check pci_set_mwi(struct pci_dev *dev);
959 int pci_try_set_mwi(struct pci_dev *dev);
960 void pci_clear_mwi(struct pci_dev *dev);
961 void pci_intx(struct pci_dev *dev, int enable);
962 bool pci_intx_mask_supported(struct pci_dev *dev);
963 bool pci_check_and_mask_intx(struct pci_dev *dev);
964 bool pci_check_and_unmask_intx(struct pci_dev *dev);
965 void pci_msi_off(struct pci_dev *dev);
966 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size);
967 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask);
968 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
969 int pci_wait_for_pending_transaction(struct pci_dev *dev);
970 int pcix_get_max_mmrbc(struct pci_dev *dev);
971 int pcix_get_mmrbc(struct pci_dev *dev);
972 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
973 int pcie_get_readrq(struct pci_dev *dev);
974 int pcie_set_readrq(struct pci_dev *dev, int rq);
975 int pcie_get_mps(struct pci_dev *dev);
976 int pcie_set_mps(struct pci_dev *dev, int mps);
977 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
978 enum pcie_link_width *width);
979 int __pci_reset_function(struct pci_dev *dev);
980 int __pci_reset_function_locked(struct pci_dev *dev);
981 int pci_reset_function(struct pci_dev *dev);
982 int pci_try_reset_function(struct pci_dev *dev);
983 int pci_probe_reset_slot(struct pci_slot *slot);
984 int pci_reset_slot(struct pci_slot *slot);
985 int pci_try_reset_slot(struct pci_slot *slot);
986 int pci_probe_reset_bus(struct pci_bus *bus);
987 int pci_reset_bus(struct pci_bus *bus);
988 int pci_try_reset_bus(struct pci_bus *bus);
989 void pci_reset_secondary_bus(struct pci_dev *dev);
990 void pcibios_reset_secondary_bus(struct pci_dev *dev);
991 void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
992 void pci_update_resource(struct pci_dev *dev, int resno);
993 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
994 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
995 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
996 bool pci_device_is_present(struct pci_dev *pdev);
998 /* ROM control related routines */
999 int pci_enable_rom(struct pci_dev *pdev);
1000 void pci_disable_rom(struct pci_dev *pdev);
1001 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1002 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1003 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
1004 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1006 /* Power management related routines */
1007 int pci_save_state(struct pci_dev *dev);
1008 void pci_restore_state(struct pci_dev *dev);
1009 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1010 int pci_load_saved_state(struct pci_dev *dev,
1011 struct pci_saved_state *state);
1012 int pci_load_and_free_saved_state(struct pci_dev *dev,
1013 struct pci_saved_state **state);
1014 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1015 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1017 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1018 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1019 u16 cap, unsigned int size);
1020 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1021 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1022 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1023 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1024 void pci_pme_active(struct pci_dev *dev, bool enable);
1025 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1026 bool runtime, bool enable);
1027 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1028 int pci_prepare_to_sleep(struct pci_dev *dev);
1029 int pci_back_from_sleep(struct pci_dev *dev);
1030 bool pci_dev_run_wake(struct pci_dev *dev);
1031 bool pci_check_pme_status(struct pci_dev *dev);
1032 void pci_pme_wakeup_bus(struct pci_bus *bus);
1034 static inline void pci_ignore_hotplug(struct pci_dev *dev)
1036 dev->ignore_hotplug = 1;
1039 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1042 return __pci_enable_wake(dev, state, false, enable);
1045 /* PCI Virtual Channel */
1046 int pci_save_vc_state(struct pci_dev *dev);
1047 void pci_restore_vc_state(struct pci_dev *dev);
1048 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1050 /* For use by arch with custom probe code */
1051 void set_pcie_port_type(struct pci_dev *pdev);
1052 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1054 /* Functions for PCI Hotplug drivers to use */
1055 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1056 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1057 unsigned int pci_rescan_bus(struct pci_bus *bus);
1058 void pci_lock_rescan_remove(void);
1059 void pci_unlock_rescan_remove(void);
1061 /* Vital product data routines */
1062 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1063 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1065 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1066 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1067 void pci_bus_assign_resources(const struct pci_bus *bus);
1068 void pci_bus_size_bridges(struct pci_bus *bus);
1069 int pci_claim_resource(struct pci_dev *, int);
1070 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1071 void pci_assign_unassigned_resources(void);
1072 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1073 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1074 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1075 void pdev_enable_device(struct pci_dev *);
1076 int pci_enable_resources(struct pci_dev *, int mask);
1077 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
1078 int (*)(const struct pci_dev *, u8, u8));
1079 #define HAVE_PCI_REQ_REGIONS 2
1080 int __must_check pci_request_regions(struct pci_dev *, const char *);
1081 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1082 void pci_release_regions(struct pci_dev *);
1083 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1084 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1085 void pci_release_region(struct pci_dev *, int);
1086 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1087 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1088 void pci_release_selected_regions(struct pci_dev *, int);
1090 /* drivers/pci/bus.c */
1091 struct pci_bus *pci_bus_get(struct pci_bus *bus);
1092 void pci_bus_put(struct pci_bus *bus);
1093 void pci_add_resource(struct list_head *resources, struct resource *res);
1094 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1095 resource_size_t offset);
1096 void pci_free_resource_list(struct list_head *resources);
1097 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags);
1098 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1099 void pci_bus_remove_resources(struct pci_bus *bus);
1101 #define pci_bus_for_each_resource(bus, res, i) \
1103 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1106 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1107 struct resource *res, resource_size_t size,
1108 resource_size_t align, resource_size_t min,
1109 unsigned long type_mask,
1110 resource_size_t (*alignf)(void *,
1111 const struct resource *,
1117 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1119 static inline dma_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1121 struct pci_bus_region region;
1123 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1124 return region.start;
1127 /* Proper probing supporting hot-pluggable devices */
1128 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1129 const char *mod_name);
1132 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1134 #define pci_register_driver(driver) \
1135 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1137 void pci_unregister_driver(struct pci_driver *dev);
1140 * module_pci_driver() - Helper macro for registering a PCI driver
1141 * @__pci_driver: pci_driver struct
1143 * Helper macro for PCI drivers which do not do anything special in module
1144 * init/exit. This eliminates a lot of boilerplate. Each module may only
1145 * use this macro once, and calling it replaces module_init() and module_exit()
1147 #define module_pci_driver(__pci_driver) \
1148 module_driver(__pci_driver, pci_register_driver, \
1149 pci_unregister_driver)
1151 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1152 int pci_add_dynid(struct pci_driver *drv,
1153 unsigned int vendor, unsigned int device,
1154 unsigned int subvendor, unsigned int subdevice,
1155 unsigned int class, unsigned int class_mask,
1156 unsigned long driver_data);
1157 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1158 struct pci_dev *dev);
1159 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1162 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1164 int pci_cfg_space_size(struct pci_dev *dev);
1165 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1166 void pci_setup_bridge(struct pci_bus *bus);
1167 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1168 unsigned long type);
1170 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1171 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1173 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1174 unsigned int command_bits, u32 flags);
1175 /* kmem_cache style wrapper around pci_alloc_consistent() */
1177 #include <linux/pci-dma.h>
1178 #include <linux/dmapool.h>
1180 #define pci_pool dma_pool
1181 #define pci_pool_create(name, pdev, size, align, allocation) \
1182 dma_pool_create(name, &pdev->dev, size, align, allocation)
1183 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1184 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1185 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1187 enum pci_dma_burst_strategy {
1188 PCI_DMA_BURST_INFINITY, /* make bursts as large as possible,
1189 strategy_parameter is N/A */
1190 PCI_DMA_BURST_BOUNDARY, /* disconnect at every strategy_parameter
1192 PCI_DMA_BURST_MULTIPLE, /* disconnect at some multiple of
1193 strategy_parameter byte boundaries */
1197 u32 vector; /* kernel uses to write allocated vector */
1198 u16 entry; /* driver uses to specify entry, OS writes */
1202 #ifdef CONFIG_PCI_MSI
1203 int pci_msi_vec_count(struct pci_dev *dev);
1204 void pci_msi_shutdown(struct pci_dev *dev);
1205 void pci_disable_msi(struct pci_dev *dev);
1206 int pci_msix_vec_count(struct pci_dev *dev);
1207 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec);
1208 void pci_msix_shutdown(struct pci_dev *dev);
1209 void pci_disable_msix(struct pci_dev *dev);
1210 void pci_restore_msi_state(struct pci_dev *dev);
1211 int pci_msi_enabled(void);
1212 int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec);
1213 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1215 int rc = pci_enable_msi_range(dev, nvec, nvec);
1220 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1221 int minvec, int maxvec);
1222 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1223 struct msix_entry *entries, int nvec)
1225 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1231 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1232 static inline void pci_msi_shutdown(struct pci_dev *dev) { }
1233 static inline void pci_disable_msi(struct pci_dev *dev) { }
1234 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1235 static inline int pci_enable_msix(struct pci_dev *dev,
1236 struct msix_entry *entries, int nvec)
1238 static inline void pci_msix_shutdown(struct pci_dev *dev) { }
1239 static inline void pci_disable_msix(struct pci_dev *dev) { }
1240 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1241 static inline int pci_msi_enabled(void) { return 0; }
1242 static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec,
1245 static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec)
1247 static inline int pci_enable_msix_range(struct pci_dev *dev,
1248 struct msix_entry *entries, int minvec, int maxvec)
1250 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1251 struct msix_entry *entries, int nvec)
1255 #ifdef CONFIG_PCIEPORTBUS
1256 extern bool pcie_ports_disabled;
1257 extern bool pcie_ports_auto;
1259 #define pcie_ports_disabled true
1260 #define pcie_ports_auto false
1263 #ifdef CONFIG_PCIEASPM
1264 bool pcie_aspm_support_enabled(void);
1266 static inline bool pcie_aspm_support_enabled(void) { return false; }
1269 #ifdef CONFIG_PCIEAER
1270 void pci_no_aer(void);
1271 bool pci_aer_available(void);
1273 static inline void pci_no_aer(void) { }
1274 static inline bool pci_aer_available(void) { return false; }
1277 #ifdef CONFIG_PCIE_ECRC
1278 void pcie_set_ecrc_checking(struct pci_dev *dev);
1279 void pcie_ecrc_get_policy(char *str);
1281 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1282 static inline void pcie_ecrc_get_policy(char *str) { }
1285 #define pci_enable_msi(pdev) pci_enable_msi_exact(pdev, 1)
1287 #ifdef CONFIG_HT_IRQ
1288 /* The functions a driver should call */
1289 int ht_create_irq(struct pci_dev *dev, int idx);
1290 void ht_destroy_irq(unsigned int irq);
1291 #endif /* CONFIG_HT_IRQ */
1293 void pci_cfg_access_lock(struct pci_dev *dev);
1294 bool pci_cfg_access_trylock(struct pci_dev *dev);
1295 void pci_cfg_access_unlock(struct pci_dev *dev);
1298 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1299 * a PCI domain is defined to be a set of PCI buses which share
1300 * configuration space.
1302 #ifdef CONFIG_PCI_DOMAINS
1303 extern int pci_domains_supported;
1304 int pci_get_new_domain_nr(void);
1306 enum { pci_domains_supported = 0 };
1307 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1308 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1309 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1310 #endif /* CONFIG_PCI_DOMAINS */
1313 * Generic implementation for PCI domain support. If your
1314 * architecture does not need custom management of PCI
1315 * domains then this implementation will be used
1317 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1318 static inline int pci_domain_nr(struct pci_bus *bus)
1320 return bus->domain_nr;
1322 void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent);
1324 static inline void pci_bus_assign_domain_nr(struct pci_bus *bus,
1325 struct device *parent)
1330 /* some architectures require additional setup to direct VGA traffic */
1331 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1332 unsigned int command_bits, u32 flags);
1333 void pci_register_set_vga_state(arch_set_vga_state_t func);
1335 #else /* CONFIG_PCI is not enabled */
1338 * If the system does not have PCI, clearly these return errors. Define
1339 * these as simple inline functions to avoid hair in drivers.
1342 #define _PCI_NOP(o, s, t) \
1343 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1345 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1347 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1348 _PCI_NOP(o, word, u16 x) \
1349 _PCI_NOP(o, dword, u32 x)
1350 _PCI_NOP_ALL(read, *)
1351 _PCI_NOP_ALL(write,)
1353 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1354 unsigned int device,
1355 struct pci_dev *from)
1358 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1359 unsigned int device,
1360 unsigned int ss_vendor,
1361 unsigned int ss_device,
1362 struct pci_dev *from)
1365 static inline struct pci_dev *pci_get_class(unsigned int class,
1366 struct pci_dev *from)
1369 #define pci_dev_present(ids) (0)
1370 #define no_pci_devices() (1)
1371 #define pci_dev_put(dev) do { } while (0)
1373 static inline void pci_set_master(struct pci_dev *dev) { }
1374 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1375 static inline void pci_disable_device(struct pci_dev *dev) { }
1376 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
1378 static inline int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
1380 static inline int pci_set_dma_max_seg_size(struct pci_dev *dev,
1383 static inline int pci_set_dma_seg_boundary(struct pci_dev *dev,
1386 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1388 static inline int __pci_register_driver(struct pci_driver *drv,
1389 struct module *owner)
1391 static inline int pci_register_driver(struct pci_driver *drv)
1393 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1394 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1396 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1399 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1402 /* Power management related routines */
1403 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1404 static inline void pci_restore_state(struct pci_dev *dev) { }
1405 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1407 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1409 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1412 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1416 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1418 static inline void pci_release_regions(struct pci_dev *dev) { }
1420 #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0)
1422 static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1423 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1425 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1427 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1429 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1432 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1436 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1437 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1438 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1440 #define dev_is_pci(d) (false)
1441 #define dev_is_pf(d) (false)
1442 #define dev_num_vf(d) (0)
1443 #endif /* CONFIG_PCI */
1445 /* Include architecture-dependent settings and functions */
1447 #include <asm/pci.h>
1449 /* these helpers provide future and backwards compatibility
1450 * for accessing popular PCI BAR info */
1451 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1452 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1453 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1454 #define pci_resource_len(dev,bar) \
1455 ((pci_resource_start((dev), (bar)) == 0 && \
1456 pci_resource_end((dev), (bar)) == \
1457 pci_resource_start((dev), (bar))) ? 0 : \
1459 (pci_resource_end((dev), (bar)) - \
1460 pci_resource_start((dev), (bar)) + 1))
1462 /* Similar to the helpers above, these manipulate per-pci_dev
1463 * driver-specific data. They are really just a wrapper around
1464 * the generic device structure functions of these calls.
1466 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1468 return dev_get_drvdata(&pdev->dev);
1471 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1473 dev_set_drvdata(&pdev->dev, data);
1476 /* If you want to know what to call your pci_dev, ask this function.
1477 * Again, it's a wrapper around the generic device.
1479 static inline const char *pci_name(const struct pci_dev *pdev)
1481 return dev_name(&pdev->dev);
1485 /* Some archs don't want to expose struct resource to userland as-is
1486 * in sysfs and /proc
1488 #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER
1489 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1490 const struct resource *rsrc, resource_size_t *start,
1491 resource_size_t *end)
1493 *start = rsrc->start;
1496 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1500 * The world is not perfect and supplies us with broken PCI devices.
1501 * For at least a part of these bugs we need a work-around, so both
1502 * generic (drivers/pci/quirks.c) and per-architecture code can define
1503 * fixup hooks to be called for particular buggy devices.
1507 u16 vendor; /* You can use PCI_ANY_ID here of course */
1508 u16 device; /* You can use PCI_ANY_ID here of course */
1509 u32 class; /* You can use PCI_ANY_ID here too */
1510 unsigned int class_shift; /* should be 0, 8, 16 */
1511 void (*hook)(struct pci_dev *dev);
1514 enum pci_fixup_pass {
1515 pci_fixup_early, /* Before probing BARs */
1516 pci_fixup_header, /* After reading configuration header */
1517 pci_fixup_final, /* Final phase of device fixups */
1518 pci_fixup_enable, /* pci_enable_device() time */
1519 pci_fixup_resume, /* pci_device_resume() */
1520 pci_fixup_suspend, /* pci_device_suspend() */
1521 pci_fixup_resume_early, /* pci_device_resume_early() */
1522 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1525 /* Anonymous variables would be nice... */
1526 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1527 class_shift, hook) \
1528 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1529 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1530 = { vendor, device, class, class_shift, hook };
1532 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1533 class_shift, hook) \
1534 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1535 hook, vendor, device, class, class_shift, hook)
1536 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1537 class_shift, hook) \
1538 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1539 hook, vendor, device, class, class_shift, hook)
1540 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1541 class_shift, hook) \
1542 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1543 hook, vendor, device, class, class_shift, hook)
1544 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1545 class_shift, hook) \
1546 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1547 hook, vendor, device, class, class_shift, hook)
1548 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1549 class_shift, hook) \
1550 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1551 resume##hook, vendor, device, class, \
1553 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1554 class_shift, hook) \
1555 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1556 resume_early##hook, vendor, device, \
1557 class, class_shift, hook)
1558 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1559 class_shift, hook) \
1560 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1561 suspend##hook, vendor, device, class, \
1563 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1564 class_shift, hook) \
1565 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1566 suspend_late##hook, vendor, device, \
1567 class, class_shift, hook)
1569 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1570 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1571 hook, vendor, device, PCI_ANY_ID, 0, hook)
1572 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1573 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1574 hook, vendor, device, PCI_ANY_ID, 0, hook)
1575 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1576 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1577 hook, vendor, device, PCI_ANY_ID, 0, hook)
1578 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1579 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1580 hook, vendor, device, PCI_ANY_ID, 0, hook)
1581 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1582 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1583 resume##hook, vendor, device, \
1584 PCI_ANY_ID, 0, hook)
1585 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1586 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1587 resume_early##hook, vendor, device, \
1588 PCI_ANY_ID, 0, hook)
1589 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1590 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1591 suspend##hook, vendor, device, \
1592 PCI_ANY_ID, 0, hook)
1593 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1594 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1595 suspend_late##hook, vendor, device, \
1596 PCI_ANY_ID, 0, hook)
1598 #ifdef CONFIG_PCI_QUIRKS
1599 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1600 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1601 void pci_dev_specific_enable_acs(struct pci_dev *dev);
1603 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1604 struct pci_dev *dev) { }
1605 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1610 static inline void pci_dev_specific_enable_acs(struct pci_dev *dev) { }
1613 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1614 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1615 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1616 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1617 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1619 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1621 extern int pci_pci_problems;
1622 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1623 #define PCIPCI_TRITON 2
1624 #define PCIPCI_NATOMA 4
1625 #define PCIPCI_VIAETBF 8
1626 #define PCIPCI_VSFX 16
1627 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1628 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1630 extern unsigned long pci_cardbus_io_size;
1631 extern unsigned long pci_cardbus_mem_size;
1632 extern u8 pci_dfl_cache_line_size;
1633 extern u8 pci_cache_line_size;
1635 extern unsigned long pci_hotplug_io_size;
1636 extern unsigned long pci_hotplug_mem_size;
1638 /* Architecture-specific versions may override these (weak) */
1639 void pcibios_disable_device(struct pci_dev *dev);
1640 void pcibios_set_master(struct pci_dev *dev);
1641 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1642 enum pcie_reset_state state);
1643 int pcibios_add_device(struct pci_dev *dev);
1644 void pcibios_release_device(struct pci_dev *dev);
1645 void pcibios_penalize_isa_irq(int irq, int active);
1647 #ifdef CONFIG_HIBERNATE_CALLBACKS
1648 extern struct dev_pm_ops pcibios_pm_ops;
1651 #ifdef CONFIG_PCI_MMCONFIG
1652 void __init pci_mmcfg_early_init(void);
1653 void __init pci_mmcfg_late_init(void);
1655 static inline void pci_mmcfg_early_init(void) { }
1656 static inline void pci_mmcfg_late_init(void) { }
1659 int pci_ext_cfg_avail(void);
1661 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1663 #ifdef CONFIG_PCI_IOV
1664 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1665 void pci_disable_sriov(struct pci_dev *dev);
1666 int pci_num_vf(struct pci_dev *dev);
1667 int pci_vfs_assigned(struct pci_dev *dev);
1668 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1669 int pci_sriov_get_totalvfs(struct pci_dev *dev);
1671 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1673 static inline void pci_disable_sriov(struct pci_dev *dev) { }
1674 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
1675 static inline int pci_vfs_assigned(struct pci_dev *dev)
1677 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1679 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1683 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1684 void pci_hp_create_module_link(struct pci_slot *pci_slot);
1685 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1689 * pci_pcie_cap - get the saved PCIe capability offset
1692 * PCIe capability offset is calculated at PCI device initialization
1693 * time and saved in the data structure. This function returns saved
1694 * PCIe capability offset. Using this instead of pci_find_capability()
1695 * reduces unnecessary search in the PCI configuration space. If you
1696 * need to calculate PCIe capability offset from raw device for some
1697 * reasons, please use pci_find_capability() instead.
1699 static inline int pci_pcie_cap(struct pci_dev *dev)
1701 return dev->pcie_cap;
1705 * pci_is_pcie - check if the PCI device is PCI Express capable
1708 * Returns: true if the PCI device is PCI Express capable, false otherwise.
1710 static inline bool pci_is_pcie(struct pci_dev *dev)
1712 return pci_pcie_cap(dev);
1716 * pcie_caps_reg - get the PCIe Capabilities Register
1719 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
1721 return dev->pcie_flags_reg;
1725 * pci_pcie_type - get the PCIe device/port type
1728 static inline int pci_pcie_type(const struct pci_dev *dev)
1730 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
1733 void pci_request_acs(void);
1734 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
1735 bool pci_acs_path_enabled(struct pci_dev *start,
1736 struct pci_dev *end, u16 acs_flags);
1738 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
1739 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
1741 /* Large Resource Data Type Tag Item Names */
1742 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
1743 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
1744 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
1746 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
1747 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
1748 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
1750 /* Small Resource Data Type Tag Item Names */
1751 #define PCI_VPD_STIN_END 0x78 /* End */
1753 #define PCI_VPD_SRDT_END PCI_VPD_STIN_END
1755 #define PCI_VPD_SRDT_TIN_MASK 0x78
1756 #define PCI_VPD_SRDT_LEN_MASK 0x07
1758 #define PCI_VPD_LRDT_TAG_SIZE 3
1759 #define PCI_VPD_SRDT_TAG_SIZE 1
1761 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
1763 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
1764 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
1765 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
1766 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
1769 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
1770 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
1772 * Returns the extracted Large Resource Data Type length.
1774 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
1776 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
1780 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
1781 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
1783 * Returns the extracted Small Resource Data Type length.
1785 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
1787 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
1791 * pci_vpd_info_field_size - Extracts the information field length
1792 * @lrdt: Pointer to the beginning of an information field header
1794 * Returns the extracted information field length.
1796 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
1798 return info_field[2];
1802 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
1803 * @buf: Pointer to buffered vpd data
1804 * @off: The offset into the buffer at which to begin the search
1805 * @len: The length of the vpd buffer
1806 * @rdt: The Resource Data Type to search for
1808 * Returns the index where the Resource Data Type was found or
1809 * -ENOENT otherwise.
1811 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
1814 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
1815 * @buf: Pointer to buffered vpd data
1816 * @off: The offset into the buffer at which to begin the search
1817 * @len: The length of the buffer area, relative to off, in which to search
1818 * @kw: The keyword to search for
1820 * Returns the index where the information field keyword was found or
1821 * -ENOENT otherwise.
1823 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
1824 unsigned int len, const char *kw);
1826 /* PCI <-> OF binding helpers */
1829 void pci_set_of_node(struct pci_dev *dev);
1830 void pci_release_of_node(struct pci_dev *dev);
1831 void pci_set_bus_of_node(struct pci_bus *bus);
1832 void pci_release_bus_of_node(struct pci_bus *bus);
1834 /* Arch may override this (weak) */
1835 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
1837 static inline struct device_node *
1838 pci_device_to_OF_node(const struct pci_dev *pdev)
1840 return pdev ? pdev->dev.of_node : NULL;
1843 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
1845 return bus ? bus->dev.of_node : NULL;
1848 #else /* CONFIG_OF */
1849 static inline void pci_set_of_node(struct pci_dev *dev) { }
1850 static inline void pci_release_of_node(struct pci_dev *dev) { }
1851 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
1852 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
1853 #endif /* CONFIG_OF */
1856 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
1858 return pdev->dev.archdata.edev;
1862 int pci_for_each_dma_alias(struct pci_dev *pdev,
1863 int (*fn)(struct pci_dev *pdev,
1864 u16 alias, void *data), void *data);
1866 /* helper functions for operation of device flag */
1867 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
1869 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
1871 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
1873 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
1875 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
1877 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
1879 #endif /* LINUX_PCI_H */